Assignment Lab 4 Carry Look-ahead Adder/Subtractor and Hazard Free Design
Due February 28, Thursday, 1:00pm Introduction:
This lab assignment consists of two parts: (1) Implementation of a carry look-ahead excess-3 adder/subtractor, and (2) Hazard analysis and implementation of hazard-free circuits.
Part 1: Carry look-ahead excess-3 adder/subtractor
In Part 2 of your Lab 3 assignment, you have implemented an excess-3 adder using a 4-bit binary adder and a constant-3 adder/subtractor that you have designed. In this part of the lab, you will be designing a carry look-ahead adder/subtractor for excess-3 numbers of 4 decimal digits. The interesting part of a binary carry look-ahead adder is that it can in some sense precompute the carries of each bit, thus drastically speeding up the overall adder through enabling a number of operations to happen concurrently. One of the questions that this lab assignment tries to get you to address is whether the same idea of precomputation of carries is applicable to decimal adders, say ones that are encoded in excess-3 representation. The write-up explains how to approach this problem so that you can design a circuit that can speedily add (or subtract) two 4digit decimal numbers. The challenges for you will be concentrated in two parts; primarily, you need to think about how the excess-3 representation (instead of binary) impacts the applicability of the carry look ahead techniques we outline here and are described in detail in the textbook. Secondly, you need to think about how to incorporate subtraction capabilities in your circuit in addition to addition. You will find that the second part of your previous lab assignment should be of help with some of these issues. Carry look-ahead binary adder You have learned from your textbook that a single bit full adder (FA) takes as inputs two operands xi, yi and the carry ci, and produces as outputs the sum si and carry ci+1. An n-bit binary adder can be implemented as a serial connection of FAs, arranged such that the output carry of each FA serves as the input carry for the next-higher significant FA. This type of adder is denoted as ripple-carry adder, since any change in the least significant bits c0, x0, or y0 has to ripple through all the FAs. One important feature of an adder is its delay, that is, the time it takes for it to output the sum and carry. For a ripple-carry adder, each FA needs to wait for the next-lower significant FA for generating the carry, thus imposing a significant limitation on the speed of this type of adder. The purpose of designing a carry look-ahead adder is to reduce the delay of the carry chain in a ripple-carry adder. This technique takes advantage of the fact that the major part of the expressions of each carry in the chain can be precomputed. Let's take as an example a 4-bit adder that computes x3x2x1x0 + y3y2y1y0 + c0. We first define two functions as follows: (1) the carry-generate function gi = xiyi, and (2) the carry-propagate function pi = xi yi. Using these two functions, the four carries c1, ..., c4 can be expressed as follows: c1 = g0 + p0c0 c2 = g1 + p1c1 = g1 + p1(g0 + p0c0) = g1 + p1g0 + p1p0c0 c3 = g2 + p2c2 = g2 + p2g1 + p2p1g0 + p2p1p0c0 (1) (2) (3)
c4 = g3 + p3c3 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0
(4)
These four equations show that the four carries c1, ..., c4 can be computed directly from input bits x3x2x1x0, y3y2y1y0, and input carry c0 without the ripple effect! In other words, the carry value for each bit can be generated in parallel, which in turn allows the addition of each bit to be performed in parallel, thus drastically speeding up the completion delay of the overall adder! The principle and structure of carry look-ahead adders are discussed in detail in Section 5.2 of your textbook. In general, a carry look-ahead adder circuit consists of three parts: Carry-generate functions and carry-propagate functions for every bit: the carrygenerate function gi = xiyi determines whether the two input values xi and yi will generate a carry to a higher bit, while the carry-propagate function pi = xi yi determines whether the two input values can propagate a carry coming from a lower bit to a higher bit. A carry look-ahead (CLA) generator: the CLA logic takes as inputs the carry-generate and carry-propagate functions of each bit, and generates the carry value for each bit in parallel using Equations (1)-(4). 1-bit half adders for every bit: each adder takes as inputs the carry- generate function gi and the carry value ci (generated by the CLA logic), and generates the sum si = gi ci.
Carry look-ahead excess-3 adder We have discussed the implementation of a 4-bit CLA binary adder. As you have learned in Part 2 of your Lab 3 assignment, a 4-bit CLA binary adder and a constant-3 adder/subtractor can be hooked together to implement an excess-3 adder for adding two decimal digits in excess-3 representation. Furthermore, the addition of two 4-digit decimal excess-3 numbers can be performed by four excess-3 adders of this type, as long as the carry-in value of each excess-3 adder can be generated correctly. Therefore, the question we need to consider is how the carryin value for each of these four adders can be computed. Fundamentally, for each decimal digit, an excess-3 carry should be propagated to the higher bit if the excess-3 sum is larger than 9. As our excess-3 adder is implemented using a 4-bit CLA binary adder and a constant-3 adder/subtractor, we have two additional signals in our hand: the binary sum and the binary carry. We have already examined the relationship between the binary sum and the excess-3 sum in the second part of your Lab 3 assignment. Now let's examine the relationship between the binary carry and the excess-3 carry. The following table shows two boundary cases regarding the values of these two signals. 1st input 2nd input Excess-3 sum Excess-3 carry Binary sum Binary carry 0111(4) 1000(5) 1100 (9) 0 1111 0 0110(3) 1010(7) 0011 (0) 1 0000 1 As you can see, while the offset value between the binary sum and the excess-3 sum is 3, the binary carry and the excess-3 carry are identical. This implies that the exact logic for generating the binary carry can be used to generate the excess-3 carry without any modification! Accordingly, the 4-digit adder for excess-3 numbers can be implemented using a 16-bit (4*4) CLA binary adder and four constant-3 adders/subtractors that you have designed in Lab 3. The values of excess-3 carries can be handled perfectly by the 16-bit CLA binary adder, while the excess-3 sums can be generated by adding/subtracting 3 to/from every 4-bit binary sum. Equations (1)-(4) show the precomputation of carries for a 4-bit binary adder. It is possible to think that the idea can be extended to implement a 16-bit CLA binary adder. However, because of fan-in and fan-out limitations, it is practically infeasible to extend Equations (1)-(4) to 16 bits. Therefore, in this part of the lab, we will use two other methods to implement a 16-bit CLA
binary adder. The simpler method just connects four 4-bit CLA binary adders in serial such that the carry-out of each CLA adder serves as the carry-in of the next-higher significant CLA adder. This 16-bit binary adder is denoted as a single-level CLA adder since it is constructed in such a way that carries inside each 4-bit adder are computed by a CLA generator based on the values of g's, p's, while the 4-bit carries c4, c8, c12, and c16 ripple through the 4-bit slices. The advantage of this method is that it requires no extra hardware besides the four 4-bit CLA adders. However, each 4-bit CLA adder still needs to wait for the next-lower significant CLA adder to generate the carry, thus limiting the speed of this adder. In contrast, the somewhat more complicated but faster method, the two-level CLA adder, uses an extra CLA generator in addition to the four 4-bit CLA adders in order to speed up the generation of 4-bit carries c4, c8, c12, and c16. Equations (1)-(4) show that the ci+1 formulatyion can be exploited to help us precompute the 4 carries ci+1, ..., ci+4. In an analogous manner, if we can cast the relationship between ci+4 and ci into a similar equation such that ci+4 = g(i,i+3)+ p(i, i+3)ci, we can use a set of equations similar to (1)-(4) to precompute the 4 carries c4, c8, c12, and c16 based on the value of c0. The critical part of the second level CLA logic is to find the variables g(i, i+3) and p(i, i+3). But a moment's reflection should show that these variables can be easily derived from Equation (4). Let's first get g(0,3) and p(0,3). Equation (4) can be rewritten as follows: c4 = g(0,3) + p(0,3)c0 (5) in which g(0,3) = g3 + p3g2 + p3p2g1 + p3p2p1g0 and p(0,3) = p3p2p1p0. In an analogous manner, we can get the equations for the other g(i, i+3) and p(i, i+3), and subsequently equations for c8, c12 and c16. For example, the equation for c8 can be written as follows: c8 = g(4,7) + p(4,7)c4 = g(4,7) + p(4,7)g(0,3) + p(4,7)p(0,3)c0 in which g(4,7) = g7 + p7g6 + p7p6g5 + p7p6p5g4 and p(4,7) = p7p6p5p4. Unlike the single-level CLA adder, in this two-level design the carries do not ripple through the CLA generators. In other words, the output carries c4, c8, c12, and c16 from the first-level CLA generators are not used. Instead, the g(i,i+3) and p(i,i+3) outputs from the first-level generators are used to generate these carries within the second-level generator, which are then fed into the first level CLA blocks to finish up the whole computation of each carry bit. Therefore, this design is denoted as a two-level CLA adder. In this design, the generation of all the carry values can be partitioned into 5 steps. Firstly, an array of AND and XOR gates are employed to generate the values of gi and pi (i = 0 to 15). Then, each first-level CLA logic generates g(i,i+3) and p(i,i+3) (i = 0,4,8,12) which are subsequently propagated to the second-level CLA logic. Using these values, the second-level CLA logic generates c4, c8, c12, and c16 at the 3rd step. Then, the values of ci (i = 0,4,8,12) are propagated back to each of the first-level CLA logic to generate ci+1, ci+2, ci+3, and ci+4, thus completing the carry generation process. Finally, the value of each carry ci (i = 0 to 15) is fed into another XOR array to compute the sum si = gi ci. Obviously, these two designs of 16-bit CLA binary adder display distinct hardware complexity and timing characteristics. In this part of the lab, you are asked to implement both designs and compare their timing characteristics. The detailed instruction for timing analysis will be discussed later in this writeup. Excess-3 adder/subtractor Up until now we have discussed the implementation of a 4-digit CLA excess-3 adder using a 16bit CLA binary adder (which has two possible implementations) and four constant-3 adders/subtractors that you have designed in Lab 3. The next issue we consider is to upgrade this adder to an adder/subtractor that can conditionally perform addition/subtraction according to a selector signal `A/S'. We know that the logic for computing the difference of a single bit (6)
subtractor is identical to the sum logic of a single bit adder. Therefore, the only question that needs consideration is whether or not we can still use the CLA logic to generate the values of borrows for a subtractor. We know that the carry logic of a single bit adder can be written as ci+1 = xiyi + xici + yici, while the borrow logic of a single bit subtractor can be written as bi+1 = xi'yi + xi'ci + yici. This indicates that if we flip every bit of the first input, the exact carry logic can be used to generate the borrow signals of a subtractor without any modification! However, as we flip every bit the of first input so as to reuse the carry logic, the subtraction result (i.e., the difference) will end up getting flipped. Therefore, in order to get the correct subtraction result, we also need to flip each result bit of the adder. In this way, the 16-bit CLA binary adder can be converted to a 16-bit binary subtractor. Obviously, the result of a 16-bit binary subtractor cannot be a valid excess-3 code. To obtain the correct excess-3 result, the subtractor output again needs to be fed into the constant-3 adders/subtractors to conditionally add or subtract 3. Your job is to figure out the add/subtract conditions, which display high similarity to the conditions of the addition cases that you have seen in the second part of your Lab 3. Implementation Guidelines Now let us summarize the preceding information and try to provide you a somewhat sharper picture regarding the implementation of this design. Your implementation of the 4-digit excess-3 adder/subtractor should be composed of the following parts: 16 carry-generate and carry-propagate functions: you need AND and XOR gates to implement gi = xiyi and pi = xi yi, respectively. 16 single-bit half adders: each adder takes as inputs the carry- generate function gi and the carry value ci (generated by the CLA logic), and generates the sum si = gi ci. 4 (or 5) 4-bit CLA generators: the circuit of a CLA generator is presented in Figure 5.2(b) of your textbook. You can also find on the same page the connections of a CLA generator to the single-bit adders for the implementation of a 4-bit binary adder. A total of 4 CLA generators are needed to implement a single-level 16-bit CLA adder, while an additional 4bit CLA generator is needed to implement a two-level 16-bit CLA adder. The structures of single-level and two-level 16-bit CLA adders are presented in Figure 5.3(b) of your textbook. 4 constant-3 adders/subtractors: The 4-bit sum of each 4-bit binary adder is fed into a constant-3 adder/subtractor, which conditionally performs addition/subtraction according to the value of the binary carryout. We will provide you this adder/subtractor design in case you do not have a fully working one handy. Your glue logic: you need to conditionally flip the first 16-bit input and the 16-bit output of your binary adder to perform subtraction. You are not allowed to implement subtraction by adding two's complement of the second 16-bit input. For both the case of addition and subtraction, you also need to conditionally add/subtract 3 to/from each 4-bit binary result to obtain a valid excess-3 code.
You are asked to implement both the single-level and two-level 16-bit CLA binary adders for your excess-3 look-ahead adder/subtractor. Once you have finished both implementations, you are asked to furthermore compare their performance. To achieve this goal, you should first set the delay of the gates according to the delay values specified in Table 1. The delay values listed in the table actually equal ten times the delay values reported in the text book for these gates1. You can set the delay value of any gate by using the "Simulation Params" option in the "Simulation" menu of LogicWorks.
1
We did this adjustment since LogicWorks only accepts integer values for gate delays.
You can read the total delay of the circuit by reading the timing display in LogicWorks. When you change the inputs, it will take some time for the effect of that change to reflect into the output. This difference in time is your total delay. Usually different input-output pairs have distinct delays. Even for the same input-output pair, its delay varies with distinct input combinations. The maximum delay value of each input-output pair is considered as its real delay value. After you finish your design, you need to measure the delays on the paths specified in Table 2 and fill in that table. In Table 2, xi and yi respectively denote the ith bit of your two excess-3 inputs (each input is 16 bits in total), ci denotes the carry-in for the ith bit of your binary adder, and si denotes the ith bit of your excess-3 addition/subtraction results. Table 1: Gate delay list Name Delay (ns) 2-input AND 24 3-input AND 28 4-input AND 32 2-input OR 24 3-input OR 28 4-input OR 32 2-input XOR 42 Inverter 10 Name Delay (ns) 2-input NAND 14 3-input NAND 18 4-input NAND 22 2-input NOR 14 3-input NOR 18 4-input NOR 22 2-input XNOR 32
Table 2: Path delay of 4-digit look-ahead excess-3 adder/subtractor Path Delay Path Delay Path Delay c0 to c4 x0 to c4 y0 to c4 c0 to c8 x0 to c8 y0 to c8 c0 to c12 x0 to c12 y0 to c12 c0 to c16 x0 to c4 y0 to c16 c0 to s3 x0 to s3 y0 to s3 c0 to s7 x0 to s7 y0 to s7 c0 to s11 x0 to s11 y0 to s11 c0 to s15 x0 to s15 y0 to s15 Your design will be evaluated based on both correctness and elegance. You should always try to minimize the total number of gates. As the two implementations of the 16-bit binary adders are straight from the textbook and the implementation of the constant-3 adder/subtractor is provided to you, your only job is to minimize the number of gates used in your glue logic. An efficient implementation only needs 32 gates in total. In sum, the whole design of your 4-digit excess-3 adder/subtractor should be completed within 200 gates. Given this significant number of gates needed in your implementation, it is almost impossible to put all the gates in one circuit. Therefore, in this lab assignment you are asked to package the CLA generator into a component2 so that you can reuse it multiple times. You can furthermore package the 4-bit binary adder into another component. In this way, the highest level of your schematic would be composed of four 4-bit CLA binary adders, four constant-3 adders/
2
The way of creating components in LogicWorks is presented in your LogicWorks tutorial.
subtractors, your glue logic, and one CLA generator, if you are using a two-level 16-bit CLA binary adder.
Part 2: Static Hazards
This part of the lab concerns the detection and elimination of static hazards in a circuit. As has been discussed in Section 4.7 of your textbook, static hazards are caused by two complementary signals (such as x and x'), which exhibit identical values for short periods of time due to different delays on the various paths through the schematic. Fundamentally, static hazards can be detected using KMaps. A static 1-hazard occurs if there exist two adjacent 1-minterms that are not covered by a common product term in a sum-ofproducts implementation. Similarly, a static 0-hazard occurs if there exist two adjacent 0maxterms that are not covered by a common sum term in a product-of-sums implementation. To eliminate a static 1-hazard, we must include an additional prime implicant covering both adjacent 1-minterms in the sum-of-products form. Similarly, to eliminate a static 0-hazard, we must include an additional prime implicate covering both adjacent 0-maxterms in the productof-sums form. This additional prime implicant/implicate is redundant since the sum-ofproducts/product-of-sums form with and without it defines the same Boolean function. In this part of your lab, you are asked to evaluate the possibility of static 0-hazards for 3-variable Boolean functions. As you know, a 3-variable Boolean function F can contain i (i=0...8) 0maxterms. The function of 0 0-maxterms obviously equals 1, while the function of 8 0-maxterms obviously equals 0, neither of which can of course have static hazards. Therefore, the question you need to answer is as follows: is it possible for a 3-variable Boolean function F that contains i (i=1...7) 0-maxterms to have static 0-hazard? As you know, the total number of 3-variable Boolean functions are 2^(23) = 256. However, most of these functions happen to be variants of the same type in that given one function, the remaining functions of the same type can be easily generated through rotating the variable names and/or complementing one or multiple variables. For example, the following two functions of 5 0-maxterms are considered to be of the same type, i.e., isomorphic,
ab c
00 0 1
01 0 0
11 0 1
10 0 1
ab c
00 0 1
01 1 1 F= a'(c+b)
11 0 0
10 0 0
0 1
0 1
F = c(a+b')
since you can generate the second function by exchanging the names of `a' and `c' in the first function and then complementing `a' and `b'. Given a value of i that satisfies 0<i<8, you only need to analyze one instance of each isomorphic type of the 3-variable Boolean functions that contains i 0-maxterms. If you think it is impossible for the function under consideration to have a static 0-hazard, explain your reason using Kmaps. If you think it is possible, you need to identify and eliminate the hazard through the following steps: 1. Draw the Kmap, show the minimal prime implicate needed for a minimal product-of-sums design by circling them. 2. On the same map, encircle also the prime implicates necessary to correct static hazards in the implementation, but this time with dotted lines or other means of distinguishing them from the minimum set.
3. Provide, for each KMap, the product-of-sums form for implementations both with and without static hazards. 4. Show how many static hazards exist in the minimal set of prime implicates for each function, and identify the circuit input transition necessary to trigger the static hazard (i.e. in what input transition condition will a glitch be observed at the output?). All the steps above should be clearly presented in your report. You'll also provide a LogicWorks design sheet named "Lab4Part2.cct" that contains two implementations for each of the 7 maxterm enumeration classes that you think is not hazard-free: one with the static hazards and one for the (redundant) form which corrects them. Each circuit should be clearly labeled by its number of 0-maxterms, and should be connected to binary switches and probes for testing purposes. To provide you a more concrete illustration on how to approach this question, we will analyze the case of i=2, i.e., F contains two 0-maxterms. Obviously, all the 3-variable Boolean functions of two 0-maxterms can be classified into two types: (1) the two 0-maxterms are not adjacent, and (2) the two 0-maxterms are adjacent. For the first situation, the two 0-maxterms cannot create any static 0-hazard since they are not adjacent. For the second situation, the two adjacent 0-maxterms can be covered by a single prime implicate, thus again resulting in no static 0-hazard. Therefore, our conclusion is that none of the 3-variable Boolean functions of two 0-maxterm can have any static 0-hazard.
Deliverables:
LogicWorks Files: Part 1: Include a LogicWorks design file (.cct) for each of the two 4-digit CLA excess-3 adder/subtractor circuits (with single- and two- level CLA generators). Include a component library file (.clf) that contains the circuit of the CLA generator and the 4-bit CLA adder. Part 2: As stated above, include a LogicWorks design file (.cct) that contains a pair of circuits for each of the 7 cases that you think may have a static 0-hazard. Reports: For part 1, you should submit a report that briefly explains how you designed your glue logic using a minimal number of gates. You should also provide your measured delay data by filling in Table 2 for both implementations of your CLA excess-3 adder/subtractor circuits. For part 2, for each of the 7 maxterm enumeration classes, you need to clearly state whether it is possible for a 3-input Boolean function to have static 0-hazard or not. If you think it is impossible, you need to clearly present your reason. It you think a function of that case may have static 0-hazard, your report should present all the maps, Boolean functions and explanations described above.