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VHDL EE367 Guide Book Spring 2005 VHDL Entity/Architecture Entity: entity entity_name is port ( signal_names : mode signal_type; signal_names : mode signal_type; ... signal_names : mode signal_type); end entity_name; Architecture: architecture architecture_name of entity_name is type declarations signal declarations constant declarations function definitions procedure definitions component declarations begin concurrent_statement; ... concurrent_statement; end architecture_name; VHDL Concurrent Signal Assignments: Simple Signal Assignment: signal_name <= expression; Conditional Signal Assignment: signal_name <= expression when boolean_expression else expression when boolean_expression else ... expression when boolean_expression else expression; Selected Signal Assignment: with expression select signal_name <= signal_value when choices, signal_value when choices, ... signal_value when others; Process: process ( signal_name, . . ., signal_name ) begin ... end process; VHDL Component Declaration: component component_name port ( signal_names : mode signal_type; signal_names : mode signal_type); end component; VHDL Predefined Types: bit bit_vector boolean character integer real severity_level string time VHDL Operators: arithmetic: +, -, *, / logical: and, or, xor, nand, nor, xnor, not relational: =, /=, <, <=, >, >= shift left/right logical: sll, srl shift left/right arithmetic: sla, sra rotate left/right logical: rol, ror other: concatenation: & exponentiation: ** remainder: rem division modulo: mod VHDL Process: process ( signal_name, . . ., signal_name ) type declarations variable declarations constant declarations function definitions procedure definitions begin sequential_statement ... sequential_statement end process; VHDL Array Declarations: type type_name is array (start to end) of element_type; type type_name is array (start downto end)of element_type; type type_name is array (range_type) of element_type; type type_name is array (range_type range start to end) of element_type; type type_name is array (range_type range start downto end) of element_type; VHDL CONSTANT Declaration: CONSTANT const_name : signal_type := expression; VHDL Component Instantiation: label: component_name port map (port_signal_name_1 => signal_1, port_signal_name_2 => signal_2, . . . , port_signal_name_n => signal_n ); VHDL Sequential Statements: Simple Signal Assignment: signal_name <= expression; VHDL if Statement: if boolean_expression then sequential_statement end if; if boolean_expression then sequential_statement else sequential_statement end if; if boolean_expression then sequential_statement elsif boolean_expression then sequential_statement ... elsif boolean_expression then sequential_statement end if; if boolean_expression then sequential_statement elsif boolean_expression then sequential_statement ... elsif boolean_expression then sequential_statement else sequential_statement end if; VHDL Case Statement: VHDL Entity with Generic: entity entity_name is generic ( constant_names : constant_type; ... constant_names : constant_type); port ( signal_names : mode signal_type; signal_names : mode signal_type; ... signal_names : mode signal_type); end entity_name; VHDL Package Definition: package package_name is type declarations signal declarations constant declarations function definitions procedure definitions component declarations end package_name; package body package_name is type declarations constant declarations function definitions procedure definitions end package_name; case expression is when choices => sequential_statements ... when choices => sequential_statements end case; VHDL Loop Statements: Loop: loop sequential_statement ... sequential_statement end loop; for loop: for identifier in range loop sequential_statement sequential_statement ... end loop; while loop: while boolean_expression loop sequential_statement ... sequential_statement end loop; VHDL Signal Assignment Statements The architecture body has concurrent_statements within the begin and end. Concurrent statements are: Simple Signal Assignment: signal_name <= expression; Conditional Signal Assignment: signal_name <= expression when boolean_expression else expression when boolean_expression else ... expression when boolean_expression else expression; Selected Signal Assignment: with expression select signal_name <= signal_value when choices, signal_value when choices, ... signal_value when choices; Process: A process with it s begin and end is considered to be a concurrent statement in the architecture body. The process body between it s begin and end must have sequential_statements. Sequential statements are: Simple Signal Assignment: signal_name <= expression; IF statement: if boolean_expression then sequential_statement end if; if boolean_expression then sequential_statement else sequential_statement end if; if boolean_expression then sequential_statement elsif boolean_expression then sequential_statement ... elsif boolean_expression then sequential_statement end if; if boolean_expression then sequential_statement elsif boolean_expression then sequential_statement ... elsif boolean_expression then sequential_statement else sequential_statement end if; CASE Statement: case expression is when choices => sequential_statements ... when choices => sequential_statements end case; You may NOT use conditional signal assignments or selected signal assignments within a process as they are not sequential statements. Other Miscellaneous Stuff about VHDL You can specify bit strings in hex: x"ab" is equivalent to "10101011" You can carve out a slice of bits from a logic vector: Data1 : in STD_LOGIC_VECTOR(15 downto 0); Data2 : out STD_LOGIC_VECTOR(7 downto 0); You can specify individual bits in a vector: Bit_1 : STD_LOGIC: Bit_1 <= Data1(1); You can assign the high byte of Data1 to Data2 by: Data2(7 downto 0) <= Data1(15 downto 8); Type conversion between STD_LOGIC_VECTOR and INTEGERS and Arithmetic Operations on STD_LOGIC_VECTORS: You have two choices to do arithmetic when your signals are STD_LOGIC_VECTOR type (recommended for the entity inputs and outputs.) You can: a. Convert input data to integers, perform all required operations on integers and convert the results to STD_LOGIC_VECTOR. b. Attach a package containing definitions of arithmetic and relational operators that allow arithmetic using STD_LOGIC_VECTOR. The most frequently used packages that contain both conversion functions and definitions of popular operators for logic vector arguments are: STD_LOGIC_SIGNED and STD_LOGIC_UNSIGNED. These define exactly the same set of objects, but the first interprets logic vectors as numbers with sign and the second as unsigned numbers. STD_LOGIC_ARITH. This declares special types SIGNED and UNSIGNED and a full set of operations on arguments of those types. Package Arithmetic Operations Conversion to Integer Conversion to STD_LOGIC_VECTOR none STD_LOGIC_SIGNED and STD_LOGIC_UNSIGNED STD_LOGIC_ARITH A+B conv_integer(A) signed(A) + signed(B) or unsigned(A)+unsigned(B) conv_integer(signed(A)) or conv_integer(unsigned(A) ) conv_std_logic_vector(Int,nb ) A, B: std_logic_vector Int: Integer nb: number of bits required in the resulting vector signed, unsigned: casting a vector to a signed or unsigned number You use these packages by declaring them before the entity: library IEEE; use IEEE.STD_LOGIC_1164.all; ` -- Uses the STD_LOGIC_VECTOR defintions use IEEE.STD_LOGIC_ARITH.all; -- Use the STD_LOGIC_ARITH functions G:\1wpdocs\univ\dept\courses\Ee367\VHDL Guide Book_05a.doc
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ee367_lecture_15.pdf
Path: Montana >> EE >> 367 Spring, 2008
Description: EE 367 Logic Design Lecture #15 Agenda 1. VHDL : Test Benches Announcements (Wednesday, 2/27) 1. No new HW posted 2. Lab #6 today EE 367 Logic Design Spring 2008 Lecture #15 Page 1 VHDL : Test Benches Test Benches - We need to stimulate our...
EE367_Project_Description.doc
Path: Montana >> EE >> 367 Spring, 2008
Description: EE 367 Logic Design Spring, 2008 Final Project Description Summary Instead of a final exam, you are to complete a design project. This project will require you to design, test, and implement a design that is not covered in class or in lab. This proj...
ee367_lecture_28.pdf
Path: Montana >> EE >> 367 Spring, 2008
Description: EE 367 Logic Design Lecture #28 Agenda 1. MSI: Multipliers 2. Exam #2 Review Announcements (Wednesday, 4/9) 1. Exam #2 Friday (4/11) 2. HW #11 posted, due 4/18 (last one!) 3. Lab Catch-Up Day - work on Lab #9 EE 367 Logic Design Spring 2008 Lec...
ee367_lecture_17.ppt
Path: Montana >> EE >> 367 Spring, 2008
Description: EE 367 Logic Design Lecture #17 Agenda 1. Latches and Flip-Flops Announcements (Wednesday, 3/5) 1. HW #7 posted, due Thursday, (3/20) by 2pm. Friday (3/21) is a holiday. 2. Catch-up day in lab, no new assignment EE 367 Logic Design Spring 2008...
ee367_lecture_25.ppt
Path: Montana >> EE >> 367 Spring, 2008
Description: EE 367 Logic Design Lecture #25 Agenda 1. MSI: Ripple Carry Adders Announcements (Wednesday, 4/2) 1. HW# 10 posted, due 4/11 2. Lab #9 Today EE 367 Logic Design Spring 2008 Lecture #25 Page 1 Ripple Carry Adder Addition Half Adder - one bi...
ee367_lecture_13.pdf
Path: Montana >> EE >> 367 Spring, 2008
Description: EE 367 Logic Design Lecture #13 Agenda 1. VHDL : Variables 2. VHDL : If/Then Statements 3. VDHL : Case Statements Announcements (Friday, 2/22) 1. HW #5 due today EE 367 Logic Design Spring 2008 Lecture #13 Page 1 Variables Variables - Signa...
ee371_t3_f05_key.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE371 Third Semester Test Thursday November 17, 2005 40 points, 16.67% of Final Grade Please put your name on the outside of the paper also. Name _KEY_ Notation: An active- low signal is denoted by an *, i.e. ADR_OK* is a signal asserted low. 1. Ass...
pr_buf.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: pr_buf.asm Assembled with CASM 10/06/2000 09:30 PAGE 1 0000 0000 0000 0000 0000 0000 0000 4000 4000 CF8000 4003 CE4041 4006 8612 4008 16400F 400B 16402C 400E 3F 400F 4010 4011 4012 39 3B 34 35 4013 36 4014 4016 4017 4018 401C 401E E630 34 87 ...
asm_coding_standard.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE371 Assembly Language Coding Standard The reason for this standard is to insure all embedded firmware meets minimum levels of readability and maintainability. This standard is tailored for EE371 and a more fully defined development standard example...
371L07F4.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE371 Lab 7, Fall 2004 Structured Program Design and Implementation A balanced diet is a cookie in each hand Oct 19,20: Do the lab Oct 26, 27: Last chance to demo Name _ Meeting Day _HR _ Demo_ Schedule: Extra(1)_ Code _ Boy, our customer at Two ...
ee371_t1_f05_key.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE371 First Semester Test - Thursday September 29, 2005 40 Points, 16.667% of Final Grade Please put your name on the outside of the paper also. Hand in the test folded so your name shows on the outside. Name: _ 1. Assume the following information i...
371sch.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE371 MICROCOMPUTER SOFTWARE ENGINEERING FALL 2005 SCHEDULE AND INFORMATION EE371 Web Page: http:/www.coe.montana.edu/ee/courses/ee/ee371/ee371hpg.htm email: fcady@ee.montana.edu Office Hours: M - 2:00, Tu - 10:30, Wed - 1:30, Th - 9, Fri - 8 Class M...
mmerrors.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: Errors in Microcomputers and Microcontrollers September 13, 2002 Pg 28 96 Error Correction There is an extra bit shown as the carry out of the least significant bytte addition. Top line on page: figure 7-4(b) should read Figure 7-3(b) Thanks Tim Szaf...
ee371_t1_f04_key.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE371 First Semester Test - Thursday September 30, 2004 40 Points, 16.667% of Final Grade Please put your name on the outside of the paper also. Name: _KEY_ Hand in the test folded so your name shows on the outside. 1. Discuss the difference between ...
ee371_t4_f04_key.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Final Exam Tuesday December 14, 2004 3 pages, 7 questions, 55 points, 15% of Final Grade Please put your name on the outside of the paper also Name _KEY_ 1. The memory display shows: 4000: 08 29 3F 7F - 86 99 A0 64 - . . . and the current val...
CSM12C32_SCH_B.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: ...
lab_09.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor HW & SW Laboratory Lab #9 Timers Date: 11/12/08 Due: 11/19/08 Name : _ Partner : _ Section: _ Grade : Part 1: Part 2: Extra Credit : Total : _ / 2 _ / 8 _ / 1 _ / 10 Lab Description Todays lab will introduce you to the HCS1...
ee371_syllabus.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware and Software Systems 4 Credits, Fall Semester, 2008 Department of Electrical & Computer Engineering Montana State University Bozeman, MT Objective: This course introduces students to the structure of microprocessors an...
ee371_lecture_33.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware Synchronous Serial Peripheral Interface\" - higher speed link for peripherals, DSP\'s, MCU\'s, etc - typically used ...
ee371_lecture_19.pptx
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware & Software Systems Lecture #19 Agenda 1. External Reset 2. Interrupts Announcements (W, 10/22/08) 2. Lab Exam today and tomorrow, make sure you are signed up for a time slot 3. Read Chapter 12 4. HW #7 posted EE 3...
homework_07.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware and Software Systems Fall, 2008 Homework #7 Due 10/31/08 Name: Grade: _ _ /10 1) For the following interrupts, indicate the Global Enable, Local Enable, and Interrupt Vector Address. You can use the symbol for the En...
ee371_lecture_21.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware & Software Systems Lecture #21 Agenda 1. IRQ_L External Interrupt IRQ_L External Interrupt IRQ_L Details - an external IRQ available to the HC12 - is a physical pin on the device - can be used for likes like sensors,...
ee371_lecture_04.pptx
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware SW Systems Fall 2008 12/19/08 M68HCS12 Overview H...
ee371_lecture_35.pptx
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware SW Systems Fall 2008 12/19/08 Dig...
lab_01.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor HW & SW Laboratory Lab #1 Introduction and MC68HCS12 Programming Date: 9/10/08 Due: 9/17/08 Name : _ Partner : _ Section: _ Grade : Pre-Lab: Part 1: Part 2: Extra Credit: Total: _ / 0 _/ 2 _/ 3 _/ 1 _ / 5 Lab Description To...
homework_04.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware and Software Systems Fall, 2008 Homework #4 Due 10/3/08 Name: Grade: _ _ /5 1) Decode the following HCS12 Machine Code into assembly language : (include directives required to place at appropriated memory location, as...
ee371_lecture_17.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware & Software Systems Lecture #17 Agenda 1. Multi-Precision Arithmetic + (C=1) Multi-Precision Addition Multi-Precision Arithmetic (Addition) - sometimes #s need more than 1 byte to represent the data. So we need more t...
ee371_lecture_02.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware & Software Systems Lecture #2 Agenda 1. Number Systems Number Systems Base Notation - We will use the same notation as the HC12 Assembler. Decimal: Binary: Octal: Hexadecimal: ASCII: nothing % @ $ ex) ex) ex) ex) e...
ee371_lecture_06.pptx
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware SW Systems Fall 2008 12/19/08 Addressing Modes (Indexed) Indexed Addre...
CSM12C32_UG.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: DOC-0328-010, REV D CSM12C32 Educational Module for Freescale MC9S12C32 Axiom Manufacturing 2813 Industrial Lane Garland, TX 75041 Email: Sales@axman.com Web: http:/www.axman.com CSM12C32 JUNE 8, 2005 CONTENTS CAUTIONARY NOTES ..4 FEATURES...
ee371_lecture_30.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware successive approximation\" A/D - 8 channels (pins) can be connected to the A/D ...
homework_09.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware and Software Systems Fall, 2008 Homework #9 Due 11/21/08 Name: Grade: _ _ /10 1) What HC12 Timer is best suited for the following tasks: (6 points) a) Generate an IRQ every 1 s: b) Generate an IRQ every 8ms: c) Gener...
ee371_lecture_16.pdf
Path: Montana >> EE >> 371 Fall, 2008
Description: EE 371 Microprocessor Hardware & Software Systems Lecture #16 Agenda 1. Data Modification Instructions a) Transfers and Moves b) Clear and Set c) Shift and Rotate d) Logic e) Debouncing TRANSFER Transfer - Moves data ONLY within the CPU Registers ...
BSIM3v3_Users_Manual.pdf
Path: Montana >> EE >> 414 Fall, 2008
Description: BSIM3v3.2.2 MOSFET Model Users Manual Weidong Liu, Xiaodong Jin, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K. Ko and Chenming Hu Department of Electrical Engineering and C...
ee414_lecture_14.pdf
Path: Montana >> EE >> 414 Fall, 2008
Description: EE 414 Introduction to VLSI Design Lecture #14 Agenda 1. Inverter Switching Characteristics CMOS Switching Characteristics CMOS Switching Characteristics - we studied the DC (or Static) characteristics of the CMOS inverter - we learned how to cal...
ch_02_fabrication_slides.pdf
Path: Montana >> EE >> 414 Fall, 2008
Description: CMOS Digital Integrated Circuits Chapter 2 Fabrication of MOSFETs S.M. Kang and Y. Leblebici 1 CMOS Digital Integrated Circuits 3rd Edition Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Categories of...
VLSI_Cost_Analysis.xls
Path: Montana >> EE >> 414 Fall, 2008
Description: VLSI Cost Analysis - Using your own IC NRE Fab Shop Mask, Tooling, Test, Packaging Custom ASIC STD Cell ASIC Gate Array FPGA $300,000 $200,000 $150,000 $0 Upfront Cost CAD Tools $200,000 $100,000 $50,000 $0 Engineering Cost Total DEV Cost Custom AS...
ee414_lecture_17.pdf
Path: Montana >> EE >> 414 Fall, 2008
Description: EE 414 Introduction to VLSI Design Lecture #17 Agenda 1. Combinational Logic - graph theory - AOI / OAI - T-gates Announcements (Thursday, 11/13/08) 1. Read 7.4 - 7.5 2. HW #9 CMOS Combinational Logic Complex CMOS Logic Circuits - we can impleme...
ee414_lecture_03.pptx
Path: Montana >> EE >> 414 Fall, 2008
Description: EE 414 Introduction to VLSI Design Lecture #3 Agenda 1. MOSFET Operation cont - Device Physics cont - MOS Structure - MOSFET Structure Announcements (Tuesday, 9/9/08) 1. HW#1 due on Thursday (9/6) at the beginning of class 2. HW#2 is posted 3. R...
ee414_lecture_13.pptx
Path: Montana >> EE >> 414 Fall, 2008
Description: EE 414 Introduction to VLSI Design Lecture #13 Agenda 1. Inverter Static Characteristics Announcements (Thursday, 10/23/08) 1. HW #6 due EE 414 Introduction to VLSI Design Fall 2008 12/19/08 CMOS Inverter Threshold CMOS Inverter Static Beha...
ee414_lecture_03.pdf
Path: Montana >> EE >> 414 Fall, 2008
Description: EE 414 Introduction to VLSI Design Lecture #3 Agenda 1. MOSFET Operation cont - Device Physics cont - MOS Structure - MOSFET Structure Work Function Electron Affinity & Work Function - another metric of a material is the amount of energy it takes...
ee414_lecture_14.pptx
Path: Montana >> EE >> 414 Fall, 2008
Description: EE 414 Introduction to VLSI Design Lecture #14 Agenda 1. Inverter Switching Characteristics Announcements (Tuesday, 10/28/08) 1. Read 6.1 - 6.3 2. HW #8 posted EE 414 Introduction to VLSI Design Fall 2008 12/19/08 CMOS Switching Characterist...
ee414_lecture_18.pdf
Path: Montana >> EE >> 414 Fall, 2008
Description: EE 414 Introduction to VLSI Design Lecture #18 Agenda 1. Sequential Logic 2. Exam #2 Review Announcements (Tuesday, 11/18/08) 1. Read 8.1-8.5 2. HW #10 due Thursday (11/20/08), Last One! 3. Exam #2 Thursday (11/8/08), Last One! - open books, open ...
TDR_AppNote_Agilent_TDRtheory_5966-4855E.pdf
Path: Montana >> EE >> 461 Spring, 2008
Description: Time Domain Reflectometry Theory Application Note 1304-2 For Use with Agilent 86100 Infiniium DCA Introduction The most general approach to evaluating the time domain response of any electromagnetic system is to solve Maxwells equations in the tim...
ee461_lecture_18.ppt
Path: Montana >> EE >> 461 Spring, 2008
Description: EE 461 Digital System Design Lecture #18 Agenda Crosstalk Announcements (Friday, 2/29) 1. Read 10.18 2. HW #6 due today 3. Exam #1, Monday 3/3 EE 461 Digital System Design Spring 2008 Lecture #18 Page 1 Exam #1 Review Exam #1 - Monday, 3/3...
ee461_lecture_11.pdf
Path: Montana >> EE >> 461 Spring, 2008
Description: EE 461 Digital System Design Lecture #11 Agenda 1. Transmission Lines (TD & Z0) Announcements (Monday, 2/11) 1. Read 7.10 - 7.15 EE 461 Digital System Design Spring 2008 Lecture #11 Page 1 Transmission Lines Circuit Model - A T-line is a di...
ee461_lecture_08.ppt
Path: Montana >> EE >> 461 Spring, 2008
Description: EE 461 Digital System Design Lecture #8 Agenda Lab #2: Variables and Subcircuits in ADS Announcements (Monday, 2/4) 1. n/a EE 461 Digital System Design Spring 2008 Lecture #8 Page 1 Lab #2 ADS Variables & Subcircuits Todays Lab Objectives...
ee461_lecture_34.ppt
Path: Montana >> EE >> 461 Spring, 2008
Description: EE 461 Digital System Design Lecture #34 Agenda Lab #11 (TDR) Announcements (Monday, 4/21) 1. All PCB\'s will be in this week. EE 461 Digital System Design Spring 2008 Lecture #34 Page 1 Time Domain Reflectrometry TDR - A TDR is an oscillos...
ee461_lecture_32.pdf
Path: Montana >> EE >> 461 Spring, 2008
Description: EE 461 Digital System Design Lecture #32 Agenda 1. Differential Signaling 2. ZODD, ZEVEN Announcements (Wednesday, 4/16) 1. n/a EE 461 Digital System Design Spring 2008 Lecture #32 Page 1 Uncoupled Lines Impedance Definitions - Last time we...
ee461_lecture_05.ppt
Path: Montana >> EE >> 461 Spring, 2008
Description: EE 461 Digital System Design Lecture #5 Agenda Lab #1: Introduction to Advanced Design System (ADS) Software Announcements (Monday, 1/28) There is a Quick Start Guide to ADS on the Course Website under Information EE 461 Digital System Desig...
ee461_lecture_13.pdf
Path: Montana >> EE >> 461 Spring, 2008
Description: EE 461 Digital System Design Lecture #13 Agenda 1. Transmission Lines (Terminations) Announcements (Friday, 2/15) 1. HW #4 due today 2. Read 8.9 - 8.10 3. No Class Monday (2/18), President\'s Day EE 461 Digital System Design Spring 2008 Lectur...
TDR_AppNote_Agilent_MeasCL_apr96a11.pdf
Path: Montana >> EE >> 461 Spring, 2008
Description: Measuring Parasitic Capacitance and Inductance Using TDR Time-domain reflectometry (TDR) is commonly used as a convenient method of determining the characteristic impedance of a transmission line or quantifying reflections caused by discontinuities a...
phys213lec07.pdf
Path: Montana >> PHYS >> 213 Spring, 2008
Description: Lecture 7: 1/27/06 Homework HW#1 returned on Monday. HW#2 due next Wednesday before class. See revised written homework format in this lecture! MP#7 is due Monday at 1pm. Read 21.1 by Monday Practice problems from Serway (Not to be turned in!) Pro...
phys213lec07.pdf
Path: Montana >> PHYS >> 222 Fall, 2008
Description: Lecture 7: 1/27/06 Homework HW#1 returned on Monday. HW#2 due next Wednesday before class. See revised written homework format in this lecture! MP#7 is due Monday at 1pm. Read 21.1 by Monday Practice problems from Serway (Not to be turned in!) Pro...
GettingStartedMasteringPhysics.pdf
Path: Montana >> PHYS >> 213 Spring, 2008
Description: MP.Booklet_Student_mech.qxd 10/27/05 8:24 AM Page 1 STUDENT EDITION Getting Started with MASTERINGPHYSICSTM IS POWERED BY MYCYBERTUTOR BY EFFECTIVE EDUCATIONAL TECHNOLOGIES MP.Booklet_Student_mech.qxd 10/27/05 8:24 AM Page 2 Copyright 2006...
GettingStartedMasteringPhysics.pdf
Path: Montana >> PHYS >> 222 Fall, 2008
Description: MP.Booklet_Student_mech.qxd 10/27/05 8:24 AM Page 1 STUDENT EDITION Getting Started with MASTERINGPHYSICSTM IS POWERED BY MYCYBERTUTOR BY EFFECTIVE EDUCATIONAL TECHNOLOGIES MP.Booklet_Student_mech.qxd 10/27/05 8:24 AM Page 2 Copyright 2006...
phys213lec38.pdf
Path: Montana >> PHYS >> 213 Spring, 2008
Description: Grab your Hour Exams in front of class Lecture 38: 4/26/06 Binding Energy per Nucleon Average Binding Energy per nucleon <Eb> = ( Z mp + N mn MA) / (Z+ N) x 931.494 MeV/u <Eb> = ( Z (mp +me) + N mn MAtomic) / (Z+ N) x 931.494 MeV/u <Eb> = ( Z M...
phys213lec38.pdf
Path: Montana >> PHYS >> 222 Fall, 2008
Description: Grab your Hour Exams in front of class Lecture 38: 4/26/06 Binding Energy per Nucleon Average Binding Energy per nucleon <Eb> = ( Z mp + N mn MA) / (Z+ N) x 931.494 MeV/u <Eb> = ( Z (mp +me) + N mn MAtomic) / (Z+ N) x 931.494 MeV/u <Eb> = ( Z M...
phys213lec23.pdf
Path: Montana >> PHYS >> 213 Spring, 2008
Description: Lecture 22: 3/10/06 Homework HW# 7 due next Wednesday Do as one problem as per homework format of lecture 7 Include a drawing of hermit\'s frame and spacecraft frame. MP#18 is not due today, but due Monday after Spring Break at 1pm. No new MP. Read...
phys213lec23.pdf
Path: Montana >> PHYS >> 222 Fall, 2008
Description: Lecture 22: 3/10/06 Homework HW# 7 due next Wednesday Do as one problem as per homework format of lecture 7 Include a drawing of hermit\'s frame and spacecraft frame. MP#18 is not due today, but due Monday after Spring Break at 1pm. No new MP. Read...
phys213lec11.pdf
Path: Montana >> PHYS >> 213 Spring, 2008
Description: Lecture 11: 2/5/06 Homework HW#3 due Wednesday 2/8 before class. See end of lecture 9 for problem. Follow written homework format in Lecture 7. Hint-You\'ll need your calculus background for this one. HW#2 returned on today. MP#11 is due Monday at ...
phys213lec11.pdf
Path: Montana >> PHYS >> 222 Fall, 2008
Description: Lecture 11: 2/5/06 Homework HW#3 due Wednesday 2/8 before class. See end of lecture 9 for problem. Follow written homework format in Lecture 7. Hint-You\'ll need your calculus background for this one. HW#2 returned on today. MP#11 is due Monday at ...
phys213lec06.pdf
Path: Montana >> PHYS >> 213 Spring, 2008
Description: Lecture 6: 1/25/06 Homework HW#1 due before class. HW#2 due next Wednesday before class. Problem at end of lecture. MP#6 is due Friday at 1pm. No new reading (Should be through 20.7 by now) Practice problems from Serway (Not to be turned in!) Probl...
phys213lec06.pdf
Path: Montana >> PHYS >> 222 Fall, 2008
Description: Lecture 6: 1/25/06 Homework HW#1 due before class. HW#2 due next Wednesday before class. Problem at end of lecture. MP#6 is due Friday at 1pm. No new reading (Should be through 20.7 by now) Practice problems from Serway (Not to be turned in!) Probl...
phys353lec10.pdf
Path: Montana >> PHYS >> 353rn Spring, 2008
Description: Physics 353RN Spring 2008 Lecture 10 Upcoming Deadlines 1. LAB 3 holograms and write-up due 4/22 LAB 3 meeting times: Monday 4/7/08 11:00-12:50pm Thursday 4/10/08 12:10-2:00pm Thursday 4/10/08 3:10-5:00pm Friday 4/11/08 12:10-2:00pm 2. Independent...
phys353lec12_6pp.pdf
Path: Montana >> PHYS >> 353rn Spring, 2008
Description: Physics 353RN Spring 2008 Lecture 12 Making a Second Generation Hologram Making a Transmission 2nd Generation Hologram H1 H1 H2 R L White Light Hologram Huge Curved Mirror H2 R L White Light Transmission Hologram Huge Curved Mirror Transmis...
Examtres03.doc
Path: Montana >> PSPP >> 433r Fall, 2008
Description: 1. Johnny Appleseed provided America with the tools to create many new apple cultivars never before seen. Explain what Johnny Appleseed did to create so many cultivars, why his method worked, and how this allowed the apple to thrive in America. 2. De...
RefDisectionExercise.pdf
Path: Montana >> ESCI >> 301 Fall, 2008
Description: ...
18PeriLand.ppt
Path: Montana >> ESCI >> 455 Spring, 2008
Description: Periglacial/Permafrost Frost heave/creep Heave = f( e He Cr ee p Moisture) Grain size) Saturation) Grain size) Slope) Creep = f( av Settle Fine Frost heave /creep Movement = f( Coarse Time) Slope) Coarse Fine Transect across ...
20Karst2.ppt
Path: Montana >> ESCI >> 455 Spring, 2008
Description: Karst Landforms and Landscapes Effects of mixing Two waters meetin, limestone is eaten. Water sources Water table Lakes, etc. Acid sources Cave types Meteoric Hydrothermal Geochemical transitions Degassing Precipitation of CaCO3 Chargi...
