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367 EE Logic Design Lecture #17 Agenda 1. Latches and Flip-Flops Announcements (Wednesday, 3/5) 1. HW #7 posted, due Thursday, (3/20) by 2pm. Friday (3/21) is a holiday. 2. Catch-up day in lab, no new assignment EE 367 Logic Design Spring 2008 Lecture #17 Page 1 Latches Latches - we ve learned all of the VHDL syntax necessary to describe sequential storage elements - Let s review where sequential devices come from SR Latch - To understand the SR Latch, we must remember the truth table for a NOR Gate AB 00 01 10 11 F 1 0 0 0 EE 367 Logic Design Spring 2008 Lecture #17 Page 2 Latches SR Latch - when S=0 & R=0, it puts this circuit into a Bi-stable feedback mode where the output is either: Q=0, Qn=1 0 1 0 0 AB 00 01 10 11 F 1 (U2) 0 0 (U1) 0 EE 367 Logic Design Spring 2008 Q=1, Qn=0 0 0 0 1 1 0 0 AB 00 01 10 11 F 1 (U1) 0 (U2) 0 0 Lecture #17 Page 3 1 Latches SR Latch - we can force a known state using S & R: Set (S=1, R=0) 0 0 1 1 AB 00 01 10 11 F 1 (U1) 0 0 (U2) 0 (U2) 0 1 1 1 0 0 1 AB 00 01 10 11 F 1 (U2) 0 (U1) 0 0 (U1) 0 Reset (S=0, R=1) EE 367 Logic Design Spring 2008 Lecture #17 Page 4 Latches SR Latch - we can write a Truth Table for an SR Latch as follows SR 00 01 10 11 Q Last Q 0 1 0 Qn . Last Qn 1 0 0 - Hold - Reset - Set - Don t Use - S=1 & R=1 forces a 0 on both outputs. However, when the latch comes out of this state it is metastable. This means the final state is unknown. EE 367 Logic Design Spring 2008 Lecture #17 Page 5 Latches S R Latch - we can also use NAND gates to form an inverted SR Latch S R 00 01 10 11 Q 1 1 0 Last Q Qn . 1 0 1 Last Qn - Don t Use - Set - Reset - Hold EE 367 Logic Design Spring 2008 Lecture #17 Page 6 Latches SR Latch w/ Enable - we then can add an enable using line NAND gates - remember the Truth Table for a NAND gate AB 00 01 10 11 F 1 1 1 0 - a 0 on any input forces a 1 on the output - when C=0, the two EN NAND Gate outputs are 1, which forces Last Q/Qn - when C=1, S & R are passed through INVERTED EE 367 Logic Design Spring 2008 Lecture #17 Page 7 Latches SR Latch w/ Enable - the truth table then becomes C 1 1 1 1 0 SR 00 01 10 11 xx Q Last Q 0 1 1 Last Q Qn . Last Qn 1 0 1 Last Qn - Hold - Reset - Set - Don t Use - Hold EE 367 Logic Design Spring 2008 Lecture #17 Page 8 Latches D Latch - a modification to the SR Latch where R = S creates a D-latch - when C=1, Q <= D - when C=0, Q <= Last Value CD 10 11 0x Q 0 1 Last Q Qn . 1 - track 0 - track Last Qn - Hold EE 367 Logic Design Spring 2008 Lecture #17 Page 9 Latches VHDL of a D Latch architecture Dlatch_arch of Dlatch is begin LATCH : process (D,C,Q) begin if (C= 1 ) then Q<=D; Qn<=not D; else Q<=Q; Qn<=Qn; end if; end process; end architecture; EE 367 Logic Design Spring 2008 Lecture #17 Page 10 Flip Flops D-Flip-Flops - we can combine D-latches to get an edge triggered storage device (or flop) - the first D-latch is called the Master , the second D-latch the Slave Master CLK=0, Q<=D Open CLK=1, Q<=Q Closed Slave CLK=0, Q<=Q Close CLK=1, Q<=D Open - on a rising edge of clock, D is latched and held on Q until the next rising edge EE 367 Logic Design Spring 2008 Lecture #17 Page 11 Flip Flops VHDL of a D-Flip-Flop architecture DFF_arch of DFF is begin FLOP : process (CLK) begin if (CLK event and CLK=1) then Q<=D; Qn<=not D; else Q<=Q; Qn<=Qn; end if; end process; end architecture; -- recognized by all synthesizers as DFF EE 367 Logic Design Spring 2008 Lecture #17 Page 12

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