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### web_sol_ch8_ed3c1

Course: ECE 203, Spring 2006
School: Northwestern
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Word Count: 549

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to Solutions Problems Marked with a * in Logic and Computer Design Fundamentals, 3rd Edition Chapter 8 (Updated 9/21/06) 2004 Pearson Education, Inc. 8-1.*(Updated 9/21/06) S0 Z1 = 0 Z2 = 0 0 Inputs: X1X2 Outputs: Z1Z2 1 S1 X1 Z1 = 0 Z2 = 1 00 10 X1X2 01 11 S2 Z1 = 1 Z2 = 0 00 11 X1X2 01 10 8-2.* A: 0 B: 1 C: 0 State: ST1 Z: 0 1 1 1 ST1 0 1 0 0 ST2 0 0 1 1 ST3 1 1 0 0 ST1 0 1 1 1 ST2 1 0 0 0 ST3 1 1...

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to Solutions Problems Marked with a * in Logic and Computer Design Fundamentals, 3rd Edition Chapter 8 (Updated 9/21/06) 2004 Pearson Education, Inc. 8-1.*(Updated 9/21/06) S0 Z1 = 0 Z2 = 0 0 Inputs: X1X2 Outputs: Z1Z2 1 S1 X1 Z1 = 0 Z2 = 1 00 10 X1X2 01 11 S2 Z1 = 1 Z2 = 0 00 11 X1X2 01 10 8-2.* A: 0 B: 1 C: 0 State: ST1 Z: 0 1 1 1 ST1 0 1 0 0 ST2 0 0 1 1 ST3 1 1 0 0 ST1 0 1 1 1 ST2 1 0 0 0 ST3 1 1 1 1 ST1 0 ST2 8-5.* STA Reset 0 STB X 1 STD 0 STC X 1 Z STE X 0 Z 1 0 1 0 X X 1 8-8.* ST1(t + 1) = ST1A + ST2BC + ST3, ST2(t + 1) = ST1A, ST3(t + 1)= ST2(B + C), Z = ST2B + ST3 For the D flip-flops, DSTi = STi(t + 1) and STi = QSTi. Reset initializes the flip-flops: ST1 = 1, ST2 = ST3 = 0. 1 Problem Solutions Chapter 8 8-9.* State Assignment Y1 Y0 ST1 ST2 ST3 0 0 0 1 1 0 DY0 D C R Y0 DECODER 2 21 Y1 0 ST1 0 ST2 1 ST3 2 A B C DY0 DY1 DY1 D C R Z Reset 8-11.* 100110 (38) 110101 ( 53) 100110 000000 100110 000000 100110 100110 11111011110 (2014) 100110 110101 000000 100110 100110 0100110 00100110 100110 10111110 010111110 0010111110 100110 1100011110 01100011110 100110 11111011110 011111011110 Init PP Add After Add After Shift After Shift Add After Add After Shift After Shift Add After Add After Shift Add After Add After Shift 8-16.* IN CLK LA L AR Bit 15 Zero R is a synchronous reset that overides any simultaneous synchronous transfer. A Reset LB L BR LC CLK A(14:0)||0 S 1 MUX 0 CLK L R CR B(14:0)||0 A(15:0) B(15:0) 0 G 1 LA B LB C LC 2 Problem Solutions Chapter 8 G D C R LA Reset D C R LB D C R LC 8-19.* library IEEE; use IEEE.std_logic_1164.all; entity asm_819 is port ( A, B, C, CLK, RESET: in STD_LOGIC; Z: out STD_LOGIC ); end asm_819; architecture asm_819_arch of asm_819 type is state_type is (ST1, ST2, ST3); signal state, next_state : state_type; begin state_register: process (CLK, RESET) begin if RESET='1' then--asynchronous RESET active High state <= ST1; elsif (CLK'event and CLK='1') then --CLK rising edge state <= next_state; end if; end process; next_state_func: process (A, B, C, state) begin case (state) is when ST1 => if A = '0' then next_state <= ST1; else next_state <= ST2; end if; when ST2 => if ((B = '1') and (C = '0')) then next_state <= ST1; else next_state <= ST3; end if; when ST3 => next_state <= ST1; end case; end process; output_func: process (B, state) begin case (state) is when ST1 => Z <= '0'; when ST2 => if (B = '1') then Z <= '1'; else Z <= '0'; end if; when ST3 => Z <= '1'; end case; end process; end asm_819_arch; 3 Problem Solutions Chapter 8 clk reset a b c state st1 z 0 50 100 150 st2 st3 st1 st2 st1 st2 st3 st1 8-20.* module asm_820 (CLK, RESET, A, B, C, Z) ; input CLK, RESET, A, B, C ; output Z ; reg [1:0] state, next_state; parameter ST1=2'b00, ST2=2'b01, ST3=2'b10; reg Z; //State register always @(posedge CLK or posedge RESET) begin if (RESET) //asynchronous RESET active High state <= ST1; else //use CLK rising edge state <= next_state; end //Next state function always @(A or B or C or state) begin case (state) ST1: next_state <= A ? ST2: ST1; ST2: next_state <= (B && ! C) ? ST1: ST3; ST3: next_state <= ST1; default: next_state <= ST1; endcase end //Output function always @(B or state) begin case (state) ST1: Z <= 1'b0; ST2: Z <= B ? 1'b1: 1'b0; ST3: Z <= 1'b1; default: Z <= 0'b0; endcase end endmodule CLK RESET A B C Z state 00 0 01 50 10 00 01 100 00 01 150 10 00 4
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