Cmpe 2030 A Introduction to Computer Engineering Quiz -II May 7th , 1999 There are 7 questions and 10 pages including the cover sheet and two blank work sheets. Please make sure that you have all of them. This examination is closed textbook. No calculators, class notes or any material is allowed! 1. Please show all of your work 2. State any assumptions you feel you have to make or ask for clarification 3. Keep in mind it is difficult to give partial credit without written material. Please make sure you document any partial solutions. 4. Points are stated next to each problem. Use them to plan your work! Question 1 2 3 4 5 6 7 Total Points 8 8 6 6 8 68 8 50 Graded Name:_________________________________________________ Student Number:_________________________________________ 1. Implement a synchronous binary counter that counts to ten. Use the minimum number of a basic toggle cell shown below. In addition you have at your all of the basic gates. Assume that the phi1 and phi2 clocks are available to all cells. Your design should include a global Enable signal and a global CLR signal (active low) that works for all counters. TE - Toggle Enable CLR - Clear TE Q CLR 2. Consider the boolean function specified with the truth table shown below. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Out 0 1 1 0 1 0 0 0 2 (a) Implement this function using a 4:1 multiplexor and inverters. Clearly label all signals including the inputs, output and multiplexor select lines. 3. This question is based on the following description of a priority encoder. IN0 0 X X X 1 IN1 0 0 0 1 0 IN2 0 X 1 X 0 IN3 0 1 0 X 0 OUT1 X 1 1 0 0 OUT0 X 1 0 1 0 Valid 0 1 1 1 1 3 (a) List the inputs from highest to lowest priority order. 3 (b) Implement OUT1 and OUT0 using basic gates. 4. Complete the timing diagram below for a single bit register cell constructed from a pair of transparent latches. input register cell phi1 phi2 output phi1 phi2 Input Out 5 (a) Convert the following numbers from one notation to the other. Base 10 157 32 Binary _____________ _____________ Hexadecimal ______________ ______________ Octal _____________ _____________ 5 (b) Convert the following numbers to the notation shown. IEEE 754 Floating Point in Hexadecimal Notation ____________________________ _____________________________ Base 10 22.625 1.0 Fixed Point Binary (e.g., 110.01 ______________________________ _____________________________ 5 (c) Perform the following operations. The numbers are represented in two complement s form. Identify the operations for which overflow occurs, i f any. 101100 + 010010 - 01101 01110 10111 + 11000 6. Complete the following timing diagram. Assume initial values of signals are zero. Ignore any propagation delays. 3-bit Synch Binary Counter S0 S1 S2 Binary Decoder C0 C1 C2 C3 C4 C5 C6 C7 phi1 phi2 phi1 phi2 1 C0 0 1 C2 0 7. Using 4:1 multiplexors shown below construct shift logic that will produce an output (b3b2b1b0) that is computed as a right shift or left shift of two bits of the input (a3a2a1a0). Assume a zero fill for the values shifted into the output B. For example, a right shift of 1100 by 2 bits will produce 0011.Fill in the truth table to reflect the operation being performed for each value of the select lines. 0 a3 a2 a1 a0 0 3 2 1 b3 0 3 2 1 b2 0 3 2 1 b1 0 3 2 1 b0 0 4:1 Mux s0 s1 4:1 Mux 4:1 Mux 4:1 Mux S0 0 0 1 1 0 1 0 1 S1 Operation shift right shift left no shift