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2030 Cmpe A Introduction to Computer Engineering Final Examination June 10th , 1999 There are 15 questions and 11 pages including the cover sheet and two blank work sheets and three data sheets. Please make sure that you have all of them. This examination is closed textbook. No calculators, class notes or any material is allowed! 1. Please write legibly. Use the work sheets if you need to. 2. Please show all of your work 3. State any assumptions you feel you have to make or ask for clarification 4. Keep in mind it is difficult to give partial credit without written material. Please make sure you document any partial solutions. 5. All questions carry equal points. Plan your work! 6.The exam is 2 hours and 50 minutes. Question 1 2 3 Total Points 15 15 20 50 Graded Name:_________________________________________________ Student Number:_________________________________________ 1. Provide a switch level implementation of the following expression using n-type and p-type switches. F = A B 2. Complete the following switch level circuit by designing the pull down network. Fill in the truth table and provide expressions for OUT, OUT, SOP using minterms and POS using maxterms. Truth Table A B C Out A B C C Out Out = ___________________________________________ Out = ___________________________________________ SOP = ___________________________________________ POS = ___________________________________________ 3 Implement the following expression using only NAND and NOT gates. Use the mixed logic notation we have used in class. Do not assume that the complements of the inputs are available. Do not simplify the expression. Provide the number of transistors in the implementation. F = ( A + B )C + AC + BCD #Transistors = ____________ 4 This questions deals with logic minimization using K-Maps. 4 (a) Simplify the following expression algebraically to a sum of products form. F = A + C + BC ( D + B ) Function _______________________________________ 4 (b) Fill in the K-Map for the preceding function. CD AB 00 01 00 01 11 C 10 B 11 A 10 D 4 (c) Circle all of the prime implicants and fill in the table shown to the side. CD AB 00 01 00 01 11 C 10 Prime Implicants Essential? y n B 11 A 10 D 4 (d) From the preceding K-Map provide the simplified boolean expression. Function = ____________________________ 5(a) Draw the gate level implementation of a 2:1 multiplexor. Clearly label all of the control, input, and output signals. 5 (b) Show how you can construct a 4:1 multiplexor using 2:1 multiplexors. Clearly label all control, input, and output signals. Clearly show all of the connections between multiplexors. 6. Consider the boolean function specified with the truth table shown below. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Out 1 1 1 0 0 0 1 1 Implement this function using a decoder. Clearly label all signals including the inputs, output and multiplexor select lines. 7. Perform the following operations. The numbers are represented in two' complement form. s Identify the operations for which overflow occurs, i f any. 101100 + 110011 - 01101 11110 10011 + 11110 7 (a) Consider 8 bit binary numbers that use 2' complement representation for negative nums bers. What is the range of values that can be represented with this number of bits? 8. Show the heaxadecimal value of the IEEE 754 floating point representation of -1.0. 8 (a) What is the result to of the following floating point operation? The numbers are shown in complete normalized IEEE 754 form: 1.101 x 2129 + 1.01 x 2122 9. Draw the gate level implementation of a D latch. 9 Complete (a) the timing diagram below for the circuit shown below. A B input transparent latch transparent latch transparent latch transparent latch phi1 phi2 phi1 phi2 phi1 phi2 Input 1 A 0 1 B 0 0 0 1 1 10. We wish to design a counter that only counts through the odd numbers up to 15. We will approach this as state machine design problem. Use the minimum number of a basic toggle cells shown below. In addition you have at your disposal all of the basic gates. Assume that the phi1 and phi2 clocks are available to all cells. Your design should include a global Enable signal and a global CLR signal (active low) that works for all cells. TE - Toggle Enable CLR - Clear TE Q CLR 10 (a) Draw the state machine diagram. 10 (b) Write the state transition table. 10 (c) Design the counter and show the implementation. You may use any technique you wish. 11 (a). What is the difference between memory based on DRAM cells and memory based on SRAM cells? 11 (b) The following illustrates the internal organization of a 4M x 4 memory chip. Assuming that the array is a square, i.e., has the same number of rows and columns answer the following with respect to this design. A R o w D e c o d e . . . Array . . . I/O Column Decode D CS WE # of bits reuqired for row decode __________________ Expression (in terms of CS and WE) for reading from the array _______________ 11 (c) Consider the availability of memory chips with 4M addresses and 8 bits at each address. Each chip has a chip select signal and a write enable signal and the chip interface is shown below. We wish to design memory system that can provide 16M addresses with 16 bits at each address. Show a design for such a memory system. In your design the following should be clearly marked: i) the number of address bits required of the memory system, ii) the number of address bits required of each memory chip, iii) an overall memory select signal, msel, for the memory system. ADDR D0.D3 CS WE 12. Consider the following SPIM program. The data segment starts at 0x10010000 and the text segment starts at 0x00400000. .data label: .word 0, 1, 2, 3, 4, 5, 6, 7 str: .asciiz "Final" .align 2 result: .word 4 .text addi $t5, $0, 8 add $t0, $0, $0 lw $t1, label($t0) add $t2, $t1, $t2 addi $t0, $t0, 4 addi $t5, $t5 -1 bne $t5, $0, loop sw $t2, result($t0) li $v0, 10 syscall begin: 12 (a) What is the final value of the contents of memory location labeled result? result _______________ 12 (b) What are the values of the labels str and result? str ___________________ result ___________________ 12 (c) Assume that the register $sp points to the top of the stack, this location contains the value on the top of the stack. Write a short SPIM program that pushes the contents of register $t0 onto the top of the stack. 13. Consider the single cycle datapath shown overleaf. Write the microcode to implement the following operation. Make sure you fill in the description column: R3 = R4-[(R2+6R1)/4]. The result should be stored in memory at location 1000. . imm imm au lu en va en a/s en su en ld st en en r/w msel cycle 1 2 3 4 5 6 7 8 9 10 X Y Z rwe lf st Descr 14. Consider the multicycle datapath shown overleaf. 14 (a) Draw the state machine for the control of this datapath. Clearly label the function of each state. The state machine should correspond to the implementation of the following instructions: add, sub, beq, lw, sw. 14 (b) Write the complete microcode for implementing the branch instruction. imm imm au lu en va en a/s en su en ld st en en r/w msel cycle 1 2 3 4 5 6 7 8 9 10 X Y Z rwe lf st Descr

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