WORK HOME # 3
Due Date: October 29, 2007
Q1) (4.11) State the phases of the instruction cycle and briefly describe what operations occur in each phase.
(a) Fetch: Get instruction from memory. Load address of next instruction in the Program Counter. (b) Decode: Find out what the instruction does. (c) Evaluate Address: Calculate address of the memory location that is needed to process the instruction (d) Fetch Operands: Get the source operands (either from memory or register file). (e) Execute: Perform the execution of the instruction. (f) Store Result: Store the result of the execution to the specified destination.
Q2) (4.8) Suppose a 32-bit instruction has the following format:
OPCODE DR SR1 SR2 UNUSED
If there are 255 opcodes and 120 registers, and every register is available as a source or destination for every opcode, 1. What is the minimum number of bits required to represent the OPCODE?
27 < 255 < 28 So, 8 bits
2. What is the minimum number of bits required to represent the Destination Register (DR)?
26 < 120 < 27 So, 7 bits
3. What is the maximum number of UNUSED bits in the instruction encoding?
32 (8 + 7 + 7 + 7) = 3 bits
Q3) If a computer has a 16-bit MAR and a 32-bit MDR: 1. How many memory locations are available in the memory of this computer?
2^16 = 65,536 locations
2. How many bits are stored at each of those locations?
32 bits
3. What is the total size of the memory (in Bytes)?
32 * 65,536 = 2,097,152 bits, so 2,097,152/8 = 262144 Bytes
Q4) (Prob 5.5) 1. What is an addressing mode?
Addressing mode: mechanism for specifying where an operand is located.
2. Name three places an instruction's operands might be located.
An instruction's operands are located as an immediate value, in a register, or in memory.
3. List the five addressing modes of the LC-3, and for each one state where the operand is located (from part b).
The 5 are: immediate, register, direct memory address, indirect memory address, base + offset address. An immediate operand is located in the instruction. A register operand is located in a register (R0 R7). A direct memory address, indirect memory address and base + offset address all refer to operands located in memory.
4. What addressing mode is used by the ADD instruction shown in Section 5.1.2?
Add R2, R0, R1 => register addressing mode.
Q5) (Prob 5.9) We would like to have an instruction that does nothing. Many ISAs actually have an opcode devoted to doing nothing. It is usually called NOP, for NO OPERATION. The instruction is fetched, decoded and executed. The execution phase is to do nothing! Which of the following three instructions could be used for NOP and have the program still work correctly? 1. 0001 001 001 1 00000
Add R1, R1, #0 => differs from a NOP in that it sets the Condition Codes.
2. 0000 111 000000001
BRnzp #1 => Unconditionally branches to one after the next address in the PC. There fore no, this instruction is not the same as NOP.
3. 0000 000 000000000
Branch that is never taken. Yes same as NOP
What does the ADD instruction do that the others do not do?
It sets the Condition Codes.
Q6) (Adapted 5.13) 1. How might one use a single LC-3 instruction to move the value in R2 into R3?
0001 010 011 1 00000 (ADD R3, R2, #0 )
2. Using only one LC-3 instruction and without changing the contents of any register, how might one set the condition codes based on the value that resides in R1?
0001 001 001 1 00000 (ADD R1, R1, #0 ) or 0101 001 001 1 11111 (AND R1, R1, #1)
3. Write an LC-3 instruction that clears the contents of R2.
0101 010 010 1 00000 (AND R2, R2, #0)
Q7) Classify the LC-3 instructions into operate, data movement or control instructions.
Operate ADD, AND, NOT Data Movement LD, LDI, LDR, ST, STI, STR, LEA. Control BR, JMP, JSR, JSRR, RET, RTI, TRAP.
Q8) (5.30) The following table shows a part of the LC-3s memory:
Address 0011 0001 0000 0000 0011 0001 0000 0001 0011 0001 0000 0010 0011 0001 0000 0011
Data 1001 001 001 111111 0001 010 000 000 001 1001 010 010 111111 0000 010 111111100
State what is known about R1 and R0 if the conditional branch redirects control to location x3100.
R1=R0 The assembly code for the given machine code is: NOT R1, R1; Inst 1 ADD R2, R0, R1; Inst 2 NOT R2, R2; Inst 3 BRz x3100; Inst 4 Since the branch is taken, Inst 3 (NOT R2, R2) should have set the condition code to 0. This implies Inst 3 stores a 0 in R2. Hence, R2 originally should have contained xFFFF. Going back to Inst 2, R0 + NOT(R1)=xFFFF. Hence R0=R1.
Q9) The following LC-3 Machine Language program is supposed to multiply the contents of R1 with R2 and store the result in R3. The program assumes that both R1 and R2 contain positive integers. However, there is an error in the program.
x3000: 0101 0110 1110 0000 0001 0110 1100 0010 0001 0010 0111 1111 0000 0111 1111 1101 1111 0000 0010 0101 1. What is the error?
The error is in the 4th instruction. It branches back if the result from the previous instruction was positive or zero, resulting in the loop being executed one extra time than is needed.
2. Modify the present program to make it work correctly
Everything should remain the same except the 4th line which should be 0000 0011 1111 1101. Now, it branches back only if the result was positive.
Q10) (5.28) It is the case that we REALLY don't need to have load indirect (1010) and store indirect (1011) instructions. We can accomplish the same results using other instruction sequences instead of using these instructions. Replace the store indirect (1011) instruction in the code below with whatever instructions are necessary to perform the same function. X3000 X3001 X3002 X3003 X3004 0010 0000 0000 0010 1011 0000 0000 0010 1111 0000 0010 0101 0000 0000 0100 1000 1111 0011 1111 1111
The above instructions are: X3000 : LD R0, x3003 X3001 : STI R0, x3004 X3002 : TRAP x25 X3003 : x0048 X3004 : xF3FF Here, we first load R0 with x0048, and then use STI instruction to store the contents of R0 (x0048) in memory location xF3FF. Alternatively, this can be done using the following instructions: X3000 : LD R0, x3004 (0010 0000 0000 0011) X3001 : LD R1, x3005 (0010 0010 0000 0011) X3002 : STR R0, R1, #0 (0111 0000 0100 0000) X3003 : TRAP x25 (1111 0000 0010 0101) X3004 : x0048 (0000 0000 0100 1000) X3005 : xF3FF (1111 0011 1111 1111)