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c246

Course Number: CSE 246, Fall 2008

College/University: UCSD

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Dose Map and Placement Co-Optimization for Timing Yield Enhancement and Leakage Power Reduction Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park and Hailong Yao ECE and CSE Departments, Univ. of California at San Diego, La Jolla, CA 92093 E-mail: {kjeong,chpark,hailong}@vlsicad.ucsd.edu, abk@ucsd.edu ABSTRACT In sub-100nm CMOS processes, delay and leakage power reduction continue to be among the most critical...

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Map Dose and Placement Co-Optimization for Timing Yield Enhancement and Leakage Power Reduction Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park and Hailong Yao ECE and CSE Departments, Univ. of California at San Diego, La Jolla, CA 92093 E-mail: {kjeong,chpark,hailong}@vlsicad.ucsd.edu, abk@ucsd.edu ABSTRACT In sub-100nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of ne-grain exposure dose control in the stepper to achieve both design-time (placement) and manufacturing-time (yield-aware dose mapping) optimizations of timing yield and leakage power. Our placement and dose map co-optimization can simultaneously improve both timing yield and leakage power of a given design. We formulate the placement-aware dose map optimization as a quadratic program, and solve it using an efcient quadratic programming solver. In this paper, we mainly focus on the placement-aware dose map optimization problem; in the Appendix, we describe the complementary but less impactful dose map-aware placement optimization, and an efcient cell swapping heuristic. Experimental results are promising: with typical 90nm stepper (ASML Dose Mapper) parameters, we achieve more than 8% improvement in minimum cycle time of the circuit without any leakage power degradation. Categories and Subject Descriptors B.7.2 [Hardware]: INTEGRATED CIRCUITSDesign Aids; J.6 [Computer Applications]: COMPUTER-AIDED ENGINEERING General Terms Algorithms, Design, Performance Keywords Dose Map, Placement, Timing Yield, Leakage Power Reduction 1. INTRODUCTION Continued scaling of feature sizes in integrated circuits (ICs) drives improvements of integration complexity and device speed with each successive technology node. In sub-100nm process nodes, manufacturing variations are the primary sources of design performance variability and parametric yield loss. To minimize the impact of manufacturing variations on performance variability, the manufacturing process itself can be improved, and/or designs can be made robust to variations. Improvements to the manufacturing process require, most prominently, advanced techniques in reticle enhancement, mask making, and optical lithographic equipment all of which increase the manufacturing cost and subsequently the design cost. As a result, so-called Design for Manufacturability (DFM) techniques [1] have received great attention within the electronic design and electronic design automation communities. Critical dimension (CD) variation is a dominant factor in the variation of delay and leakage current of transistor gates in integrated circuits. With advanced manufacturing processes, CD variation is worsening due to a variety of systematic variation sources at both within-die and reticle- or wafer-scale; the latter sources include radial bias of spin-on photoresist thickness, etcher bias, reticle bending, uniformity of wafer starting materials, etc. A statistical leakage minimization method is proposed in [2], which obtains signicant improvement in total leakage reduction by simultaneously varying the threshold voltage, gate sizes and gate lengths. [3] proposed to apply gate-length (CD) biasing only on the devices in non-critical paths for leakage power control without negative effects on timing. A recent technology from ASML, called DoseMapper [7, 8], allows for optimization of ACLV (Across-Chip Linewidth Variation) and AWLV (Across-Wafer Linewidth Variation)1 using an exposure dose (or, simply, dose) correction scheme. DoseMapper in the ASML tool parlance exercises two degrees of control, Unicom-XL and Dosicom [5], which respectively change dose proles along the lens slit and the scan directions of the stepand-scan exposure tool. Today, the DoseMapper technique is used solely (albeit very effectively - e.g., [6]) to reduce ACLV or AWLV metri...
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