4 Chapter Simple Calculations
Arthur B. Maccabe Department of Computer Science The University of New Mexico
Copyright 19932000, Arthur B. Maccabe and McGraw-Hill, Inc.
Overview
Slide 1
Preliminaries RISC/CISC registers, load/store architecture SPARC data manipulation instructions registers and data paths arithmetic, logical (bitwise), and shift instructions sethi and synthetic instructions SPARC Control Flow labels and unconditional branches conditional branching nullication encoding branching instructions translation issues
1
Introduction
Slide 2
Slide 3
Architecture: the design of an instruction set Organization: the implementation of an instruction set SPARC (Scalable Processor ARChitecture) RISC (Reduced Instruction Set Computer) architecture an open standard Register windows and resource management Binary compatibility Backward compatibility
Preliminaries
RISC/CISC reduced/complex instruction set computer the complexity of individual instructions changing role of assembly language programming Kinds of instructions data transfer data mainpulation control ow Statements, operations, and operands single operation per instruction operations include store (e.g., multiply-and-store) source operands provide values destination operand provides a location
2
Preliminaries: Registers
Slide 4
Registers Main memory L2 cache CPU L1 cache
Preliminaries: Memory/Memory Architecture
Slide 5
Memory Registers ALU
3
Preliminaries: Load/Store Architecture
Slide 6
Memory
load Registers store ALU
Data Manipulation Instructions
Slide 7
Background Machine language formats Internal data paths Assembly language Arithmetic instructions Logical (bitwise) instructions Shift and 32-bit shift instructions sethi (set high) Synthetic instructions 32-bit multiply and divide instructions
4
SPARC Background
Slide 8
31 30 29
Slide 9
Basic sizes 32-bit word 64-bit double (or extended) word Registers 32 64-bit registers %r0 through %r31 %r0 is always zero
SPARC Instruction Formats
25 24 19 18 14 13 12 5 4 0
10
rd
op3
rs1
0
00000000
rs2
Register-register 10 rd op3 rs1 1 simm13
Register-immediate
Field rd op3 rs1 rs2 simm13 Meaning Destination register Op code First source register Second source register Second source value in 13-bit 2s complement representation
5
Internal Data Paths
64 64 64
Slide 10
Sign extend
13
Registers
64
ALU
Instruction Register
Arithmetic Instructions
Operation Integer add Integer subtract 00 0100 op3 00 0000 Assembly syntax add add sub sub 00 1001 rs1 , rs2 , rd rs, siconst13 , rd rs1 , rs2 , rd rs, siconst13 , rd Operation implemented reg[rd]=reg[rs1 ]+reg[rs2 ] reg[rd]=reg[rs]+siconst13 reg[rd]=reg[rs1 ] reg[rs2 ] reg[rd]=reg[rs] siconst13 reg[rd]=reg[rs1 ] reg[rs2 ] reg[rd]=reg[rs] siconst13 reg[rd]=reg[rs1 ] reg[rs2 ] reg[rd]=reg[rs] siconst13
4096 to 4095, inclusive.
Slide 11
Integer multiply Integer divide 10 1101 mulx rs1 , rs2 , rd mulx rs, siconst13 , rd sdivx rs1 , rs2 , rd sdivx rs, siconst13 , rd
Destination last
6
Note: siconst13 denotes a signed integer constant in the range
Encoding Example 1
Slide 12
Slide 13
SPARC instruction: mulx %r1, 2, %r1 Format
31 30 29 25 24 19 18 14 13 12 5 4 0
10
rd
op3
rs1
1
simm13
Field values
Field rd op3 rs1 simm13 Value %r1 mulx %r1 2 Encoded value 00001 001001 00001 0000000000010
Encoding: 10 00001 001001 00001 1 0000000000010 or 0x82486002
Encoding Example 2
SPARC instruction: add %r1, %r10, %r1 Format
31 30 29 25 24 19 18 14 13 12 5 4 0
10
rd
op3
rs1
0
00000000
rs2
Field values
Field rd op3 rs1 rs2 Value %r1 add %r1 %r10 Encoded value 00001 000000 00001 01010
Encoding: 10 00001 000000 00001 0 00000000 01010 or 0x8200400A
7
Assembly Language Example
Line oriented
Comments start with !
Logical (Bitwise) Instructions
Operation And op3 00 0001 Assembly syntax and rs1 , rs2 , rd and rs, siconst13 , rd And not 00 0101 andn rs1 , rs2 , rd andn rs, siconst13 , rd or or 10 0110 rs1 , rs2 , rd rs, siconst13 , rd Operation implemented reg[rd]=reg[rs1 ]&reg[rs2 ] reg[rd]=reg[rs]&siconst13 reg[rd]=reg[rs1 ]& reg[rs2 ] reg[rd]=reg[rs]& siconst13 reg[rd]=reg[rs1 ] reg[rs2 ] reg[rd]=reg[rs] s iconst13 reg[rd]=reg[rs] reg[rd]=reg[rs1 ]
Slide 15
Exclusive xor Exclusive xor not
00 0011
xor rs1 , rs2 , rd or rs, siconst13 , rd xorn rs1 , rs2 , rd orn rs, siconst13 , rd
reg[rd]=reg[rs1 ]reg[rs2 ] reg[rd]=reg[rs]siconst13 reg[rd]=reg[rs1 ] reg[rs2 ] reg[rd]=reg[rs] siconst13
10 0111
8
or not
orn rs, siconst13 , rd
Inclusive
orn rs1 , rs2 , rd
or
Inclusive
00 0010
Slide 14
a a2 bcd a is in %r1, b is in %r2, c is in %r3, and d is in %r4 mulx mulx mulx add %r1, 2, %r1 %r2, %r3, %r10 %r10, %r4, %r10 %r1, %r10, %r1 ! ! ! ! a=a 2 t1 = b c t1 = t1 d a = a + t1
reg[rs2 ] siconst13
Examples
Slide 16
Clear all but the least signicant 10 bits in register %r4 and %r4, 0x3ff, %r4
Set all but the least signicant 10 bits in register %r4 orn %r4, 0x3ff, %r4
Operation left shift logical right shift
Slide 17
logical right shift arithmetic 10 0111
Logical shifts ll vacated bit positions with 0
Arithmetic right shifts replicate the sign bit
Compute the 8-bit, bitwise logical and for 11100011 and 10101010 11100011 & 10101010 10100010 Compute the 8-bit, bitwise logical or for 11100011 and 10101010 11100011 10101010 11101011
Shift Instructions
op3 10 0101 Assembler syntax sllx rs1 , rs2 , rd sllx rs1 , iconst6 , rd 10 0110 srlx rs1 , rs2 , rd srlx rs1 , iconst6 , rd srax rs1 , rs2 , rd srax rs1 , iconst6 , rd Operation implemented reg[rd] = reg[rs1 ] reg[rs2 ] reg[rd] = reg[rs1 ] iconst6 reg[rd] = reg[rs1 ] reg[rs2 ] reg[rd] = reg[rs1 ] iconst6 reg[rd] = reg[rs1 ] reg[rs2 ] reg[rd] = reg[rs1 ] iconst6
Note: iconst6 denotes an integer constant in the range 0 to 63, inclusive.
9
Encoding Shift Instructions
31 30 29 25 24 19 18 14 13 12 11 6 5 4 0
10
rd
op3
rs1
01
0000000
rs2
Register-register 10 rd op3 rs1 11 000000 shcnt64
Slide 18
Register-immediate
Field rd op3 rs1 rs2 shcnt64 Meaning Destination register Op code First source register Second source register Second source value in 6-bit binary representation
32-bit Shift Instructions
Operation left shift logical right shift logical 10 0110 op3 10 0101 Assembler syntax sll rs1 , rs2 , rd sll rs1 , iconst5 , rd srl rs1 , rs2 , rd srl rs1 , iconst5 , rd 10 0111 sra rs1 , rs2 , rd sra rs1 , iconst5 , rd Operation implemented reg[rd] = reg[rs1 ] reg[rs2 ] reg[rd] = reg[rs1 ] iconst5 reg[rd] = reg[rs1 ] reg[rs2 ] reg[rd] = reg[rs1 ] iconst5 reg[rd] = reg[rs1 ] reg[rs2 ] reg[rd] = reg[rs1 ] iconst5
Slide 19
right shift arithmetic
Note: iconst5 denotes an integer constant in the range 0 to 31, inclusive.
sll is sllx with a reduced shift count srl sets the most signicant 32 bits to 0, then acts like srlx sra copies the 32-bit sign bit into most signicant 32 bit, then acts like srax
10
Encoding 32-bit Shift Instructions
31 30 29 25 24 19 18 14 13 12 11 5 4 0
10
rd
op3
rs1
00
0000000
rs2
Register-register 10 rd op3 rs1 10 0000000 shcnt32
Slide 20
Register-immediate
Field rd op3 rs1 rs2 shcnt32 Meaning Destination register Op code First source register Second source register Second source value in 5-bit binary representation
sethi: Motivation
Using a sequence of shift and or instructions, set the register %r2 to the 64-bit value 0x1234567887654321. or sllx or sllx or sllx or sllx or sllx or %r0, 0x123, %r2 %r2, 12, %r2 %r2, 0x456, %r2 %r2, 12, %r2 %r2, 0x788, %r2 %r2, 12, %r2 %r2, 0x765, %r2 %r2, 12, %r2 %r2, 0x432, %r2 %r2, 4, %r2 %r2, 0x1, %r2 ! ! ! ! ! ! ! ! ! ! ! start with the most signicant 12 bits make room for the next 12 bits the next 12 bits make room for the next 12 bits the next 12 bits make room for the next 12 bits the next 12 bits make room for the next 12 bits the next 12 bits make room for the next 4 bits the last 4 bits
Slide 21
11
sethi
Set the register %r2 to the 64-bit value 0x1234567887654321. sethi or sllx sethi or or 0x12345, %r2 %r2, 0x678, %r2 %r2, 32, %r2 0x87654, %r3 %r3, 0x321, %r3 %r2, %r3, %r2 ! ! ! ! ! ! set bits 31 through 12 ll in bits 0 through 11 shift to the most signicant bits set bits 31 through 12 ll in bits 0 through 11 combine the two 32-bit values
Slide 22
Encoding sethi Instructions
31 30 29 25 24 22 21 0
00
rd
100
imm22
Slide 23
Field rd imm22 Meaning Destination register The 22-bit immediate value
12
%uhi(), %ulo(), %hi() and %lo()
Operator Slide 24 %uhi(val) %ulo(val) %hi(val) %lo(val) Value bits 6342 of val bits 4132 of val bits 3110 of val bits 90 of val
Using %uhi(), %ulo(), %hi() and %lo()
Set the register %r2 to the 64-bit value 0x1234567887654321. Slide 25
sethi or sllx sethi or or %uhi(0x1234567887654321), %r2 %r2, %ulo(0x1234567887654321), %r2 %r2, 32, %r2 %hi(0x1234567887654321), %r3 %r3, %lo(0x1234567887654321), %r3 %r2, %r3, %r2 ! ! ! ! ! ! set bits 31 through 12 ll in bits 0 through 11 shift to most signif. bits set bits 31 through 12 ll in bits 0 through 11 combine two 32-bit values
13
Synthetic Data Manipulation Instructions
Synthetic instr. not rs, rd not rd neg rs, rd neg rd Implementation xnor rs, %r0, rd xnor rd, %r0, rd sub %r0, rs, rd sub %r0, rd, rd add rd, 1, rd add rd, siconst13 , rd sub rd, 1, rd sub rd, siconst13 , rd or or rd, rs, rd rd, siconst13 , rd set bits decrement increment negation Comment invert bits
Slide 26
inc rd inc siconst13 , rd dec rd dec siconst13 , rd bset rs, rd bset siconst13 , rd
Synthetic Data Manipulation Instructions (continued)
Synthetic instr. bclr rs, rd bclr siconst13 , rd Implementation andn rd, rs, rd andn rd, siconst13 , rd xor rd, rs, rd xor rd, siconst13 , rd or or or %r0, %r0, rd %r0, rs, rd %r0, siconst13 , rd clear (zero) a register copy rs to rd set rd to siconst13 toggle bits Comment clear bits
Slide 27
btog rs, rd btog siconst13 , rd clr rd
mov rs, rd mov siconst13 , rd
14
Synthetic Instructions for 32- and 64-bit Values
Synthetic instr. Implementation srl rs, %r0, rd srl rd, %r0, rd sra rs, %r0, rd sra rd, %r0, rd sign extend a 32-bit value Comment clear upper word
Slide 28
clruw rs, rd clruw rd signx rs, rd signx rd
The set unsigned word Synthetic Instructions
Synthetic instr. setuw val, rd set unsigned word Implementation sethi %hi(val), rd or Condition
or sethi %hi(val), rd or set val, rd %r0, %lo(val), rd
otherwise
synonym for setuw
15
Slide 29
or
%r0, val, rd
0
val
4095
val&0x3ff
0
The set signed word Synthetic Instructions
Synthetic instr. setsw val, rd set signed word or Implementation sethi %hi(val), rd or Condition
or sethi %hi(val), rd
Slide 30
sra
rd, %r0, rd or
or
%r0, %lo(val), rd or
or sra
%r0, %lo(val), rd rd, %r0, rd
The set extended word Synthetic Instructions
Synthetic instr. setx val, tmp, rd Implementation sethi tmp %uhi(val), or tmp, %ulo(val), tmp Condition worst case, optimizations are possible
Slide 31
set extended (tmp is a temporary register)
sllx tmp, 32, tmp sethi %hi(val), rd or or rd, tmp, rd rd, %lo(val), rd
16
sethi %hi(val), rd
otherwise, if val
sethi %hi(val), rd
otherwise, if val
0
0
val
0 && val & 0x3ff
%r0, val, rd
4096
val
4095
0
val && val & 0x3ff
0
0
32-bit Multiply
32 32 32
Slide 32
Sign extend
13
Registers
Y
32 32
smul/umul
Instruction Register
most significant least significant
32-bit Divide
32 least significant 32 most significant 32
Slide 33
32
Sign extend
13
Registers
Y
32 32
sdiv/udiv
Instruction Register
remainder quotient
17
Control Transfer Instructions
Slide 34
18
Slide 35
Using simple gotos
temp = y; x = 0; top: if( temp z ) goto bottom x = x + 1; temp = temp z; goto top; bottom:
Conditional and unconditional branches Labels and unconditional branches on the SPARC Delayed branches Register comparison to zero Condition code registers Encoding branching instructions Loop improvements Complex conditional expressions
An Example
Using a while loop
temp = y; x = 0; while( temp z ) x = x + 1; temp = temp z;
Labels
Slide 36
Slide 37
A label is an identier (and follows the standard rules for identier formation). The denition of a label occurs when the label appears as the rst non-white space item on a line followed by a colon (:). Each label can have at most one denition. The value of the label is the address of the next instruction (which may be on the same line as the label). Whenever you use a label in a non dening context, the assembler substitutes the value of the label for the label. You may use a label before you give its denition.
Delayed Branching
Unconditional branch: ba %xcc, label
Two program counters: pc and npc An example
Code s1: s2: s3: s4: s5: s6: s7: inc ba inc inc inc inc inc %r1 %xcc, s5 %r3 %r4 %r5 %r6 %r7 s5 s6 s6 s7 sequential execution pc s1 s2 s3 npc s2 s3 s5 Comment start sequential execution (delayed) branch to s5
The nop instruction
19
Translating the Unconditional Branch
Assume x is stored in %r2, y is stored in %r3, z is stored in %r4, and temp is stored in %r5 mov %r3, %r5 clr %r2 Slide 38 top: inc sub ba nop bottom: ! temp = y; ! x = 0; if( temp z ) goto bottom x = x + 1; temp = temp - z; goto top; delay slot
Eliminating the nop
mov %r3, %r5 clr %r2 top: inc ba sub bottom: Slide 39 ! temp = y; ! x = 0; if( temp z ) goto bottom x = x + 1; goto top; temp = temp - z; delay slot
20
!
! %r2 ! %xcc, top ! %r5, %r4, %r5 !
!
! %r2 ! %r5, %r4, %r5 ! %xcc, top ! !
Conditional Branching
Slide 40
Slide 41
brgz rs, label brgez rs, label
reg[rs] reg[rs]
21
% $ #
brnz rs, label
reg[rs]
!
brlz rs, label
reg[rs]
"
brlez rs, label
reg[rs]
Register comparison to zero Condition codes
Register Comparison to Zero
Assembler syntax brz rs, label Branching condition reg[rs] 0 0 0 0 0 0
Using Comparisons to Zero
Using Comparisons to Zero (continued)
Avoiding temp2
temp = y z; x = 0; top: if( temp 0 ) goto bottom x = x + 1; temp = temp z; goto top; bottom:
Slide 43
22
Slide 42
Simple translation
temp = y; x = 0; top: temp2 = temp z; if( temp2 0 ) goto bottom x = x + 1; temp = temp z; goto top; bottom:
Translating into SPARC Code
top: Slide 44
%r2 %xcc, top %r5, %r4, %r5
bottom:
Avoiding the nop Instruction
top: Slide 45
bottom: dec %r2 ! make up for the extra inc
23
!
brlz inc ba sub
%r5, bottom %r2 %xcc, top %r5, %r4, %r5
! ! ! !
if( temp 0 ) goto bottom x = x + 1; delay slot goto top; temp = temp - z; delay slot
&
sub clr
%r3, %r4, %r5 %r2
! temp = y ! x = 0;
!
brlz nop inc ba sub
%r5, bottom
! ! ! ! !
if( temp 0 ) goto bottom branch delay slot x = x + 1; goto top; temp = temp - z; delay slot
&
sub clr
%r3, %r4, %r5 %r2
! temp = y ! x = 0;
z;
z;
Condition Codes
Slide 46
First translation c = a b; if( c 0 ) goto ; a = a + 1; : Translation to SPARC code
sub brlez nop inc : %r2, %r3, %r4 %r4, %r2
24
"
Slide 47
! ! ! !
'
$
&
(
Example Condition code bits (ags) Setting the condition codes Conditional branching based on condition codes
Another Example
The code if( a b ) a = a + 1;
c = a b; if( c 0 ) goto ; branch delay slot a = a + 1;
Condition Code Bits (Flags)
Slide 48
Slide 49
Summarize the result of an earlier operation Four ags: Z, zero N, negative C, carry V, overow
Setting the Condition Code Bits
Operations that update the condition codes Operation integer addition integer subtraction bitwise and bitwise and not bitwise or bitwise or not bitwise xor bitwise xor not Name addcc subcc andcc andncc orcc orncc xorcc xorncc op3 01 0000 01 0100 01 0001 01 0101 01 0010 01 0110 01 0011 01 0111 Operations that do not affect the condition codes Name add sub and andn or orn xor xorn op3 00 0000 00 0100 00 0001 00 0101 00 0010 00 0110 00 0011 00 0111
25
Synthetic Instructions that Update the Condition Code
Synthetic instr. cmp rs1 , rs2 cmp rs, siconst13 tst Slide 50 rs Implementation subcc rs1 , rs2 , %r0 subcc rs, siconst13 , %r0 orcc %r0, rs, %r0 addcc rd, 1, rd addcc rd, siconst13 , rd subcc rd, 1, rd subcc rd, siconst13 , rd andcc rd, rs, rd andcc rd, siconst13 , rd test bits decrement test increment Comment compare
inccc rd inccc siconst13 , rd deccc rd deccc siconst13 , rd btst btst rs, rd siconst13 , rd
The Condition Codes
Slide 51
Two condition codes are updated The 32-bit result: %icc The 64-bit result: %xcc
26
Branching Based on the Condition Codes
Name ba bn bne Condition always never Z Z Z Z Comment unconditional branch always unconditional branch never not equal (to zero) nonzero (a synonym for bne) equal (to zero) zero (a synonym for be) greater (than zero)
Slide 52
bnz be bz
bge bl
N xorV N xorV
Branching Based on the Condition Codes (continued)
Name bgu bleu bcc bgeu Condition C or Z C or Z C C Comment greater (than zero), unsigned less or equal (to zero), unsigned carry clear greater or equal (to zero), unsigned (synonym for bcc) bcs blu bpos bneg bvc bvs C C N N V V carry set less (than zero), unsigned positive negative overow clear overow set
Slide 53
0
)
ble
Z or
N xorV
0
)
bg
Z or
N xorV
Less or equal (to zero) greater or equal (to zero) less (than zero)
27
SPARC Code Examples
Slide 54
:
Using a cmp synthetic instruction cmp %r2, %r3 ble %xcc, ! if( a b ) goto ; nop ! branch delay slot inc %r2 ! a = a + 1; :
Nullication: Motivation
Cancelling the effect of an instruction in the branch delay slot
Example original cmp %r2, %r3 ble %xcc, ! if( a b ) goto ; nop ! branch delay slot inc %r2 ! a = a + 1; : without using a nop instruction cmp bg inc dec : %r2, %r3 %xcc, ! if( a b ) goto ; %r2 ! a = a + 1; delay slot %r2 ! a = a 1; cancel
Slide 55
28
"
"
&
"
&
$
Basic translation sub %r2, %r3, %r0 ble %xcc, nop inc %r2 ! ! ! ! a b; if( c 0 ) goto ; branch delay slot a = a + 1;
Nullication
:
Encoding Branches Using Register Comparison to Zero
31 30 29 28 27 25 24 22 21 20 19 18 14 13 0
00 a 0 rcond
011
dhi p
rs1
Field a rcond dhi p rs1 d16lo
Meaning Annul (nullify): 1 to annul the instruction in the delay slot Branching condition Most signicant 2 bits of the displacement Prediction: 1 to predict branch taken, 0 to predict branch not taken Source register Least signicant 14 bits of the displacement
Slide 57
Name brz brlez brlz
rcond 001 010 011
Name brnz brgz brgez
29
$
Slide 56
For conditional branching instructions: branch taken: instruction in delay slot is executed branch not taken: affect of instruction in delay slot can be nullied For unconditional branching (ba and bn): instruction in delay slot can be nullied Specied by concatenating ,a to the operation name SPARC uses the name annul instead of nullify Example cmp %r2, %r3 bg,a %xcc, inc %r2 ! if( a b ) goto ; ! a = a + 1; delay slot
d16lo
rcond 101 110 111
Displacement Addressing
Displacement Sign extend *4 + Program Counter (PC)
Slide 58
Encoding Branches Based on the Condition Codes
31 30 29 28 25 24 22 21 20 19 18 0
00 a
cond
001
cc p
disp19
Slide 59
Field a cond cc p disp19
Meaning Annul (nullify): 1 to annul the instruction in the delay slot Branching condition Condition code used in branching: 00 for %icc, 10 for %xcc Prediction: 1 to predict branch taken, 0 to predict branch not taken 19-bit displacement
30
Encoding the Condition
Name bn be, bz Slide 60 ble bl bleu bcs, blu bneg bvs cond 0000 0001 0010 0011 0100 0101 0110 0111 Name ba bne, bnz bg bge bgu bcc, bgeu bpos bvc cond 1000 1001 1010 1011 1100 1101 1110 1111
Instruction Encoding Examples
Slide 61
bot:
31
Code
top: brlz inc ba sub %r5, bot %r2 %xcc, top %r5, %r4, %r5 ! ! ! ! if( temp 0 ) goto bot x = x + 1; delay goto top; temp = temp - z; delay
Instruction Encoding Examples (Continued)
Slide 62
Slide 63
Encoding the brlz instruction Format
31 30 29 28 27 25 24 22 21 20 19 18 14 13 0
00 a 0 rcond 011 dhi p
rs1
d16lo
Field values
Field a rcond dhi p rs1 d16lo Encoding 0 011 00 1 00101 00000000000011
Encoding: 00 0 0 011 011 00 1 00101 00000000000011 or 0x06c94003.
Instruction Encoding Examples (Continued)
Encoding the ba instruction Format
31 30 29 28 25 24 22 21 20 19 18 0
00 a
cond
001
cc p
disp19
Field values
Field a cond cc p disp19 Encoding 0 1000 10 1 1111111111111111110
Encoding: 00 0 1000 001 10 1 1111111111111111110 or 0x106ffffe.
32
Translating Loops
Slide 64
Slide 65
33
&
&
%
Translate to code that uses simple conditional unconditional branches Try to eliminate unconditional branches in loops Translate to SPARC assembly code, using nop instructions in the branch delay slots Put real instructions in the branch delay slots
Eliminate Unconditional Branches in Loops
Move the test to the bottom of the loop Example temp = y z; x = 0; goto test; top: x = x + 1; temp = temp z; test: if( temp 0 ) goto top;
Translate to SPARC Code
Slide 66
top: inc sub test: %r2 %r5, %r4, %r5 ! x = x + 1; ! temp = temp - z; ! if( temp 0 ) goto top ! branch delay slot
Put Real Instructions in the Branch Delay Slots
Slide 67
top: sub test: %r5, %r4, %r5 ! temp = temp - z; ! if( temp 0 ) goto top ! x = x + 1; delay slot
34
%
brge,a %r5, top inc %r2
&
sub ba clr
%r3, %r4, %r5 %xcc, test %r2
! temp = y z; ! goto test; ! x = 0; delay slot
%
brge %r5, top nop
&
sub clr ba nop
%r3, %r4, %r5 %r2 %xcc, test
! ! ! !
temp = y z; x = 0; goto test; branch delay slot
More Complex Conditional Expressions
&
%
%
Slide 68
Translation if( 20 a ) goto fals1; if( a 200 ) goto fals1; b = 100; goto 1; fals1: b = 100; 1:
35
'
!
&
'
!
( (
Example if( 20 a && a b = 100; else b = 100; 200 )