5263 ECEN Spring 2008
Design Project 2 Part A Due Wed. Feb. 6, 1700 Use the cadence tools to layout a circuit that implements one bit comparator described by the following table. The output, Z, is 1 when the input bits, X and Y, are the same.
X 0 0 1 1 Y 0 1 0 1 Z 1 0 0 1
This is also called the exclusive NOR (XNOR) gate. Only the uninverted inputs X and Y will be provided. If you need the inverted inputs, you must provide the inverters as part of your layout. Make the spacings and line widths as small as possible without making any design rule errors. You can make the circuit out of logic gates of any size you like or use a MUX based design (hint: the MUX based design is smaller if you use transmission gates for the MUX). You must choose an implementation that has an area smaller than 3000 2 (24.3 m2) if you want to avoid an area penalty. Be sure to include substrate contacts near power and ground contacts to prevent latch up. All power lines should be connected and named vdd. All ground lines should be connected and named gnd. If you wish, you can test your design before you submit it. A trial test file can be found in /x/lgjohn/public/ecen5263 in the file xnor.spin. This test file demands that your circuit be faster than 3 nsec. Unless you have done something really weird, your design should meet this requirement easily. Use the following with the automatic grader to submit the xnor cell. Class Name: ecen5263 Project Name: proj2a Project Directory: xnor_proj Library Name: xnor_lib Cell Name: xnor Part B Due Wed. Feb. 13, 1700 Make a higher level cell named xnor8. Make a copy (an instance) of your xnor cell (see the attached tutorial). Then make 7 more copies (instances) side by side. You should change the layout of your xnor cell if necessary so that all of the power and ground lines
ECEN 5263 Spring 2008 January 30, 2008 page 1 of 4
are connected automatically when the cells are butted together. The X and Y inputs and Z outputs should not be connected so that your xnor8 cell has 8 separate X inputs, 8 separate Y inputs, and 8 separate Z outputs. Node names correspond to the pin names in the highest level cells. In order to avoid confusion, node names in lower level cells have node names that are modified. For example, each one of the X inputs is assigned a different node name by the circuit extractor. The automatic node renaming can be overridden by attaching a new name in the high level cell. In the xnor8 cell, attach pins to the 8 X inputs named X0 to X7, the 8 Y inputs named Y0 to Y7, and the 8 Z outputs named Z0 to Z7. If you wish, you can test your design before you submit it. A trial test file can be found in /x/lgjohn/public/ecen5263 in the file xnor8.spin. This test file demands that your circuit be faster than 3 nsec. Unless you have done something really weird, your design should meet this requirement easily. Use the following with the automatic grader to submit the xnor8 cell (do not forget to include your xnor cell as described in the following tutorial). Class Name: ecen5263 Project Name: proj2b Project Directory: xnor8_proj Library Name: xnor8_lib Cell Name: xnor8
Creating a Hierarchical Design
When designing large circuits in VLSI, it is often easier to instantiate (copy) previously created cells into the current design you are working on, thereby creating a larger circuit consisting of subcells. The purpose of this tutorial is to aid you in creating a hierachical design using Virtuoso Layout Editor (icfb) that is compatible with the automatic grader. Lets assume that the xnor cell of project 2a is to be instantiated (copied) into a larger circuit which we will assume is xnor8 of project 2b. Ordinarily, Virtuoso allows from cells any library to be instantiated. The library can be anywhere, including outside of the project directory. All you have to do is use the library path editor to define the library name and the path to it (see details below). This makes it easy to use previously designed cells as building blocks to make larger designs. The automatic grader requires that all libraries must be inside the project directory. This restriction means that the xnor cell inside the xnor_lib library in the xnor_proj directory must be copied to a library inside the xnor8_proj directory (assuming you dont want to redraw the layout).
ECEN 5263 Spring 2008
January 30, 2008
page 2 of 4
1.0 Goal
What we are attempting to do here is to copy the cell containing the design to be used as a subcell (xnor) into the project directory containing the larger design (xnor8). This allows the cells from other projects to be instantiated as subcells into your current project so that the cells will be recognized by the automatic grader.
2.0 Project Directory
1. Create a NEW project directory (xnor8_proj). It is IMPORTANT that you cd into this project directory and execute cdsinit before starting the Cadence tools. 2. Type icfb &
3.0 Design Library
1. Library Manager --> File --> New --> Library... Type a name for the library (xnor8_lib) and place a . (period) in the path section of the form. Proceed to attach the library to an existing tech library. Click OK
4.0 Library Path Editor
Since we are in an entirely new project directory, we will not be able to see the xnor cell or any other cell created previously in other project directories. We need to be able to see those libraries before we attempt to copy any cell into the current library. However, this can be fixed using the following steps: 1. Library Manager --> Tools --> Library Path Editor... 2. Put in a reference name (it can be any name you wish, but not xnor8_lib) and complete the absolute path to the cell library (or any other cell library) created previously. For example: Library Path old_lib /x/lgjohn/5263/xnor_proj/xnor_lib 3. Library Path Editor --> File --> Save 4. Library Path Editor --> File --> Exit
5.0 Library Manag...