6253 ECEN Spring 2007 Design Project B1
Part A Due Friday, Feb. 2, 1700 hrs. One of project A1 and B1 are required. You may do them both for extra credit. This is a continuation of the last project in ECEN 5253 to give you chance to complete a simple pipelined processor. Delayed branching will be added using the architecture optimized for branching shown in fig. 6.51, p. 499 of Patterson and Hennessey. It should run at a 100 MHz clock rate (a full clock cycle is 10 nsec. and a half cycle is 5 nsec.). This time, you will need the equality detection logic and the adder to compute the branch address. Forwarding logic and hazard detection logic will NOT be needed for this project. You need only what is shown below.
ADD
mux
*4
ADD
4
decoder
A-data
daddrbus
clk
clk
clk MEM/WB
ID/EX
B-data
sign ext
mux
clk
clk
You will need to change the decode logic so that the following instructions are implemented. These op codes include branch and set instructions.
ECEN 6253 Spring 2007 Design Project B1
January 21, 2007
databus
mux
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PC
=
EX/MEM
instrbus
reg file
iaddrbus
IF/ID
ALU
TABLE 1. Subset of instruction codes to be implemented. Code 000011 000010 000001 001111 001100 011110 011111 010100 010101 000000 000000 000000 000000 000000 000000 000000 000011 000010 000001 000111 000100 001010 001011 Func Name ADDI SUBI XORI ANDI ORI LW SW BEQ BNE ADD SUB XOR AND OR SLT SLE Format I I I I I I I I I R R R R R R R
The instruction formats should be as in Patterson and Hennessy, fig. 3.19, p. 154, except that only the I and R formats are implemented and the logic operations are slightly different. All other op-codes should be treated as NOPs. As before, the instruction cache and data cache will not be modeled. Instead the instruction and data busses will be made available as external terminals and the test bench will simulate the behavior of the memory. Your CPU design should have the terminals shown below. iaddrbus[31:0] instrbus[31:0] reset clk CPU daddrbus[31:0] databus[31:0]
Note that the databus must be bi-directional.
ECEN 6253 Spring 2007 Design Project B1
January 21, 2007
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Design Strategy. 1. The instruction address must be produced by your CPU. This requires your CPU to put the next instruction address onto the iaddrbus at the beginning of each clock cycle. To keep the hardware simple, a one cycle delayed branch will be used (no branch stalls required). That is, the instruction after the branch is always fetched. The compiler is assumed to insert another useful instruction after the branch or a NOP otherwise. This has been used in real MIPs processors. 2. The comparisons for the set instructions can be done with an ALU subtract operation. Then you can use the status outputs from the ALU. If Z is the output of the zero detector and C is the carry out of the ALU, then set (to 1) bit 0 (the least significant bit) in the destination register when the following conditions are true.
instruction SLT SGT SLE SGE set bit 0 not C and not Z C and not Z not C or Z C or Z
Otherwise, put all zeroes in the destination register. Note, these comparisons are for unsigned numbers. Different logic would be needed to compare signed numbers. 3. The equality detector on the register file outputs controls the PC input MUX. The delay of the register file, the equality detector and the MUX must be less than half a clock period to insure that the PC gets the correct value. You must turn in your Verilog structural files, a list of Verilog structural files named cpu6.ver and your high level file must be named cpu6.v. Other files can be named as you wish. When using the automatic grader, be sure to use the correct class and assignment name (spelling and case is important!). class: ecen6253 assignment: projb1a
ECEN 6253 Spring 2007 Design Project B1
January 21, 2007
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Part B Due Fri., Feb. 16, 1700 hrs. Add branch prediction to the scalar processor of project 1. Instead of delayed branching, the processor should fetch from the predicted branch address without delay. It should run at a 100 MHz clock rate (a full clock cycle is 10 nsec. and a half cycle is 5 nsec.). The combined branch prediction and branch target buffer should be designed with latches as was done last semester for the register file. It must have the following inputs and outputs.
addr[31:2]
nval rd wr
btb
hit bta[31:0] s[1:0]
The addr input is from the PC. Since instructions are assumed to be word aligned, addr[1:0] are assumed 0. Just as the for register file, separate read (rd) and write (wr) controls are provided to make timing easier. The nval input invalidates all the btb entries (sets all V bits to 0). A hit output indicates that a branch target address has been previously stored in the btb. The bta input/output is the branch target address and the s input/output is the state of the 2-bit predictor. The btb should be organized as a small 16-line cache (real BTB/BPBs would be much larger). The internal organization of the cache might look like the following. nval 4 to 16 binary decoder =? 1
addr[5:2]
V tag[31:6] bta[31:0] s[1:0]
addr[31:6] hit
s[1:0] bta[31:0] Each cache line should have a 26-bit tag, 32-bit predicted address and 2-bits for the state of the branch predictor. Use a binary decoder on addr[5:2] to select one of the 16 cache lines. Compare (equality detector) addr[31:6] with the 26-bit tag then gate with the valid bit to generate the hit output. The nval input should cause all (not just the selected line) the V bits to be set to 0 (invalid). Whenever a write into bta and s occurs, a 1 should also be written in the selected V bit.
ECEN 6253 Spring 2007 Design Project B1 January 21, 2007 page 4 of 6
Note that the hit output is ignored during a write operation. The new bta and s bits simply replace whatever was in the btb. Even though the btb is not clocked, it must be fast enough to complete a read operation or a write operation in 1/2 clock cycle (5 nsec). The timing requirements of the latches makes the register file model more consistent with a realistic BTB/BPB based on a static RAM design. The operation of the bi-directional bta and s are controlled by the rd and wr control lines as follows.
rd 0 0 1 1 wr 0 1 0 1 function bta and s not used write bta and s into location selected by addr read bta and s selected by addr not allowed
You must submit a list of all Verilog files in a file named btb.ver and your high level Verilog file must be named btb.v. Other Verilog files can be named as you wish. When using the autograder, be sure to use the correct class and assignment name (spelling and case is important!). class: ecen6253 assignment: projb1b Part C Due Fri., Mar. 2, 1700 hrs. The combined branch prediction and branch target buffer from part a should be added to the linear pipelined processor from project 1. The btb should be placed in parallel with the PC incrementer (the adder that adds 4 to the PC) in the IF stage as discussed in the class notes. The btb only stores the branch predictor state. The predictor state should be generated with the 2-bit saturating counter state machine. A state diagram is shown below. T NT 00/0 NT 01/0 NT T 10/1 NT T 11/1 T
You will need to...