Overview An of Atomic Layer Deposition and its role in Transistor Gate Dielectrics
ENMA465 Dr. Gary Rubloff May 14, 2003
Nicole Harrison Bryan Sadowski Anne Samuel Kunal Thaker
Table of Contents
Introduction ALD Theory and Chemistry Applications of Atomic Layer Deposition ALD Equipment Comparison of ALD to other deposition methods for the formation of gate dielectrics Current and Future Developments Conclusion References 19 22 26 27 2 2 7 14
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Introduction ALD (Atomic layer deposition), previously known by the name ALE (Atomic Layer Epitaxy), was originated by T. Suntola in Finland. It was originally developed for the fabrication of polycrystalline luminescent ZnS:Mn and amorphous Al2O3 insulator films for electroluminescent flat panel displays. Due to its complex surface chemistry, no real break-through was achieved in this area since 1985. But decreasing device dimensions and increasing aspect ratios in the IC circuits increased interest towards this technique since the mid 1990's. ALD has a slow deposition rate (this is the draw back of this technique), however, this is becoming less important as the thickness of the films are reducing to the order of a few nanometers [1]. Since this is a layer-by-layer deposition it produces films of uniform thickness and excellent conformality. In this report, we are discussing ALD theory and its' chemistry, ALD equipment, Applications of ALD in gate dielectrics, Comparison of ALD to other processes for the formation of gate dielectrics and finally, current and future developments of ALD.
ALD Theory and Chemistry What is Atomic Layer Deposition (ALD): ALD previously known by the name ALE (Atomic layer Epitaxy), was originated by T. Suntola in Finland. This is the deposition method by which precursor gases and vapors are alternately pulsed on to the surface of a substrate. When precursor gases are introduced onto the substrate surface, chemi-sorption or surface reactions take place at the surface. The ALD reactor is purged with an inert gas between the precursor pulses [1]. The surface reactions in ALD are all self-limiting. In fact, self-limiting characteristics of the process steps are the foundation of ALD [2]. Deposition process steps are repeated to grow films. The self- limiting process in ALD promotes the growth of conformal films with accurate thickness on large areas. The characteristics features of ALD, with their implications on the film growth and practical advantages are given in Table 1. There are two self-limiting process in ALD that are discussed below.
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Table 1. Characteristic features of ALD (ALE), implications on film growth and practical advantages [3].
Self-Limiting Mechanisms in ALD: There are two fundamental self-limiting mechanisms in ALD. They are CS-ALD: Chemi-sorption saturation process followed by exchange reaction and RS-ALD: Sequential surface chemical reactions. In the CS-ALD process, the substrate surface is exposed to the first molecular precursor, which is retained on the surface by chemi-sorption. This layer is then exposed to the second precursor, which reacts on the surface of the first precursor. Exchange reactions take place between two precursors and by-products are formed. Exchange reactions continue until the first precursor reacts with the second precursor, so this is a self-limiting step. A layer of desired film is formed and this sequence is repeated to grow films. The chemi-sorption saturation process sequence is given in Figure 1 below.
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Figure 1. Showing the chemi-sorption saturation process sequence [2].
In the figure above, ML2 represents the first molecular precursor, AN2 represents the second molecular precursor and LN is the by-product formed due to the exchange reaction between ML2 and AN2. The final reaction looks like this: ML2 + AN2 MA (film) + 2 LN (1) In contrast to CS-ALD process, the RS-ALD process is promoted by the chemistry between reactive surface and reactive molecular precursor. The film deposition in this process is as a result of the chemical reactions between reactive molecular precursors and the substrate. The RS-ALD process sequence is given in Figure 2.
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Figure 2. Showing sequential surface chemical reaction [2].
The figure above shows that at the beginning, the substrate surface is activated by AN groups. This surface is then exposed to the first metal precursor ML2 where M can be Al, W, Ta, Si etc. and L can be CH3, Cl, F, C4H11 etc. ML2 molecules react with the surface AN reactive species to form AML groups. The reaction sequence is given equation 2, AN + ML2 AML +NL (2) where NL is the by-product and this reaction self saturates when all AN groups are converted to AML groups. Followed by this reaction, the first precursor is removed by inert gas purging prior to the introduction of the second precursor. Once the first precursor is removed, the second precursor, AN2, is introduced to the ML surface. The second precursor is usually non-metallic where A is O, N, S and N can be H2O, NH3 or H2S. AN2 reacts with ML to form: AML + AN2 MAN + NL (3) This reaction self saturates until all ML groups are converted MAN, which cannot further react with the AN2 precursor. The substrate surface looks like the initial surface, with AN groups
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present on it. The sequence is repeated to grow films and this reaction sequence that restores the surface to the initial surface is known as the ALD deposition cycle [2]. In RS-ALD process, deposition reactions are half-reactions (equations 2 and 3). During each half-reaction, the surface functionality changes from one surface species to another [3]. And the final half-reaction leads to the restoration of the initial surface. Restoration of initial surface is the factor that differentiates RS-ALD from CS-ALD. Requirements for ALD: The factors that are taken in account during ALD reaction are the volatility and stability of the precursor materials, their pulsing into the reactor and their interaction with the substrate surface and each other [4]. Precursor Requirements: Precursor chemistry plays a key role in ALD [1]. Precursors must be volatile and thermally stable in order to ensure its' efficient transportation, so that reactions will not be precursor flux controlled. The vapor pressures of the precursors must be high enough to cause complete fill of the substrate area so that monolayer chemi-sorption can take place in a reasonable length of time. The approximate vapor pressure of precursors must be 0.1 torr. Precursors are preferably liquids and gases, but solids can also be used, as they present no sintering related problems. Some examples of ALD precursors include elements like Zn, Cd, S, Se, metal halides like AlCl3, TiCl4,TaCl5, Alkyls, Diketonates etc. [5]. Precursors must chemi-sorb on the surface or react rapidly with the surface groups and react aggressively with other. The aggressive reactions help to attain fast saturation with short cycle times, complete reactions with high film purity and avoids gas phase reactions. Precursors should not undergo self-decomposition, as self-decomposition would destroy self-limiting film growth, which in turn will affect thickness non-uniformity, inaccuracy and film contamination. Also, precursors should not etch and/or dissolute into the film or substrate, as this would prevent the self-limiting film growth. An example of precursor etching reaction would be the following [5]: NbCl5 (g) + NbO5 (g) NboCl3 (g) (4) The ALD reaction chamber is purged with an inert gas between precursor pulses in order to prevent gas-phase interactions that take place in the reactor. Besides separating dosing pulses, inert gas purging has a cleaning effect. It transports excess of reactants from the chamber and desorbed materials from the reactor walls. The substrate temperature, reactor-wall temperature and purging time should be fixed so that the monolayer remains on the surface and does not
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desorb during the purging period and maximum cleaning effect can be attained [4]. The thin film materials deposited by ALD are given in Table 2. The table shows films that are deposited in epitaxial, polycrystalline or amorphous form. As seen in Table 2, the groups of materials deposited by ALD are extensive: covering oxides, nitrides and semiconductors.
Table 2. Thin film materials deposited by ALD including all films deposited in epitaxial, polycrystalline or amorphous form [6].
Applications of Atomic Layer Deposition The great potential of Atomic Layer Deposition (ALD) leads to a wide variety of applications. The high degree of control, conformality, and uniformity offered by ALD makes it the most suited processing method for various applications within and outside the semiconductor arena. The list below highlights the major potential applications for this technology: 1) Transistor Gate Dielectrics 2) MEMS 3) Opto-electronics 4) Diffusion Barriers 5) Flat- Panel displays a) Organic Light Emitting Diodes (OLED)
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6) Interconnect Barriers 7) Interconnect seed layer 8) DRAM and MRAM dielectrics 9) Embedded capacitors 10) All thin films (<90 nm) 11) Electromagnetic recording heads Though the list above is not comprehensive, it outlines the major applications where ALD could find financial viability in the coming years. The focus of the paper will be on the use of ALD in the fabrication of transistor gate dielectrics. The current material used in transistor gate dielectrics is SiO2 (oxide), however limitations on this material with growing trends toward Ultra Large Scale Integration (ULSI), for higher switching speed and faster logic operations, requires a new method to deposit these new materials. Figure 3 below shows a technology roadmap predicted by Intel Corp, a major manufacturer of advanced and commercial microprocessors.
Figure 3. A technology roadmap for the required thickness of SiO2 gate dielectric [7]
The roadmap shows the need to switch from oxide to another gate dielectric sometime between 2002 and 2005 in order to prevent gate dielectrics from becoming the limitation on further transistor design enhancement [7]. There are many physical limitations on the transistors used in the majority of todays computing (Complementary Metal-Oxide Semiconductor (CMOS) field effect transistors). See Figure 4 for a schematic of a CMOS transistor, and note the arrows indicating where the gate dielectric is located. 8
Figure 4. A vertical profile of a typical CMOS transistor [8]
The CMOS transistor works by combining both an N-Type MOSFET and a P-type MOSFET, and controlling the current flow through applied voltages on the gates, which in turn form and remove charged regions in the silicon which serve to facilitate or hinder charge transfer between the respective doped regions. Thus positive and negative bias voltages on the gates can control the functionality of the switch (on or off). For a more detailed explanation of transistor theory the reader is referred to Silicon VLSI Technology: Fundamentals, Practice, and Modeling by Plummer, et al. Table 3 below shows the physical dimension limitations on key aspects of the CMOS technology and the reasons that these dimensions pose a physical limitation to the functionality of the transistor.
Table 3. A table of the physical limitations on the continued miniaturization of transistors [7]
The first on the list, oxide thickness, highlights the necessity to find alternative materials, and compatible processes, to satisfy gate dielectric requirements. Currently, existing oxide gate dielectrics used have a practical limitation on the order of 2.3 nm [7]. This limitation is imposed because of the excessive leakage currents that are allowed to pass through oxide layers <2.3 nm
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[7]. The principal of electron tunneling contributes to this leakage current. Because the dimensions discussed are on the order of tens of angstroms, the probability that an electron could pass from one side of the dielectric to the other is increased, and this probability leads to a small leakage current passing through the gate dielectric, thus not allowing it to store charge and function as a controller of the CMOS depletion region. The oxide layer must continue to be scaled down with increasing miniaturization of the transistor because the ratio of the transistor channel length must be linearly scaled with the gate oxide thickness, to ensure the gate maintains the same amount of control over the channel [7]. Figure 5 below shows a plot of the channel length to gate oxide thickness versus time for the evolution of transistors [7].
Figure 5. A figure of the channel length to gate oxide thickness ratio versus the channel length [7]
This number is kept at a constant of approximately 45, thus ensuring consistent gate control over the channel properties [7]. Given this, new materials (with very high dielectric constants), such as those shown in Table 4 and others including HfO2 are being examined for their suitability in this application.
Table 4. A table of potential alternative materials to SiO2 for transistor gate dielectrics [7]
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The dielectric constant is a ratio of the electric permittivity of a given material () to the electric permittivity of free space (0), as shown in Equation 5 below [9].
(5) These high-K dielectric materials can allow the gate dielectric material to made thicker (thus reducing leakage current); yet at the same time maintain their relative capacitance, due the increased thickness coupled with a higher dielectric constant (See equation 6). Capacitance= (0A)/d= K02A/d (6) This will allow for consistent gate control of the channel, and at the same time significantly reduce the leakage problems caused by the scaling of the gate dielectric thickness with the channel length. However, many of the materials have many downsides, and they pose new problems in terms of processing. Given the need to shift to these new materials, there has been much ongoing research into the potential processes that can be used for this sensitive transistor component. Figure 6, below summarizes many of the materials and corresponding processes that are being considered for the gate dielectrics.
Figure 6. A summary of the current research on gate dielectrics [10]
Excellent thickness control, uniformity, conformality, low thermal budget, and the ability to layer multi-compositional films (to combine mechanical and electrical properties) are some of the many reasons that ALD is being considered. A comparison of ALD, with respect to transistor gate dielectrics, to other processes will be discussed in detail in the following sections. In
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addition to transistor gate dielectrics, ALD has a role to play in many other semi-conductor and non-semiconductor applications. Micro-Electro Mechanical Systems (MEMS), for example, are a growing field that integrates the mechanical world with the digital world of modern electronics. This technology has applications in sensors, transducers, high energy density power sources, inkjet printers, etc. Moreover, MEMS is a key technology to help bring to reality the system on a chip methodology, where a single Integrated Circuit (IC) would allow a complete interface between the mechanical or biological world and the logic circuits to interpret or control the chips operation. ALD, with its unique deposition properties, and advanced controllability has great potential in this field (for multi-composition thin films, etc.). Optical multiplexing and laser diodes are also emerging technologies that are being proposed to increase the bandwidth of fiber optics, and these techniques require high degrees of compositional control and uniformity that ALD could provide [11]. Diffusion barriers, such as TaN and Ti are often used to prevent the diffusion (at high temperatures) of materials such as copper into neighboring layers, and ALD, with its ability to deposit mono-layers at a time would serve as a very effective and efficient mode by which to prevent diffusion, and at the same time, not provide a substantive material buildup. ALD also has great potential in the fields of flat-panel displays and organic light emitting diodes (OLEDs) [11]. These applications, which are growing to dominate the display sector, require high levels of compositional control, so as to ensure the resulting thin-films have the appropriate electrical and optical properties. ALD also has a large role to play in interconnect barriers and interconnect seed layers. ALD can serve to deposit thin layers of dielectric material to ensure there is no electromigration or crosstalk between the respective interconnects layers. Moreover, ALD has great potential to be used as an interconnect seed layer deposition technique [12]. With ALD, an initial layer of the conducting material can be applied, and the rest of the interconnect can then be electroplated. This allows a highly controllable seed layer to form (with a low thermal budget) thus ensuring a proper platform from which electroplating can take place. ALD also has a huge market in the arena of imbedded (in the Si substrate) capacitors. The use of ALD, which will allow for the deposition of very thin high k-dielectrics (similar to those in transistor gate dielectrics), can take the processing precision and electrical properties of these capacitors to very high levels [12].
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ALD also has potential in the field of electro-magnetic read-write heads. These readwrite heads are used to read and write information on hard disks and other data storage mediums. These advanced sensor element gap applications for ALD can be seen by the need for extremely dense, uniform and pin-hole free thin films [11]. Finally, ALD has shown the most promise in the field of Dynamic Random Access Memory (DRAM) and Magnetoresistive Random Access Memory (MRAM). MRAM is a non-volatile solid-state memory device that uses magnetism to read and write data [11]. Both DRAM (very commonly used) and MRAM (under development) require high density, highly accessible capacitors from which to read, and write information. ALD provides a very sensitive processing from which these technologies can continue to grow. Random Access memory is currently one of the most active areas of microprocessing research due the physical limitations encountered by current materials and processing. The DRAM market alone is predicted to go from a $95 million industry in 2001 to a $246.9 million industry in 2006 [13]. ALD is viewed as one of the chief processing solutions to the physical limitations that the technology currently faces.
ALD Equipment
There are many manufacturers of ALD process equipment: Genus, ASML, Genitech, Moo-Han, etc. The companies tend to have only one ALD system, and they modularize the systems to allow it to be customized to various sectors of the electronics industry (DRAM, transistor gate dielectric, etc). From semi-conductor to non-semiconductor applications, these manufactures customize their systems to meet the needs of the growing number of applications that are migrating towards ALD. There are four main classes of ALD reactors: 1. Open Systems, 2. Closed Systems, 3. Semi-open systems, and 4. Semi-closed systems. These four systems are 13
characterized based on the relative geometry of the reactor chamber in relation to the wafer. Figure 7, below shows a schematic of what these four main classifications of ALD reactors look like at the microscopic level.
Figure 7. A summary of the different type of ALD reactors [14]
In an open system, the walls of the reaction chamber are far enough removed from the surface of the wall that there is no transport interaction between the reactant gases and reactor walls. In the case of a closed system, the walls of the reactor chamber are such that the transport of the reactant gases is heavily affected by the geometry of the reactor chamber. In a semi-closed system, two or more wafers are positioned parallel to each other and the reactant gas is allowed to flow between the two wafer surfaces, therefore allowing deposition on both wafer surfaces (this is a common technique used in many ALD batch reactors). Finally, there is a semi-open system in which a non-reactive species is used to keep the reactant species close to the surface of the wafer. This acts similar to a semi-closed system, except one side is a wafer and the other side is a boundary limited by a non-reactive gas flow. Given these four methods, closed and semiclosed systems seem to dominate, because reactor volume and reactant transport is an important part of the ALD process. The closed and semi-closed systems allow the reactant species to be directed toward the wafer surface, and at the same time reduce the reactor volume. Therefore, these closed and semi-closed systems tend to dominate. Many of the ALD systems currently on the market, such as the LYNX2 by the Genus Corporation are actually Chemical Vapor Deposition (CVD) systems that have been modified to allow for minimal ALD processing. The conversion from CVD to ALD consists of adding a module that facilitates fast gas switching. Since the control of ALD reactions is far simpler then that of CVD reaction, due to the self-limiting chemistry, the main difference in the equipment is the need for faster gas switching because in ALD, the gas cycle time is increased drastically, because the structure is built mono-layers at a time, as opposed to nm or m at a time as in CVD. However, there are many commercially available ALD systems, such as the ELFRA 7000 Series by the Moo-Han Corporation and the PULSAR by the ASM Corporation (Figure 8).
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FEATURE
- ALD Process - Mini-Batch Reactor ( Four 200mm wafers ) - Bridge Tool ( 200mm to 300mm ) - Minimized Reaction Volume - Disk Rotation - In-situ Cleaning - Low Process Temperature - Simple Design - Compatible with Factory Automation
Figure 8. Commercially available ALD systems: PULSAR (on the left) [15] and the ELFRA 7000 Series (on the right) [16]
Figure 9 shows a schematic of the chemical process that takes place in the ELFRA 7000 Series as well as the corresponding modes of operation that the equipment takes to allow for the successful completion of that chemical process. Basic ALD Mechanism
ALD Mode
Figure 9. A summary of the mechanisms and modes used in the ELFRA 7000 series ALD reactor [16]
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The main features of ALD reactors are as those outlined in Figure 9. The compatibility of the reactor to factory automation, the number of wafers that can be processed, the wafer output rate, and the minimization of reactor volume are the key features that determine how useful any ALD reactor is in a commercial setting. Moreover, the conformality, uniformity and consistency of the machine are also of chief importance. Figure 10, below, shows the data output for the ELFRA 7000 series.
Figure 10. A plot of the thickness vs. wafer number for the ELFRA 7000 Series ALD reactor [16]
The data suggests that the equipment was able to output a very uniform thickness film both on a given wafer, between wafers in the same batch and between different batches. This to ability control the thickness to a very high degree is what is required of modern ALD machinery. Given the ALD equipment already on the market, the features required of them, and the results needed for their widespread use, it is important to discuss the drawbacks of current ALD machinery. The main drawback of ALD machinery is wafer output. Currently, most ALD equipment offers a wafer output on the order of 16-30 wafers per hour. This wafer output must be increased significantly if ALD is to come to dominate many sectors of microprocessing, such as transistor gate dielectrics. Above we have discussed the commercially available ALD reactors, some of their features, their output results, and their drawbacks. However, as in much of microprocessing, a lot of research is ongoing to improve the ALD process and equipment. Figure 11 below shows a reactor constructed by Genitech Corporation, a major ALD equipment developer.
Figure 11. A schematic of the ALD/ PEALD reactor proposed by Genitech [17]
The reactor is a plasma enhanced ALD and standard ALD reactor (semi-closed in nature). The PEALD reactor developed by Genitech uses the following mechanism chemistry for the
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deposition of HfO2, one of the potential transistor gate dielectric materials: Hf[N(CH3)2]4 as the reactant species with an O2 plasma and H2O [17]. Ar is used as the carrier and purge gas and the plasma power is set at 100-450 W, with a temperature in the range of 200-350C [17]. The uses of this PEALD method was shown to increase the choice of reactants, increase film quality, and perhaps most importantly improve the wafer output rate. This is evidenced by Figure 12, which shows the linear increase in thickness with cycles and the higher rate of PEALD deposition verses ALD deposition [17].
Figure 12. A plot of the thickness vs. cycles for the ALD/ PEALD reactor proposed by Genitech [17]
A similar PEALD reactor with almost identical chemistry was developed by Thomas D. Abatemarco and Gregory Parsons from the Department of Chemical Engineering at NC State University in Raleigh North Carolina. Therefore, this PEALD chemistry and its corresponding reactor is an example of many techniques that could be employed to improve film quality and deposition rate. The potential of ALD has not yet been realized in the commercial sector. A major reason for this is the fact that the equipment has not yet reached a level where ALD would be an efficient or viable alternative to CVD, however ongoing research into new chemistries and equipment designs is ongoing. This research, such as that undertaken at Genitech and NC State University, has and will continue to provide substantive equipment design alternatives that will allow ALD to enter many component fabrication sequences. These equipment enhancements have the potential to make the deposition of new high-K dielectrics, such as HfO2, more precise, and thus allow the continued development (miniaturization) of transistor technology along the roadmap shown in Figure 3.
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Comparison of ALD to other deposition methods for the formation of gate dielectrics
For the past 50 years, silicon dioxide has been the major element in gate dielectrics. Silicon dioxide forms a high-quality interface with silicon and has superior electrical isolation properties that make it suitable for use in electrical components. They produce thermodynamically and electrically stable metal-oxide-semiconductor field effect transistors (MOSFETs) for use in logic and memory devices. As technology evolves, the focus has been on scaling down devices. Currently, fabrication techniques are needed to produce gate dielectric films that are 2 to 2.5nm thick. However, problems arise in silicon dioxide dielectrics at this level. Gate dielectrics containing SiO2 are plagued by several issues, one of which being high gate currents or leakage currents (discussed in more detail in the previous sections). These high leakage currents are the result of electron tunneling through the silicon dioxide film. The current density exponentially increases for transistors with gate dielectric thickness of 3.5nm and smaller. When the SiO2 oxide thickness get to around 1 and 1.2nm, there is no further gain in transistor drive current therefore limiting its use in future electronic devices. Another problem that silicon dioxide gate dielectrics face is device reliability. Dielectric degradation is caused by 1-3eV electrons crossing the transistor channel from source to drain producing physical and chemical phenomena that accelerate the breakdown of the gate oxide [18]. A serious concern of gate dielectrics is also dopant (Boron) diffusion through the oxide. A thinner oxide layer renders a poorer diffusion barrier and can lead to a different oxide composition and a higher concentration of dopant in the channel region. Since traditional insulating materials like SiO2 cannot meet current challenges faced by ultra-large scale integration (ULSI) devices, researchers have to look to other materials. Some requirements for alternative gate dielectric materials are those possessing high dielectric constants, thermodynamic stability, low interface trap densities, good interface quality with silicon, wide band gaps, process compatibility, and reliability. By 2004 as technology enters the 90nm node, gate dielectric leakage currents will need to be down to 0.23n/m2 at 100oC in
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order to survive decreasing oxide thickness [19]. The alternative materials also have to be capable of being deposited in the amorphous state because polycrystalline or single-crystal films will allow leakage along grain boundaries. Materials being studied to replace silicon dioxide for MOSFETs or other semiconductor oxide devices are zirconium, hafnium, and rare-earth oxides and silicates. Several processes have been employed over the years to deposit films on silicon substrates. The older techniques fall under physical vapor deposition (PVD) methods including sputtering, evaporation, and epitaxy. Historically, PVD processes were used in semiconductor manufacturing for planar or low aspect ratio films, but voids began to form when applying PVD techniques to sub-1000nm features, especially trenches and vias with aspect ratios above 0.5 [20]. Limitations of physical vapor deposition are its directional or isotropic nature of the depositing films as well as the high sticking coefficient of most metals. Since PVD atoms tend to stick where they hit, extra work is needed to produce a conformal and stoichiometric film. A benefit to PVD is that it can be used to produce films containing zirconium, hafnium, and rareearth oxides [19]. Chemical vapor deposition (CVD) is also a viable method to produce thin gate dielectric films. Several types of CVD processes can be used to deposit the thin films on silicon substrates. Metal organic CVD, low-pressure CVD, and plasma-enhanced CVD have all been known to successfully deposit dielectric films onto silicon wafers at temperatures ranging from 300 to 450oC. As with all CVD processes, precursors are simultaneously introduced into the deposition chambers as gases. Reactions typically occur in the gas phase and continuously deposit a thin film onto the substrate surface. In order for CVD to compete with emerging technologies for the formation of gate dielectric films, faster reactions are necessary for ultra-thin film nucleation and purity, but can result in conformality issues [20]. At lower temperatures, deposition rates can be surface-limited. At higher temperatures where deposition rates are usually higher, deposition rates are mass-flow limited [21]. As technology requires smaller devices, newer processes have to be developed to fabricate these devices. A promising technique currently being researched for its use in the formation of gate dielectrics is atomic layer deposition or ALD. Atomic layer deposition also referred to as ALCVD provides several advantages over conventional CVD and PVD techniques. ALD is a self-limiting growth process where the thickness of the oxide film is only dependent on
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the number of deposition cycles, so it has precise thickness control. Although ALD can be considered as using much of the same chemistries as CVD, CVD is done in a dynamic flow situation where ALD uses discrete steps to control the reactions [20]. ALD's deposition rates are very temperature dependent and are not limited by surface reactions and mass-flow like CVD. There is no need for reactant flux homogeneity because it has a large area capability, excellent conformality, and good reproducibility. No gas phase reactions take place in an ALD chamber because there is separate dosing of the precursors. All reactions take place at the wafer surface decreasing the amount of impurities in the films. Another benefit of surface reactions is that 100% conformality or step coverage can be achieved on films with aspect ratios greater than 25. In PVD and CVD, compositions can vary along sidewalls of high aspect ratio structures due to directionality and higher sticking coefficients of the materials used in these processes [21]. Atomic layer deposition favors precursors that are highly reactive to each other and therefore different types of precursors can be used in the process. A wide variety of precursors such as metal halides, metal alkyls, metal alkoxides, metal alkylanides, metal nitrates, and metal chlorides can all be used depending on the type of film being formed. For gate applications, it is necessary for materials to be stable on the single-crystal silicon substrates and polysilicon gate electrodes. By using atomic layer deposition, thermal as well as chemical stability can be achieved. A quality that makes atomic layer deposition so attractive is its ability to be processed at low temperatures. The typical temperature range for atomic layer deposition is between 200 and 400oC. When the deposition temperature is too high, density of the chemically reactive sites is reduced and chemical bonding can not be sustained thereby reducing the deposition rate. Fang et al. (2003) found a growth rate decrease of around four orders of magnitude compared to SiO2 caused by increasing the temperature from 225 to 600oC. Since film formation and chemisorption is thermally-activated at lower temperatures, the deposition rate is increased [21]. For example, hafnium oxide was successfully deposited to several nanometers at temperatures as low as 180oC compared to low-pressure CVD, metal organic CVD, and photo-induced CVD where the deposition temperatures ranged from 300 to 450oC [22,23,24]. As for polycrystalline rare-earth oxide films, ALD can deposit the materials between 250 and 450oC. Whereas electron beam evaporation requires temperatures as high as 550oC [25].
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In the past atomic layer deposition was frowned upon because of its slower deposition rates compared to CVD and PVD processes, but now since film thickness is decreasing, the time it takes is no longer an issue. Only a couple of seconds is required for the chemisorption of a monolayer. A rate of 10 to 50/minute in manufacturing settings can be achieved for thin films as small as 40 if a range of 0.5 to 2 per pulse-set are used [20]. Currently, ALD is too slow for applications because sizes of films range between 80 and 150.
Current and Future Developments
The current trend for gate dielectrics is focused on high-k and high barrier height materials. This path of development is not, however, an attempt to increase performance, it is an effort to lower power usage in the systems the gate dielectrics are being used. With this trend in mind, the three most commonly used gate dielectrics are HfO2, Al2O3, and ZrO2. The main reason these high-k and high barrier height materials are being used is to slow current leakage, which is a major reason there is a great deal of power wasted from gate dielectrics. High-k materials reduce current leakage by trapping electrons between the barrier gate and the SiO2 layer, which reduces energy loss from electrons burrowing through the thin layer of SiO2. A list of ks for several materials can be seen in Table 5.
Table 5. A chart of values for several commonly used gate dielectric materials. The three most used high-k materials are aluminum oxide, hafnium oxide, and zirconium oxide.
material silicon oxide silicon nitride
formula SiO2 Si3N4
kox 3.9 7
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Oxynitrides aluminum oxide tantalum pentoxide hafnium oxide zirconium oxide barium strontium titanate (BST)
SixNyOz 4 to 7 Al2O3 Ta2O5 HfO2 ZrO2 9 25 30 to 40 25
BaSrTiO3 300
One thing to notice from the graph is that the k-value of aluminum oxide is lower than that of hafnium oxide and zirconium oxide. The reason that aluminum oxide is still used is because of its high barrier height. The barrier height corresponds to the amount of energy required for an electron to pass from the gate dielectric to the silicon dioxide layer. Therefore, a material with a high barrier height will require a larger amount of energy before the energy is lost to discharge. Another reason that these three materials are used quite often is that they exhibit excellent properties when deposited onto the silicon dioxide with atomic layer deposition. All three materials exhibit excellent thickness control, which is very important in making uniform sample. Another property seen in all three materials is high conformality, which is also important when making samples regular. The final property exhibited by all three materials is excellent step coverage, sometimes almost 100 percent, which is very important when dealing with the high aspect ratio steps present in some transistors. While these properties make all of these materials very useful for ALD and gate dielectrics, they are by no means perfect. They are a great leap forward in gate dielectrics, b...