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Course: EE 7700, Fall 2008
School: LSU
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the Inside 4 Processor Pentium Micro-architecture Next Generation IA-32 Micro-architecture Fall 2000 Doug Carmean Principal Architect Intel Architecture Group August 24, 2000 Intel Copyright 2000 Intel Corporation. Labs Agenda l IA-32 Fall 2000 Processor Roadmap l Design Goals l Frequency l Instructions Per Cycle l Summary Intel Copyright 2000 Intel Corporation. PDX Intel Pentium 4 Processor Intel...

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the Inside 4 Processor Pentium Micro-architecture Next Generation IA-32 Micro-architecture Fall 2000 Doug Carmean Principal Architect Intel Architecture Group August 24, 2000 Intel Copyright 2000 Intel Corporation. Labs Agenda l IA-32 Fall 2000 Processor Roadmap l Design Goals l Frequency l Instructions Per Cycle l Summary Intel Copyright 2000 Intel Corporation. PDX Intel Pentium 4 Processor Intel NetBurst MicroMicro-Architecture Fall 2000 Performance Today P6 Micro-Architecture Micro- P5 Micro-Architecture Micro- 486 Micro-architecture Micro- Time Intel Copyright 2000 Intel Corporation. PDX Intel Pentium 4 Processor Design Goals l Deliver Fall 2000 world class performance across both existing and emerging applications l Deliver performance headroom and scalability for the future Micro-architecture that will Drive Performance Micro-architecture that will Drive Performance Leadership for the Next Several Years Leadership for the Next Several Years Intel Copyright 2000 Intel Corporation. PDX Intel NetBurst Micro-architecture 400 MHz System Bus Advanced Dynamic Execution Rapid Execution Engine Fall 2000 Advanced Transfer Cache Hyper Pipelined Technology Streaming SIMD Extensions 2 Execution Trace Cache Copyright 2000 Intel Corporation. Enhanced Floating Point / Multi-Media Intel PDX Pentium 4 Processor Block Diagram 3.2 GB/s System Interface L2 Cache and Control Integer RF L1 D-Cache and D -TLB BTB Rename/Alloc Trace Cache BTB & I-TLB uop Queues Store AGU Load AGU ALU ALU ALU ALU 3 3 Schedulers Decoder FP RF FP move FP store FMul FAdd MMX SSE uCode ROM Pentium 4 Processor Block Diagram 3.2 GB/s System Interface L2 Cache and Control Integer RF L1 D-Cache and D -TLB BTB Rename/Alloc Trace Cache BTB & I-TLB uop Queues Store AGU Load AGU ALU ALU ALU ALU 3 3 Schedulers Decoder FP RF FP move FP store FMul FAdd MMX SSE uCode ROM CPU Architecture 101 Fall 2000 Delivered Performance = Delivered Performance = Frequency ** Instructions Per Cycle Frequency Instructions Per Cycle Frequency Frequency Intel Copyright 2000 Intel Corporation. PDX Frequency l What Fall 2000 limits frequency? Process technology Microarchitecture l On a given process technology Fewer gates per pipeline stage will deliver higher frequency Frequency is driven by Micro -architecture Frequency is driven by Micro-architecture Intel Copyright 2000 Intel Corporation. PDX NetburstTM Micro-architecture Pipeline vs P6 Basic P6 Pipeline 1 Fetch 2 Fetch 3 Decode 4 Decode 5 6 7 8 Decode Rename ROB Rd Rdy/Sch Dispatch Rdy/Sch Fall 2000 Intro at 733MHz 9 .18 10 Exec Basic Pentium 4 Processor Pipeline 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Intro at 16 17 18 19 20 1.4GHz RF Ex Flgs Br Ck Drive .18 Hyper pipelined Technology enables industry Hyper pipelined Technology enables industry leading performance and clock rate leading performance and clock rate Intel Copyright 2000 Intel Corporation. PDX Hyper Pipelined Technology 20 Today Netburst MicroNetburst MicroArchitecture Fall 2000 1.4GHz Frequency 1.13GHz 10 P6 Micro-Architecture Micro- 233MHz 166MHz 60MHz 5 P5 Micro-Architecture Micro- Introduction Copyright 2000 Intel Corporation. Time Intel PDX Hyper pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive TC Nxt IP: Trace cache next instruction pointer Pointer from the BTB, indicating location of next instruction. System Interface L2 Cache and Control Integer RF BTB Rename/Alloc Trace Cache AGU AGU ALU ALU ALU ALU 3 3 FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive TC Fetch: Trace cache fetch Read the decoded instructions (uOPs) out of the Execution Trace Cache System Interface L2 Cache and Control Integer RF BTB Trace Cache Trace Cache Rename/Alloc AGU AGU ALU ALU ALU ALU 3 3 FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive Drive: Wire delay Drive the uOPs to the allocator System Interface L2 Cache and Control Integer RF BTB Rename/Alloc Trace Cache AGU AGU ALU ALU ALU ALU 3 3 FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive Alloc: Allocate Allocate resources required for execution. The resources include Load buffers, Store buffers, etc.. System Interface L2 Cache and Control Integer RF BTB Rename/Alloc Rename/Alloc Trace Cache AGU AGU ALU ALU ALU ALU 3 3 FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive Rename: Register renaming Rename the logical registers (EAX) to the physical register space (128 are implemented). System Interface L2 Cache and Control Integer RF BTB Rename/Alloc Rename/Alloc Trace Cache AGU AGU ALU ALU ALU ALU 3 3 FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive Que: Write into the uOP Queue uOPs are placed into the queues, where they are held until there is room in the schedulers System Interface L2 Cache and Control Integer RF BTB Rename/Alloc AGU AGU ALU ALU ALU ALU 3 3 FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- uop Queues uop Queues Trace Cache BTB & I-TLB I- Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive Sch: Schedule Write into the schedulers and compute dependencies. Watch for dependency to resolve. System Interface L2 Cache and Control Integer RF BTB Rename/Alloc Trace Cache AGU AGU ALU ALU ALU ALU 3 3 FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive Disp: Dispatch Send the uOPs to the appropriate execution unit. System Interface L2 Cache and Control Integer RF BTB Rename/Alloc Trace Cache AGU AGU ALU ALU ALU ALU 3 3 FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive RF: Register File Read the register file. These are the source(s) for the pending operation (ALU or other). System Interface L2 Cache and Control Integer RF Integer RF BTB Rename/Alloc Trace Cache AGU AGU ALU ALU ALU ALU 3 3 FP RF FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive Ex: Execute Execute the uOPs on the appropriate execution port. System Interface L2 Cache and Control Integer BTB RF Rename/Alloc Trace Cache AGU AGU AGU AGU ALU ALU ALU ALU ALU ALU ALU ALU 3 3 FP RF Fms Fop Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive Flgs: Flags Compute flags (zero, negative, etc..). These are typically the input to a branch instruction. System Interface L2 Cache and Control Integer RF BTB Rename/Alloc Trace Cache AGU AGU AGU AGU ALU ALU ALU ALU ALU ALU ALU ALU 3 3 FP RF Fms Fop Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive Br Ck: Branch Check The branch operation compares the result of the actual branch direction with the prediction. System Interface L2 Cache and Control Integer RF BTB Rename/Alloc Trace Cache AGU AGU ALU ALU ALU ALU ALU ALU ALU ALU 3 3 FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX Hyper Pipelined Technology 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF Fall 2000 16 RF 17 Ex 18 19 20 TC Nxt IP TC Fetch Drive Alloc Rename Que Sch Sch Sch Disp Disp Flgs Br Ck Drive Drive: Wire delay Drive the result of the branch check to the front end of the machine. System Interface L2 Cache and Control Integer RF BTB Rename/Alloc Trace Cache AGU AGU ALU ALU ALU ALU 3 3 FP RF Fms Fop ROM Copyright 2000 Intel Corporation. L1 D -Cache and D -TLB DD- BTB & I-TLB I- uop Queues Schedulers Decoder Intel PDX CPU Architecture 101 Fall 2000 Delivered Performance = Delivered Performance = Frequency ** Instructions Per Cycle Frequency Instructions Per Cycle Instructions Per Cycle Instructions Per Cycle Intel Copyright 2000 Intel Corporation. PDX Improving Instructions Per Cycle l Improve Fall 2000 efficiency Do more things in a clock Branch prediction l Reduce time it takes to do something Reducing latency Intel Copyright 2000 Intel Corporation. PDX Improving Instructions Per Cycle l Improve Fall 2000 efficiency Branch prediction Do more things in a clock l Reduce time it takes to do something Reducing latency Intel Copyright 2000 Intel Corporation. PDX Branch Prediction l Accurate Fall 2000 branch prediction is key to enabling longer pipelines l Dramatic improvement over P6 branch predictor: 8x the size (4K) Eliminated 1/3 of the mispredictions l Proven to be better than all other publicly disclosed predictors (g-share, hybrid, etc) Intel PDX Copyright 2000 Intel Corporation. The Execution Trace Cache Fall 2000 3.2 GB/s System Interface L2 Cache and Control Integer RF L1 D-Cache and D -TLB PDX BTB Rename/Alloc Trace Cache BTB & I-TLB uop Queues Store AGU Load AGU ALU ALU ALU ALU 3 3 Schedulers Decoder FP RF FP move FP store FMul FAdd MMX Intel SSE uCode ROM Copyright 2000 Intel Corporation. Execution Trace Cache l Advanced l Removes Fall 2000 L1 instruction cache Caches decoded IA -32 instructions (uops) decoder pipeline latency l Capacity is ~12K uOps l Integrates branches into single line Follows predicted path of program execution Execution Trace Cache feeds fast engine Execution Trace Cache feeds fast engine Intel Copyright 2000 Intel Corporation. PDX Execution Trace Cache 1 cmp 2 br -> T1 .. ... (unused code) T1: 3 sub 4 br -> T2 .. ... (unused code) 5 mov 6 sub 7 br -> T3 .. ... (unused code) 8 add 9 sub 10 mul 11 cmp 12 br -> T4 Intel Copyright 2000 Intel Corporation. Fall 2000 Trace Cache Delivery 1 4 7 cmp br T2 br T3 2 br T1 5 mov 8 T3:add 11 cmp 3 T1: sub 6 sub T2: 9 sub 12 br T4 10 mul T3: PDX Advanced Dynamic Execution l Extends Fall 2000 basic features found in P6 core l Very deep speculative execution 126 instructions in flight (3x P6) 48 loads (3x P6) and 24 stores (2x P6) l Provides larger window of visibility Better use of execution resources Deep Speculation Improves Parallelism Deep Speculation Improves Parallelism Intel Copyright 2000 Intel Corporation. PDX Improving Instructions Per Cycle l Improve Fall 2000 efficiency Do more things in a clock Branch prediction l Reduce time it takes to do something Reducing latency Intel Copyright 2000 Intel Corporation. PDX Rapid Execution Engine l Dramatically l P6: Fall 2000 lower ALU latency 1 clock @ 1GHz 1ns l Intel NetBurst micro-architecture: clock @ >1.4GHz <0.35ns Copyright 2000 Intel Corporation. Intel PDX L1 Data Cache Fall 2000 3.2 GB/s System Interface L2 Cache and Control Integer RF L1 D-Cache and D -TLB PDX BTB Rename/Alloc Trace Cache BTB & I-TLB uop Queues Store AGU Load AGU ALU ALU ALU ALU 3 3 Schedulers Decoder FP RF FP move FP store FMul FAdd MMX Intel SSE uCode ROM Copyright 2000 Intel Corporation. High Performance L1 Data Cache l 8KB, Fall 2000 4-way set associative, 64-byte lines l Very high bandwidth 1 Ld and 1 St per clock l New access algorithms l Very low latency 2 clock read New algorithm enables faster cache New algorithm enables faster cache Intel Copyright 2000 Intel Corporation. PDX Data Speculation l Observation: Fall 2000 Almost all memory accesses hit in the cache l Optimize for the common case Assume that the access will hit the cache Use a low cost mechanism to fix the rare cases that miss l Benefit: Reduces latency Significantly higher performance Intel Copyright 2000 Intel Corporation. PDX Replay l Repairs l Replay Fall 2000 incorrect speculation Re-execute until correct is uOP specific Replay the uOP that mis-speculated Replay dependent uOPs Independent uOPs are not replayed Efficient mechanism to reduce latency Efficient mechanism to reduce latency Intel Copyright 2000 Intel Corporation. PDX L1 Cache is >2x Faster l P6: Fall 2000 3 clocks @ 1GHz 3ns l Intel NetBurst micro-architecture: 2 clocks @ 1.4GHz <1.4ns Lower Latency is Higher Performance Lower Latency is Higher Performance Intel Copyright 2000 Intel Corporation. PDX Example with higher IPC and Faster Clock! Code Sequence Ld Add Add Ld Add Add Fall 2000 P6 @1GHz Intel NetBurst Micro-architecture @1.4GHz 10 clocks 10ns IPC = 0.6 Copyright 2000 Intel Corporation. 6 clocks 4.3ns IPCIntel = 1.0 PDX L2 Advanced Transfer Cache Fall 2000 3.2 GB/s System Interface L2 Cache and Control Integer RF L1 D-Cache and D -TLB PDX BTB Rename/Alloc Trace Cache BTB & I-TLB uop Queues Store AGU Load AGU ALU ALU ALU ALU 3 3 Schedulers Decoder FP RF FP move FP store FMul FAdd MMX Intel SSE uCode ROM Copyright 2000 Intel Corporation. L2 ATC Organization l 256KB, Fall 2000 8-way set associative 128-byte lines Two 64-byte pieces per line l Holds both data and instructions l High bandwidth: 45 GB/Sec @ 1.4GHz 2.8x P6 @1GHz Intel Copyright 2000 Intel Corporation. PDX Aggregate Cache Latency l Function Fall 2000 of all caches in a processor l Overall Effective Latency L1 latency + L1 Miss Rate * L2 latency + L2 Miss Rate * DRAM Latency Average cache speed is >1.8x better Average cache speed is >1.8x better than the Pentium III Processor than the Pentium III Processor Average on desktop applications, Intel Pentium III processor @ 1GHz, Intel Pentium 4 processor @ 1.4GHzIntel processor Copyright 2000 Intel Corporation. PDX Comparison Pentium III Processor Frequency Adder Speed Adder Bandwidth L1 Cache Speed L1 Cache Size L1 Cache Bandwidth L2 Cache Bandwidth Instructions In flight Loads in flight Stores in flight Branch targets Uop Fetch Bandwidth 1 GHz 1 ns 2 billion/sec 3 ns 16 KB 16 GB/sec 16 GB/sec 40 16 12 512 3 billion/sec Pentium 4 Processor 1.4 Ghz < .36 ns 5.6 billion/sec < 1.42 ns 8 KB 44.8 GB/sec 44.8 GB/sec 126 48 24 4092 4.2 billion/sec Relative 1.4 2.8 > 2.8 2.1 0.5 2.8 2.8 3.15 3 2 8 1.4 Fall 2000 Improvement Intel Copyright 2000 Intel Corporation. PDX Intel Pentium 4 Processor Summary l Revolutionary, Fall 2000 new microarchitecture from Intel designed for the evolving Internet l Design features for balanced, high performance platform scalability and headroom l The worlds highest performance desktop processor Intel Copyright 2000 Intel Corporation. PDX
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LSU - EE - 7700
AMDs Next Generation Microprocessor ArchitectureFred WeberOctober 2001&quot;Hammer&quot; Goals Build a next-generation system architecture which serves as the foundation for future processor platforms Enable a full line of server and workstation products
LSU - EE - 7700
April 21, 20041The Itanium Architecture A Technical OverviewThomas Siebold Technical Consultant Transition Engineering &amp; Consulting Business Critical Server Division thomas.siebold@hp.com Rev. 6.5 2004 Hewlett-Packard Development Company, L.P.
LSU - EE - 4720
11-1This Set11-1These slides do not give detailed coverage of the material. See class notes and solved problems (last page) for more information. Text covers multiple-issue machines in Chapter 4, but does not cover most of the topics presented
LSU - STAT - 7034
EXST7034 Regression Techniques Multiple Regression 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15Fall 2004 SAS examplesGeaghan Page 1*; * EXST7034 Multiple Regression Example *; * Problem from Neter, Kutner, Nachtsheim &amp; Wasserman 1996, #6.18 *; *; OPTIO
LSU - STAT - 7034
EXST7034 Regression Techniques Multiple RegressionFall 2004 SAS examplesGeaghan Page 11 *; 2 * EXST7034 Multiple Regression Example *; 3 * Problem from Neter, Kutner, Nachtsheim &amp; Wasserman 1996, #6.18 *; 4 *; 5 6 OPTIONS LS=99 PS=80 NOCENTER
LSU - STAT - 7034
EXST7034 Regression Techniques Multiple RegressionFall 2004 SAS examplesGeaghan Page 11 *; 2 * EXST7034 Multiple Regression Example *; 3 * Problem from Neter, Kutner, Nachtsheim &amp; Wasserman 1996, #6.18 *; 4 *; 5 6 OPTIONS LS=99 PS=80 NOCENTER
LSU - STAT - 7034
EXST7034 Chapter 11Multiple Regression Bootstrapping (Toluca example)Geaghan Page 1Toluca Company Example (Problem from Neter, Kutner, Nachtsheim &amp; Wasserman 1996,1.21) A particular part needed for refigeration equipment replacement parts are p
LSU - STAT - 7034
EXST7035 : Regression Techniques Analysis of Covariance &amp; PiecewiseFall 2004 SAS exampleGeaghan Page 11 *; 2 * EXST7034 Homework Example 1 *; 3 * Problem from Neter, Wasserman &amp; Kuttner 1989, #11.16 *; 4 *; 5 OPTIONS LS=82 PS=61 NOCENTER NODATE
LSU - STAT - 7034
EXST7034 Chapter 12Time series Microcomputer exampleGeaghan Page 11 *; 2 * EXST7034 Homework Example *; 3 * Problem from Neter, Wasserman &amp; Kuttner 1989, 13.92 *; 4 **; 5 6 dm'log;clear;output;clear'; 7 options nodate nocenter nonumber ps=512 l
LSU - STAT - 7034
EXST7015 : Statistical Techniques II Random coefficients regressionWeight Lifting exampleGeaghan Page 11 /*-2 SAS System for Mixed Models (1996) 3 by Ramon C. Littell, Ph.D., George A. Milliken, Ph.D., 4 Walter W. Stroup, Ph.D., and Russell D.
LSU - STAT - 7034
EXST7034 - Regression Techniques Simple Linear Regression Data: Neter, Wasserman &amp; Kuttner (1989), Page 57, Problem 2.19. _ X Y Y 0 8, 9, 11, 12 10 1 13, 15, 16 14.67 2 17, 19 18 3 22 22 Intermediate Calculations _ DX3 = 10; DX2 = 20; D(X3 -X)2 = 10;
LSU - STAT - 7034
EXST7034 - Regression Techniques POWER 1 &quot; in testing regression coefficients.Page 1If we reject a null hypothesis, we need not concern ourselves with power. If we reject H! , we have a (1-!)100% chance of having made an error (called TYPE I er
LSU - STAT - 7034
LSU - STAT - 7034
EXST7034 - Regression Techniques EXAMPLE: Using SAS to test hypotheses about &quot;! and &quot; EXST7034 - EXAMPLE 1Page 1Program Statements *; * EXST7034 Example 1 using PC-SAS *; * Problem from Neter, Wasserman &amp; Kuttner 1989, 2.19 *; *; OPTIONS LS=80 PS
LSU - STAT - 7034
EXST7034 - Regression Techniques Using F tests instead of t-testsPage 1We can also test the hypothesis H! :&quot; 0 versus H&quot; :&quot; 0 with an F test. FMSRegression MSErrorThis test is mathematically identical to the previous test of H! :&quot; =0 done wi
LSU - STAT - 7034
EXST7034 - Regression TechniquesPage 1Prediction of a new observation : note that this is a single observation, not the regression line. First, the variance of a generic linear combination (from Chapter 1:1.27a &amp; b) T aW bX cZ E(T) aE(W) bE(
LSU - STAT - 7034
EXST7034 - Regression Techniques General Linear Hypothesis Test Approach (GLHT) Given a Regression Model with all variables of interest Y3 = b! b&quot; X3 e3 we will call this the FULL model = Y3 b&quot; (X3 - X) e3Page 1Given a second Regression Mod
LSU - STAT - 7034
EXST7034 - Regression Techniques Regression diagnostics dependent variable Y3Page 1There are a number of graphic representations which will help with problem detection and which can be used to obtain a better understanding of the dataset availab
LSU - STAT - 7034
EXST7034 - Regression Techniques Lack of Fit and Pure Error Assumed Model: Yij = &quot;! + &quot; Xj + %ij %ji 's NID(0,5 2 ) Question: Are we sure that E(Yij ) = &quot;! + &quot; XjPage 1Answer: We will NEVER be absolutely sure, we should try to check it. Procedur
LSU - STAT - 7034
EXST7034 - Regression Techniques SIMPLE LINEAR REGRESSION WITH MATRIX ALGEBRA MODEL: Y3 = &quot;! + &quot; X3 + %3 MATRIX MODEL: Y = XB + E Y&quot; 1 Y 1 or # = Y8 1 X&quot; e&quot; X# b! e # b&quot; e8 X8 Page 1Where, Y is the vector of dependent vari
LSU - STAT - 7034
Coefficient of Partial Determination As the R2 provides information about the SSR(X&quot; ,X# ,X$ ), there are also Coefficients of PARTIAL Determination : this measures how much variation a variable accounts for out of the variation available to that var
LSU - STAT - 7034
POLYNOMIAL REGRESSION (Chapter 9) We have discussed curvilinear regression from transformations and polynomials 1) Transformations generally more interpretable, often more easily interpreted in terms of a possible functional relationship. (extrapolat
LSU - STAT - 7034
Building a Regression Model. 1) Think about the regression in advance. a) What variables are needed? Is it available? Is it readily measurable? Are there redundancies? b) How many observations are needed? More variables to be examined requires more c
LSU - STAT - 7034
Multicolinearity Diagnostics : Some of the diagnostics we have just discussed are sensitive to multicolinearity. For example, we know that with multicolinearity, additions and deletions of data cause shifts in the regression coefficients, this will b
LSU - STAT - 7034
Qualitative indicator variables An indicator variable is a distinguishing between qualitative categories. The easiest way creating an indicator variable is to 1) choose the category to be singled out 2) In a separate column of the X matrix, put a 1 w
LSU - STAT - 7034
Autocorrelation - particularly in data taken over time We assume errors are independent. What if they are not, such that the residual at time t is correlated to the previous residual at time t-1. This may cause runs of + or in the residuals. This
LSU - STAT - 7034
REGRESSION ON AN INDICATOR VARIABLE In this technique, the dependent variable (Y) is an indicator, and takes a value of either 0 or 1. This is called a binary response variable1 Response 0 Independent Variable(s)Examples any two categories, any
LSU - STAT - 7034
EXST7034 : Regression Techniques Logistic regressionGeaghan Page 1Simple linear regression on an indicator variable a precursor to logistic regression Basically it is a simple linear regression where the dependent variable has a value of either
LSU - STAT - 7034
Statistical Techniques IIEXST7015Logistic Regression13a_LogisticReg 1Regression on an indicator variableWhat is an indicator variable? It is a variable with either the value 0 or 1.When we get to ANOVA we will see that class variables (categ
LSU - STAT - 7034
EXST7034 Regression Techniques Assignment 1Fall 2005 Page 1EXST7034 : Regression TechniquesHOMEWORK ASSIGNMENTS : General Information PC/NT Workstations are available in room 11 and room 48, both in the basement of the Ag. Admin. Building. Clas
LSU - STAT - 7034
EXST7034 Regression Techniques Homework 1Fall 2005 Answer sheetGeaghan Page 1The SAS program I used to obtain the analyses for my answers is given below.dm'log;clear;output;clear'; *; * EXST7034 Homework Example 1 *; * Problem from Neter, Was
LSU - STAT - 7034
EXST7034 Regression Techniques Homework 2Fall 2004Geaghan Page 1HOMEWORK ASSIGNMENT 2Assigned: September 20, 2005 Due: September 27 or 29, 200510 Points 1 point each day lateA) Complete the following questions using the values from probl
LSU - STAT - 7034
EXST7034 Regression Techniques Homework 2Fall 2005 Answer sheetGeaghan Page 9The SAS program I used to obtain the analyses for my answers is given below.dm'log;clear;output;clear'; *; * EXST7034 Homework Example 1 *; * Problem from Neter, Was
LSU - STAT - 7034
EXST7034 Regression Techniques Homework 2Fall 2005Geaghan Page 1HOMEWORK ASSIGNMENT 3Assigned: October 13, 2005 Due: October 20, 200510 Points 1 point each day lateComplete the following questions from your textbook. The problems come fr
LSU - STAT - 7034
EXST7034 Regression Techniques Homework 3Fall 2005 Answer sheetGeaghan Page 17The SAS program I used to obtain the analyses for my answers is given below.*; * EXST7034 Homework Example **; * Applied Linear Statistical Models, 5th Edition, 200
LSU - STAT - 7034
EXST7034 Regression TechniquesFall 2005 GeaghanAssigned: October 20, 2005 Due: October 27, 200510 Points 1 point each day lateHOMEWORK ASSIGNMENT 4Complete the following questions from your textbook. The problems come from the &quot;Patient sati
LSU - STAT - 7034
EXST7034 Regression Techniques Homework 4Fall 2005 Answer sheetGeaghan Page 24proc GLM data=Satisfaction; TITLE2 'Analysis with GLM'; MODEL Y=X2 X1 X3; RUN; proc REG data=Satisfaction; TITLE2 'Analysis with REG'; MODEL Y=X1 X2 X3 / vif stb PCO
LSU - STAT - 7034
EXST7034 Regression TechniquesHOMEWORK ASSIGNMENT 5Fall 2005Assigned: October 27, 2005 Due: November 3, 200510 Points 1 point each day lateSteroid use problem from chapter 8. The data is in dataset &quot;http:/www.stat.lsu.edu/EXSTWeb/statlab/dat
LSU - STAT - 7034
EXST7034 Regression Techniques Homework 5Fall 2005 Answer sheetGeaghan Page 24The SAS program I used to obtain the analyses for my answers is given below.dm'log;clear;output;clear'; options nodate nocenter nonumber ps=512 ls=99 nolabel; ODS H
LSU - STAT - 7034
EXST7034 Regression TechniquesHOMEWORK ASSIGNMENT 6Fall 2003Assigned: November 3, 2005 Due: November 10, 200520 Points 1 point each day lateAll data is in &quot;http:/www.stat.lsu.edu/EXSTWeb/statlab/datasets/KNNLdata/&quot;. Complete the following qu
LSU - STAT - 7034
EXST7034 Regression Techniques Homework 6Fall 2005 Answer sheetGeaghan Page 31The program for the following sections follows.dm'log;clear;output;clear'; *; * EXST7034 Homework Example 1 **; * Problem from Neter, Wasserman &amp; Kuttner 1989, #2.1
LSU - STAT - 7034
EXST7034 Regression TechniquesHOMEWORK ASSIGNMENT 7Fall 2003Assigned: December 1, 2005 Due: December 8, 200510 Points 1 point each day lateAll data is in &quot;http:/www.stat.lsu.edu/EXSTWeb/statlab/datasets/KNNLdata/&quot;. Do the car purchase exampl
LSU - STAT - 3201
EXST3201 Background material From the textbook The Statistical SleuthPage 1Mean [20]: In your text the word mean denotes a population mean () while the work average denotes a sample average (Y). Variance [20]: The variance is a measure of the di
LSU - STAT - 3201
An Introduction to SAS Programming SAS programs consists of two major type of steps The DATA step used to create or modify a SAS dataset [Contents &gt; SAS Products &gt; Base SAS &gt; SAS Language concepts &gt; Data Step Concepts] SAS dataset a file containin
LSU - STAT - 3201
EXST3201 Mousefeed01Page 13 /* 4 Examine differences among the following 6 treatments 5 N/N85 fed normally before weaning and 85 kcal/wk after 6 N/R40 fed normally before weaning and 40 kcal/wk after 7 N/R50 fed normally before weaning and 50 kc
LSU - STAT - 3201
EXST3201 Chapter 5 Analysis of Variance [Chapter 5]GeaghanFall 2005: Page 1Testing between two samples is readily done with the two-sample t-test. In this situation we compare two groups (also referred to as classes, categories, treatments or i
LSU - STAT - 3201
EXST3201 Mousefeed02Page 11 /* 2 Examine differences among the following 6 treatments 3 N/N85 fed normally before weaning and 85 kcal/wk after 4 N/R40 fed normally before weaning and 40 kcal/wk after 5 N/R50 fed normally before weaning and 50 kc
LSU - STAT - 3201
EXST3201 Anatomy of a SAS program*; * The initial part of the program will *; * often have some comments. *; * - *; * Little boxes and lines are a nice *; * way to isolate these comments and *; * make them stand out. *; * - *; * For this box a comm
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EXST3201 Chapter 5 Analysis of Variance [Chapter 5, part 2]GeaghanFall 2005: Page 1A second case of analysis of variance, the Dr. Spock conspiracy trail. This case is an observational study, so the data does not come from a planned experiment,
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EXST3201 SpockTrial01aPage 11 /* 2 Fit an analysis of variance to determine if the jury for 3 spock trial was unusually low in the number of women. 4 */ 5 6 /* 7 SAS applications of note: 8 By statement with NOTSORTED 9 use of if statement to cr
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EXST3201 Chapter 5GeaghanFall 2005: Page 1The text describes the analysis of variance in terms of the extra sum of squares principle. This is a useful concept with many applications, and will be demonstrated on two applications to the Spock tri
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EXST3201 Chapter 6 Linear combinationsGeaghanFall 2005: Page 1A linear combination consists of a series of variables multiplied by constants. For a series of k variables the linear combination could be expressed as follows. Generic linear combi
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EXST3201 Chapter 6GeaghanFall 2005: Page 1Tests based on the t-test and Multiple range tests One of the strengths of contrasts is that they should, in general, be made a priori. This means that the investigator is not conducting a wide search f
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EXST3201 Mousefeed03bPage 1Below are Tukey adjusted pairwise comparisons done in PROC MIXED with range tests output from Saxtons macro. options ps=512 ls=88; proc mixed data=MouseDiet cl covtest; Title2 'Analysis of Variance with PROC MIXED'; cl
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Statistical Analysis II EXST3201Simple Linear Regression03a_SLR 1The objectiveGiven points plotted on two coordinates, Y and X, find the best line to fit the data.Y - the dependent variable35302520012345678910X
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EXST3201 Chapter 8aGeaghanFall 2005: Page 1Chapter 8 (More on Assumptions for the Simple Linear Regression) Chapter 8 covers the assumptions behind the SLR, and some alternative models that can be used. One of those alternatives involves the us
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EXST3201 Chapter 8bGeaghanFall 2005: Page 1Chapter 8 (More on Assumptions for the Simple Linear Regression) Your textbook considers the following assumptions: Linearity This is not something I usually consider an explicit assumption, but obvio
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EXST3201 Chapter 8cGeaghanFall 2005: Page 1Chapter 8 (A little more on Assumptions for the Simple Linear Regression) Linearity assumption the best way to determine an appropriate model is to examine the literature for a theoretical model, or t
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EXST3201 : Statistical Analysis II Spring 2005 Multiple Regression Extra Sum of Squares 37 38 39 40 41 42 43 44 PROC REG MODEL MODEL MODEL MODEL MODEL MODEL MODEL DATA=ONE; Y = X1; Y = X2; Y = X3; Y = X1 X2 Y = X1 X3 Y = X2 X3 Y = X1 X2 TITLE2 'Sub
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EXST3201 Chapter 9a Chapter 9 : Multiple RegressionGeaghanFall 2005: Page 1The first example of multiple regression is a designed experiment. The experiment involves the development of flowers on Meadowfoam a small cultivated plant used for its
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EXST3201 Chapter 9bGeaghanFall 2005: Page 1Interpretation of regression coefficients: For the simple linear regression we know that the units of the intercept are the same as the units on the variable Y. The slope has units of Y units per X uni