Lab ECE-342 3: NMOS Characteristics
Stephanie Duy, Robert England Lab Group 4 October 29, 2007
Abstract This report describes the design and test of a voltage-controlled voltage amplifier. The amplifier uses an NMOS transistor in a CD4007 integrated circuit as a voltage-controlled resistance. The amplifier uses three LF351 op-amps, and requires 12 V power supplies. The amplifier limits voltage inputs to above -200 mV to prevent device damage, and achieves a measured 19.5 dB gain with a 0 V input to the voltage controlling the CD4007's resistance, and 29.1 dB gain with a 1 V input to the control voltage. The amplifier has a corner frequency of 100 kHz at maximum gain. Component selection and test procedures are described.
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Contents
1 2 Introduction Circuit Design and Preliminary Analysis 2.1 Basic Amplifier Design 2.2 Control Input Scaler Design 2.3 Power Input Clamp Design Simulated Performance 3.1 CD4007 Simulation 3.2 Amplifier Simulation Experimental Implementation 4.1 MOSFET characteristics 4.2 Amplifier Analysis 4.2.1 Basic Amplifier Analysis 4.2.2 Control Input Scaler Analysis 4.2.3 Power Input Clamp Analysis 4.2.4 Complete Circuit Analysis Discussion Conclusion Design Calculations A1 Control Input Scaler Design Calculations A2 Power Input Clamp Design Calculations A3 Control Input Scaler Experimental Calculations 3 4 5 7 8 9 10 12 15 15 20 20 21 22 23 28 29 30 30 32 34
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Calculating a Best-Fit Line______________________________36
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1. Introduction
This report describes the design and implementation of a voltage-controlled amplifier using the NMOS, or n-type MOSFET, of a CD4007 chip as a voltagecontrolled resistance. The resistance characteristics of the MOSFET were tested by measuring the drain voltage and current of the device at specific gate voltages. These data points were then plotted, and the resistance obtained as the inverse of the slope of the linear (non-saturated) region of the plot. A non-inverting amplifier was then constructed to create a gain between 20 dB and 30 dB, controlled by a control voltage. In order to meet specifications, the amplifier included a clamp circuit to limit input signals to above -200 mV in order to prevent device damage, and a scaling circuit so that the control voltage produces a gain of 20 dB at 0 V, and 30 dB at 1 V. Section 2 details the process of designing the amplifier circuit, including the calculation of component values. Section 3 presents the results of a simulation of both a solitary transistor and the entire amplifier circuit. Section 4 presents experimental measurements taken on the amplifier circuit, and describes the process of finding a more accurate model for the NMOS. Section 5 summarizes the results of the amplifier. Appendix A contains the calculations for each section of the amplifier. Appendix B details the process of finding the best-fit linear approximation of a series of data points.
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2. Circuit Design and Preliminary Analysis
The circuit is intended to be a voltage-controlled amplifier with two inputs (the power input Vin and the control input VC) and one output (Vout). The output voltage is magnified from the power input, and the amount of this magnification is controlled by the control input. The primary specification for the circuit was that the gain between the output and the power input must range from 20 dB to 30 dB, with the power input having a magnitude under 200 mV. The amplifier was to be powered with 12 V power supplies. There were two further, optional specifications for the circuit: The gain should be 20 dB when the input control voltage is 0 V and 30 dB when the input control voltage is 1 V. The device should be protected from power inputs exceeding 200 mV in magnitude. It is also desirable for the filter to have a wide operating bandwidth. The optional specifications are most easily implemented as additions to an already working amplifier. As such, the first of the following subsections details the design of the actual amplifier, while the subsections after discuss scaling the control input to the proper operating range and clamping the power input to remain within a range to avoid damage. The end circuit would have a layout similar to Figure 1 below.
Figure 1: Amplifier layout. Each of these sections can be designed independently. Any op-amps used in the circuit will be LF351 op-amps with 12 V power supplies.
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2.1 Basic Amplifier Design
A typical voltage amplifier, using a simple op-amp feedback system, is shown in Figure 2.
Figure 2: A typical voltage amplifier. This amplifier uses the simplest noninverting configuration, and has a gain of 1+Rf1/Rn1. An N-channel MOSFET in the ohmic region (low drain-to-source voltage) was used as a voltage-controlled resistance. The MOSFET works best if its body and source are both connected to ground, so the MOSFET would take the place of Rn1. The desired output gain (G) ranges from 20 to 30 dB, or 10 to 31.6 V/V. Using a typical transistor small-signal resistance of 2 k, a set of values for Rf1 can be calculated with the following three equations. R f1=G-1 R n1 R f1 min =10-12000=18 k R f1 max=31.6-12000=61.2 k 1 2 3
A 30 k resistor was chosen for Rf1 as a central value. Figure 3 is a schematic of the basic amplifier.
Figure 3: Basic voltage amplifier design
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The required resistance range for the transistor is calculated with the following three equations. G-1 R n1= 4 R f1 30000 R n1 min = =971 5 31.9-1 30000 R n1 max= =3000 6 10-1 Using the transistor simulation in Section 3.1 of this report, these values correspond approximately to 3 V and 5.16 V at the transistor gate respectively.
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2.2 Control Input Scaler Design
The function of the input scaler must be to scale a control input of 0 V to a gate voltage of 3 V, and a control input of 1 V to a gate voltage of 5.16 V. A summing amplifier would be required to create an output of 3 V from an input of 0 V; a typical summing amplifier schematic is shown in Figure 4 below.
Figure 4: A typical summing amplifier. The labels have been subscripted with "2" to differentiate from the previous section. Here, Va is the input control voltage, while Vout2 is the gate voltage of the transistor. For simplicity, Vb was chosen to be the +12 V upper power supply of the circuit. Appendix A1 contains the derivation of the five resistors involved with this circuit. Table 1 contains the calculated values of these resistors. Table 1: Calculated resistor values for the control input scaler Ra2 736 Rb2 6344 Rp2 1 k Rn2 1 k Rf2 3 k 7
2.3 Power Input Clamp Design
The most fragile element in the amplifier circuit is the transistor; it cannot have a drain voltage under -0.3 V without melting. Otherwise, the circuit is safe from any input within several volts. Due to the nature of the amplifier, the drain voltage is approximately equal to the input voltage, so the specification will be fulfilled simply by keeping the input to the amplifier above -0.2V (the minimum operation voltage). A good way to do this is with a simple diode clamp, as shown in Figure 5.
Figure 5: Basic diode clamp circuit Vout3 is limited to values above the difference between Vclamp and the threshold voltage of the diode. The most readily available diode, 1N4004, has a threshold voltage of 0.6 V, so Vclamp should be 0.4 V. Again for simplicity, the +12 V power supply voltage was scaled to create the proper output with an op-amp. Appendix A.3 details the process of designing the circuit used to scale the +12 V to 0.4 V; the completed circuit is shown in Figure 6.
Figure 6: Complete power input clamp circuit 8
3. Simulated Performance
Figure 7 shows the complete schematic for the amplifier circuit. Where necessary, the values calculated were replaced by the closest available component values.
Figure 7: Complete voltage-controlled amplifier schematic, labeled with available component values Two different items were simulated in MicroCap. First, the transistor itself was simulated for low drain-to-source voltages to characterize its resistance; this characterization was used in the design to find the required gate voltages in the design of the basic amplifier in Section 2.1. Then, the entire circuit was simulated to test the output response to the two inputs.
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3.1 CD4007 Simulation
The transistor used and modeled is one of the transistors in a CD4007 chip. Figure 8 is a plot of the current entering the drain of the circuit compared to the gate and drain voltages.
Figure 8: Current through the transistor compared to terminal voltages. The horizontal axis of the plot is the drain voltage, while the labeled individual curves are various gate voltages.
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The resistance of the transistor for each gate voltage is the inverse of the slope of this plot. Table 2 contains the resistance of the transistor for each of the gate voltages. Table 2: Resistance at the gate voltages. Gate Voltage Slope Resistance 1V 2V 3V 4V 5V 6V 7V 8V 9V 484.5 pS 484.5 pS 300.2 S 633.5 S 966.7 S 1.300 mS 1.632 mS 1.965 mS 2.297 mS 2.06 G 2.06 G 3.33 k 1.58 k 1.03 k 769 613 509 435
The threshold voltage of the transistor is almost exactly 2 V. Figure 9 is a plot of these resistor values, with the exception of those below the threshold voltage.
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Figure 9: Transistor resistance vs. Gate voltage 11
3.2 Amplifier Simulation
The circuit simulated is shown again in Figure 10.
Figure 10: The complete amplifier circuit used in the simulation
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Figure 11 plots the decibel gain of the amplifier against the two inputs.
Figure 11: Amplifier gain vs. input voltages. The horizontal axis of the plot is the power input voltage, while the individual labeled curves correspond to the labeled values of the control input voltage. The unusual trait around 0 V occurs due to the exponential diode model used for the clamp circuit. Figure 12 is a plot of the gain over the control input voltage with the power input voltage kept at a constant 0.2 V.
Figure 12: Amplifier gain vs. control input voltage (Vin = 0.2 V) 13
Figure 13 plots the decibel gain of the amplifier against the frequency of the power input when the control input is 1 V.
Figure 13: Gain of the amplifier vs. frequency. The amplifier has a bandwidth of 130 kHz.
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4. Experimental Implementation
As with the simulation, first the transistor itself was examined and tested, and then the entire amplifier circuit was analyzed. DC voltages were generated with Agilent E3630A power supplies; AC signals were generated with an Aglient 33120A function generator. DC voltages were measured experimentally with a Keithley 175 Autoranging Multimeter; AC signals were measured with an HP 54603B oscilloscope.
4.1 MOSFET characteristics
A schematic of the CD4007 chip is shown in Figure 14 below. For the purposes of this experiment, VDD = +12 V, and VSS = 0 V.
Figure 14: CD4007 chip schematic Because transistor Q5 was the only transistor used in this experiment, all pins except for pin 14 (VDD), pin 3 (the gate voltage VG), and pin 5 (the drain voltage VD) were tied to ground.
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To test the transistor, the circuit in Figure 15 below was constructed.
Figure 15: Circuit used for testing the MOSFET characteristics The threshold voltage VT was experimentally found to be just under 1.5 V; this was the point at which the points taken for the voltage and current stabilized dramatically. Data was taken to find voltage/current curves for various values of Vg; Figures 16 to 20 below illustrate the results.
Figure 16: Voltage vs. current for Vg = 1.5472 V
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Figure 17: Voltage vs. current for Vg = 3.984 V
Figure 18: Voltage vs. current for Vg = 6.048 V
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Figure 19: Voltage vs. current for Vg = 8.000 V
Figure 20: Voltage vs. current for Vg = 10.007 V
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A best-fit line was then applied to the linear (non-saturated) portion of each graph1, and RDS was found by taking the inverse of the line's slope. Table 3 below details the results. Table 3: Resistance RDS for gate voltage Vg Vg (V) Slope of linear portion RDS () 1.5472 3.984 6.048 8.000 10.007 0.0004 0.0027 0.0039 0.0045 0.0054 2500 370.4 256.4 222.2 185.2
Figure 21 is a plot of these values, with a best-fit inverse approximation (made by inverting the best-fit linear approximation.
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Figure 21: Experimental resistance vs. gate voltage These values are significantly different from the values used in the simulation, so a different design for the control input scaler circuit would be needed. By these values, the transistor resistance would be 3.3 k when Vg is about 1.5 V, and it would be 980 when Vg is about 2 V.
1 A discussion on calculating a best-fit line is located in Appendix B.
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4.2 Amplifier Analysis
The amplifier was built in stages in the same order that it was designed; each stage was tested briefly before the next was attached to ensure that the amplifier was working properly.
4.2.1 Basic Amplifier Analysis
Figure 22 shows the basic amplifier with the component values measured by the multimeter.
Figure 22: Basic amplifier with measured resistor value As the transistor analysis resulted in values much different than the simulation, a brief check was performed to confirm the correct values of Vg. As stated in the previous section, Vg must range from 1.5 V to 2 V for the amplifier to achieve the correct output gain.
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4.2.2 Control Input Scaler Analysis
Appendix A3 details the redesign of the control input scaler to account for the new gate voltage range. Figure 23 shows the scaler circuit schematic with the final measured values.
Figure 23: Control input scaler with circuit measured component values. Note that the 6.75 k resistor was replaced by a 9.1 k resistor; 6.75 k proved to be too small upon construction of the circuit, and trial and error found that 9.1 k functioned better.
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4.2.3 Power Input Clamp Analysis
Figure 24 shows the power input clamp circuit schematic with its measured values.
Figure 24: Power input clamp circuit with measured component values. An isolated test of this circuit unattached from the remainder of the circuit showed that Vin2 remained mostly unchanged from Vin for values above -0.2 V, while values below -0.2 V were scaled dramatically. Vin2 did not reach -0.3 V until Vin reached -8.08 V, so this circuit would be safe for inputs above -8.08 V.
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4.2.4 Complete Circuit Analysis
Figure 25 shows the completed amplifier circuit with all measured values labeled.
Figure 25: Complete amplifier circuit with measured values. For analysis, the control input voltage (VC) was set at particular voltages, and Vg was measured. Then, Vin was set to a variety of DC values and Vp and Vout were measured. On the next three pages, Figure 26 plots Vg over VC, Figure 27 plots Vp over Vin, Figure 28 plots the decibel gain of the amplifier over both Vin and VC, and Figure 29 plots the decibel gain over VC.
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2 1 .9 5 1 .9 1 .8 5 1 .8 V g (V ) 1 .7 5 1 .7 1 .6 5 1 .6 1 .5 5 1 .5
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Figure 26: Vg vs. VC. Vg ranges from 1.53 V to 1.91 V.
0 .2 0 .1 8 0 .1 6 0 .1 4 0 .1 2 V p (V ) 0 .1 0 .0 8 0 .0 6 0 .0 4 0 .0 2 0
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Figure 27: Vp vs. Vin. Data was similar for all values of VC; this plot shows VC = 0.753 V because the data range was slightly longer than for other values of VC. 24
60 55 50 G a in (2 0 * lo g (V o u t / V in )) (d B ) 45 40 35 30 25 20 15
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Figure 28: Gain vs. Vin, plotted over VC. The filter works reasonably well between Vin = 0.05 V and Vin = 0.2 V.
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G a in (2 0 * lo g (V o u t / V in )) (d B )
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Figure 29: Amplifier gain vs. VC Vin = 0.1 V The lower gain is about 19.49 dB, a 2.55% error from 20 dB; the upper gain is 29.1 dB, a 3% error. The gain is slightly less than specified, likely due to the fact that Vg has a slightly different range than designed; this resulted merely from resistance tolerances (the closest available resistor to 59 k was labeled 62 k). The region Vin < 0.05 V has a dramatically increased gain. The power input clamp leaks a slight amount of voltage, which becomes significant for low values of Vin; this voltage leak is amplified, causing a greatly exaggerated gain.
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The amplifier was also tested with an AC signal for Vin. The magnitude of Vin was kept constant at 0.2 V and the frequency was changed; VC was kept constant at 1 V. The maximum and minimum values of the output were measured, and were used to find the AC magnitude of the signal; the AC magnitudes were then used to calculate the gain. The gain over frequency is plotted in Figure 30 below.
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25 G a in (A C m a g n it u d e o v e r in p u t ) (d B )
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Figure 30: Frequency response of the output. The gain is only 26 dB in the passband, significantly smaller than the designed 30 dB. The cutoff frequency is about 100 kHz. The signal also started distorting from a sinusoidal wave towards a sawtooth wave near the cutoff frequency.
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An attempt at measuring the output resistance of the amplifier was made by noting the difference in the output voltage when the output was open compared to when the output was connected to a 1 k resistor to ground. However, there was no measurable difference between the two voltages, proving that the output resistance was much smaller than the 1 k resistance. As smaller resistors failed to give stable voltages, the output resistance is simply too small to accurately measure. The current drawn from the power supply was also measured. A resistor, measured to be 1.21 , was placed between the power supply outputs and the input terminals of the circuit, and the voltage at each end was measured. Table 4 contains the data found and the current calculated. Table 4: Power supply current Voltage at Voltage at input Current power supply terminal drawn 12.012 V -12.010 V 12.004 V -12.005 V 6.6 mA -4.1 mA
5. Discussion
The model used to simulate the CD4007 transistor in the ohmic region gave results rather different than those actually measured in the laboratory setting. The model has a much higher threshold voltage, and the resistance changes more quickly with voltage. A better model for the ohmic region would have made a more accurate model and would have saved design time. The amplifier works reasonably well within its specifications. The output gains are reasonably close to the specifications at the maximum and minimum values of the control input voltage for DC values of the power input voltage with a magnitude between 50 mV and 0.2 V. Values within 50 mV work less accurately; a slight voltage is created at the output of the power input clamp from the exponential nature of the diode. Due to this, AC outputs contain a slight DC offset. The amplifier has a bandwidth of about 125 kHz; as this bandwidth is approached, the gain decreases, the DC offset increases, and the signal becomes more distorted. The output resistance proved to be too small to be accurately measured. The amplifier also draws about 6.6 mA from the +12 V supply and drains about 4.2 mA to the -12 V supply.
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Figure 31 is a plot of the gain over the control input voltage at Vin = 0.1 V.
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Figure 31: Amplifier gain vs. VC Vin = 0.1 V. The plot is mostly linear, with the gain ranging from 19.5 dB to 29.1 dB.
6. Conclusion
This report presented the design and testing of a voltage-controlled voltage amplifier. The ohmic model for a CD4007 NMOS transistor was investigated and tested, and the differences between a simulation model and a physical transistor were examined. The amplifier was built in stages and tested over a variety of inputs. The amplifier successfully created a gain of about 20 dB with a control input of 0 V, and a gain of about 30 dB with a control input of 1 V, when the power input had a magnitude between 50 mV and 0.2 V. The amplifier had a bandwidth of 125 kHz. The amplifier draws 6.6 mA from the positive power supply and drains 4.2 mA to the negative power supply. The amplifier works best for DC voltages between 50 mV and 0.2 V and between -50 mV and -0.2 V.
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Appendix A: Design Calculations
A1. Control Input Scaler Design Calculations
Figure A1 is the schematic for the control input scaler from Section 2.2.
Figure A1: Control input scaler schematic. Assuming an ideal op-amp, Vneg = Vpos. The sum of the currents leaving a node is zero, and no current flows through the inputs of an ideal op-amp, so Equation A1:1 can be written for node Vpos, and Equation A1:2 solves for Vpos. V pos-Va V pos -V b V pos =0A A1:1 Ra Rb Rp Va /R a Vb / R b V pos= A1: 2 1/ R a 1 / R b1/ R p The same can be done with node Vneg, solving for Vout (Equations A1:3 and A1:4). Vneg -Vout Vneg =0A A1:3 Rf Rn R V out =V neg 1 f A1: 4 Rn
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Equation A1:5 combines Equations A1:2 and A1:4 into one equation. Vout =
Va / R a Vb / R b 1/R a 1/ R b1/ R p
1 Rf Rn
A1: 5
The specifications require that when Va = 0 V, Vout = 3 V, and when Va = 1 V, Vout = 5.16 V. Vb is set to +12 V. As such, there are two separate states and can make two separate equations with five variables (the resistances). Three resistors can be chosen arbitrarily. For simplicity, Rp is chosen to be 1 k, Rf is chosen to be 3 k, and Rn is chosen to be 1 k. The two equations thus become Equations A1:6 and A1:7. 3=
0 / Ra 12/R b 1/R a 1/ R b1/1000
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1 /R a 12/R b 1/ Ra 1 /R b1/1000
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12 /R b 3000 =4 1000 1/R a 1/ R b0.001
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1/R a 12/ R b 3000 =4 1000 1/ Ra 1 /R b0.001
A1 :6 A1:7
The following derivation uses these two equations to calculate Ra and Rb. 12/R b 3 = =0.75 A1:8 1/R a 1/R b 0.001 4 1/R a 12/R b 5.16 = =1.29 A1: 9 1/R a 1/R b0.001 4 1/ Ra =1.29-0.75=0.54 A1:10 1 /R a 1/R b0.001 Ra 0.75 1 = =0.116 A1:11 Rb 12 0.54 1/ Ra 1 = =0.54 A1:12 1 /R a 1/R b0.001 1R a /R b0.001R a 10.1160.001 Ra =1/0.54=1.852 A1:13 R a =10001.852-1.116=736 A1:14 R b =R a /0.116=736/0.116=6344 A1:15
Table A1 contains the final values calculated for the scaler circuit. Table A1: Calculated resistor values for the control input scaler. Ra Rb Rp Rf Rn 736 6344 1 k 3 k 1 k
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A2. Power Input Clamp Design Calculations
Figure A2 is the schematic for the power input clamp from Section 2.2.
Figure A2: Power input clamp schematic When the diode is forward biased, Vout will be approximately equivalent to the diode threshold voltage plus Vclamp; when it is reverse biased, Vout is approximately Vin. At no time is Vout dependent upon Rd, so Rd is rather arbitrary; 1 k was chosen for convenience. The minimum value of Vout is equivalent to the difference between Vclamp and the threshold voltage of the diode. The most readily available diode is a 1N4004 diode, which has a threshold voltage of about 0.6 V. Vout must be above -0.2 V, so Vclamp must be 0.4 V. This can be done with the +12 V rail by using a voltage divider. However, Vclamp must be buffered; otherwise, Vin will contribute to the divider. A solution is to use an op-amp as shown in Figure A3.
Figure A3: Voltage divider and buffer
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Figure A3: Voltage divider and buffer (repeated) The only requirement is that Vcontrol is 0.4 V when the input is +12 V, so one equation can be found. There are four unknown resistors, so three can be arbitrarily chosen; Rn, Rf, and Rp are therefore chosen to be 1 k. Vpos is a voltage division of the +12 V input, and is calculated by Equation A2:1. V pos=12
Rp 12 = R p R a 10.001R a
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Equation A2:2, summing the currents leaving node Vneg, relates Vcontrol to Vneg; Equation A2:3 solves this for Vneg. V neg V neg-Vcontrol =0A A2: 2 Rn Rf V 1 0.4 1 V neg= control = =0.2V A2:3 Rf 1/ R n1/ Rf 1000 1/ 10001/1000
As the op-amp is assumed to be ideal, Vneg = Vpos. The result from Equation A2:3 can therefore be substituted into Equation A2:1 to solve for Ra as follows. 12 0.2= A2: 4 10.001 Ra R a =100012/0.2-1=59k A2:5 Table A2 contains the final values calculated for the clamp circuit. Table A2: Calculated resistor values for the power input clamp. Rd Ra Rp Rf Rn 1 k 59 k 1 k 1 k 1 k
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A3. Control Input Scaler Experimental Calculations
The calculations to find the new component values for the control input scaler are identical to those used before in Appendix Section A.1, only with different numbers. Figure A4 is the schematic for the control input scaler from Section 2.2.
Figure A4: Control input scaler schematic. Assuming an ideal op-amp, Vneg = Vpos. The sum of the currents leaving a node is zero, and no current flows through the inputs of an ideal op-amp, so Equation A3:1 can be written for node Vpos, and Equation A3:2 solves for Vpos. V pos-Va V pos -V b V pos =0A A3 :1 Ra Rb Rp Va /R a Vb /R b V pos = A3: 2 1/ Ra 1 /R b1 /R p The same can be done with node Vneg, solving for Vout (Equations A3:3 and A3:4). Vneg -Vout Vneg =0A A3:3 Rf Rn R V out =V neg 1 f A3: 4 Rn
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Equation A1:5 combines Equations A3:2 and A3:4 into one equation. Vout =
Va / R a Vb / R b 1/R a 1/ R b1/ R p
1 Rf Rn
A3: 5
The specifications require that when Va = 0 V, Vout = 3 V, and when Va = 1 V, Vout = 5.16 V. Vb is set to +12 V. As such, there are two separate states and can make two separate equations with five variables (the resistances). Three resistors can be chosen arbitrarily. For simplicity, Rp is chosen to be 1 k, Rf is chosen to be 3 k, and Rn is chosen to be 1 k. The two equations thus become Equations A3:6 and A3:7. 1.5= 2=
0/ Ra 12 /R b 1/R a 1/R b1/ 1000
1/ Ra 12/R b 1/R a 1 /R b1/1000
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12/ R b 3000 =4 1000 1/R a 1/R b0.001
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1/R a 12/ R b 3000 =4 1000 1/R a 1 /R b0.001
A3:6 A3:7
The following derivation uses these two equations to calculate Ra and Rb. 12 /R b 1.5 = =0.375 A3:8 1/R a 1 /R b0.001 4 1/ Ra 12 / R b 2 = =0.5 A3:9 1/ R a 1/R b 0.001 4 1/ Ra =0.5-0.375=0.125 A3:10 1 /R a 1/R b0.001 Ra 0.375 1 = =0.25 A3:11 Rb 12 0.125 1/R a 1 = =0.125 A3:12 1/R a 1 /R b0.001 1R a / R b0.001 R a 10.250.001R a =1 / 0.125=8 A3:13 Ra =1000 8-1.25=6.75k A3 :14 R b =R a /0.25=6750 / 0.25=27k A3:15
Table A1 contains the final values calculated for the scaler circuit. Table A1: Calculated resistor values for the control input scaler. Ra Rb Rp Rf Rn 6.75 k 27 k 1 k 3 k 1 k
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Appendix B: Calculating a Best-Fit Line
To estimate a line with equation y= using the least squares method, take n number of data points for both x and y, and calculate the following values: SX =x 1x2 ...x n SY =y 1y 2...y n SXX =x 2x 2...x 2 1 2 n SXY =x 1 y 1x 2 y 2 ...x n y n n SXY -SX SY . The slope can be estimated by = n SXX-SX SX The intercept alpha can be estimated by = S Y- S X . n
A consequence of this estimate is that the regression line will always pass through S S the "center": , = X , Y . x y n n MATLAB and Microsoft Excel were used to make these calculations.
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