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...5 Homework - Solutions 6.13 1) Draw the truth table for output (Q+) in terms of input J and K. 2) Since we are using a D flip-flop, use the excitation table to find the value of D for each input combination. 3) Find the logic equation for D in terms of inputs J, K and the present state Q. 4) Implement the logic to get a JK flip-flop using a D flip-flop. 6.16 Page 1 of 12 Homework 5 - Solutions 6.17 T 0 0 1 1 Q 0 1 0 1 Q+ 0 1 1 0 D 0 1 1 0 Q 0 0 1 1 Q+ D 0 0 1 1 0 0 1 1...
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5 Homework - Solutions 6.13 1) Draw the truth table for output (Q+) in terms of input J and K. 2) Since we are using a D flip-flop, use the excitation table to find the value of D for each input combination. 3) Find the logic equation for D in terms of inputs J, K and the present state Q. 4) Implement the logic to get a JK flip-flop using a D flip-flop. 6.16 Page 1 of 12 Homework 5 - Solutions 6.17 T 0 0 1 1 Q 0 1 0 1 Q+ 0 1 1 0 D 0 1 1 0 Q 0 0 1 1 Q+ D 0 0 1 1 0 0 1 1 Excitation table for D flipflop Q+ = Q T Thus, D = Q T 6.19 Page 2 of 12 Homework 5 - Solutions 6.21 Placing two synchronizers in series helps reduce the probability of synchronizer failure because it is in effect providing the system two clock periods to stabilize instead of one. This effect is very similar to increasing the clock period of the receiver so that it has more time to decide. Even though it seems logical to put more synchronizers in series to even further reduce the probability of synchronizer failure, this approach has the severe penalty in that each synchronizer adds another full clock period before the input can be used. Page 3 of 12 Homework 5 - Solutions II Show how to implement a J-K flip-flop starting with a T flip-flop. Page 4 of 12 Homework 5 - Solutions 7.2 We begin designing the three bit counter by first drawing the state transition graph, then the state transition table. Since state 101 is not part of the sequence, we need to make sure that it has a transition out to a state that is part of the sequence. Note: Your state diagram depends on where you add the additional state "101". State diagram: State transition table: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A+ 0 0 1 0 1 1 0 1 B+ 1 0 1 0 1 1 1 0 C+ 0 0 1 1 0 0 1 0 Page 5 of 12 Homework 5 - Solutions III C.6 (Implementation of the above counter using T flipflops) Derive the flip inputs flop TA, TB, TC using the excitation table for a T flip flop. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A+ B+ C+ TA TB TC 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 1 1 1 Following is the implementation using T flip flops. The flip-flops store A, B, C values respectively. (Continued on next page..) Page 6 of 12 Homework 5 - Solutions (C.6 Continued...) Page 7 of 12 Homework 5 - Solutions 7.20 S1+ = N1 = [( S0 S1 ) D]C + S1 C S0 + = N 0 = C S0 S1 S0 D C 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 S1+ 0 0 0 1 0 1 0 0 1 1 1 0 1 0 1 1 S0+ 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 Page 8 of 12 Homework 5 - Solutions 7.24 The state machine will have eight states as shown below. 1 State S00 indicates that an input 00 has been read and the output is 1. All the states have been named in a similar fashion. Note that the state diagram is NOT Complete. For clarity, only a few transitions are shown in the figure. Page 9 of 12 Homework 5 - Solutions 7.26 For this question, you have to assume that (Z1, Z2) = (1, 0) if present value of N is greater than the previous input. (Otherwise, it is impossible to realize the state machine in five states). Page 10 of 12 Homework 5 - Solutions 7.27 The Moore machine has six states for the following cases Number of Number of State 0's 1's Odd Odd S0 Even Odd S1 Odd 0 S2 Even 0 S3 Odd Even > 0 S4 Even Even > 0 S5 (">" indicates the "greater than" symbol) Output 0 0 0 0 1 0 Page 11 of 12 Homework 5 - Solutions V A serial-in, serial-out shift register: A parallel-in, parallel-out shift register: Since the question does not specify the nature of outputs(serial or parallel) , it is correct even if you implement a serial-in, parallel-out shift register of the following figure: Page 12 of 12
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