of Review Chapters 2 and 5
User portion of execution time is main performance metric of interest rst.
sec = instr cycles secs prog prog instr cycle = IC CPI CT
IC measures algorithmic complexity (when instruction mix is included it is better). It is improved by algorithmic changes.
CT is the cycle time of the machine at it is technology dependent for a xed architecture. Note however we have seen how it is important to decide at a digital level exactly how much combinational logic is to be allowed to settle within a cycle. CPI is address by architectural changes. Mainly attempting to do more instructions per cycle is the theme of later chapters.
Performance Metrics
for a xed program, 1 performance = time so larger numbers mean better performance. Work per unit time metrics must be used with care. MIPS { what is an instruction? MFLOPS { better but there is still variation across mutltiplication, addition and division times.
Algorithm changes can change instruction count and distribution so looking at MFLOPS for two di erent programs with substantially di erent instruction statistics for the same problem can be very misleading. For most problems of interest, when the operation count is reduced by exploiting the structure of the problem the MFLOPS metric goes down while time also goes down. workload characterization is crucial when benchmarking and existing system or predicting a future system's behavior. care must be taken when averaging performance gures across programs to compare two di erent machines.
Control of Datapath
Instruction set architecture { determines the function of the instructions when applied to the programmer-visible state of the machine and their sidee ects under exceptions machine instructions - encoding of information from ISA in terms of operand structure classes Problem for Chapter 5 { given state storage (Registers, Memory), and combinational devices (ALU, MUX etc.), generate control signals to set the path of the data from some state location through combinational devices to the destination state locations that are updated and avoid incorrect update of other state elements.
Single Cycle Implementation
Entire e ect of the intstruction is determined and the update prepared within one cycle largest amount of HW due to need to replicate function maintain to combinational form largest combination delay determines cycle time static instruction choice determines cycle time for all codes even those that do not use long instructions.
To set control lines { for each instruction: determine data path from source to destination through combinational devices (and their functions) determine information in instruction and operands needed to determine the path determine the setting of control lines that guarantee this data path exists and performs the correct function in the combinational logic that is adjustable (e.g. ALU). determine the control signals that ensure invalid data present on various lines do not update the state
Note 2,3, and 4 yield the truth table entries for the controller combinational logic. Synthesize the controller combinational logic.
Multicycle Implementation
Less HW since multiple use of same units is possible (at di erent times of course) variable instruction timings result so dynamic instruction counts for a particular program determine execution time. cycle time is determined by the time it takes to do basic combination operations, e.g., one pass through an ALU
To desgin the FSM for the controller: separate each instruction into a sequence of steps that satisfy the cycle time and HW contraints. determine the value of the control lines to perform the operations corresponding to eac...