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66 Pages

### setrev2and5

Course: CS 4101, Fall 2008
School: S.F. State
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Word Count: 21543

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of Review Chapters 2 and 5 User portion of execution time is main performance metric of interest rst. sec = instr cycles secs prog prog instr cycle = IC CPI CT IC measures algorithmic complexity (when instruction mix is included it is better). It is improved by algorithmic changes. CT is the cycle time of the machine at it is technology dependent for a xed architecture. Note however we have seen how it is...

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of Review Chapters 2 and 5 User portion of execution time is main performance metric of interest rst. sec = instr cycles secs prog prog instr cycle = IC CPI CT IC measures algorithmic complexity (when instruction mix is included it is better). It is improved by algorithmic changes. CT is the cycle time of the machine at it is technology dependent for a xed architecture. Note however we have seen how it is important to decide at a digital level exactly how much combinational logic is to be allowed to settle within a cycle. CPI is address by architectural changes. Mainly attempting to do more instructions per cycle is the theme of later chapters. Performance Metrics for a xed program, 1 performance = time so larger numbers mean better performance. Work per unit time metrics must be used with care. MIPS { what is an instruction? MFLOPS { better but there is still variation across mutltiplication, addition and division times. Algorithm changes can change instruction count and distribution so looking at MFLOPS for two di erent programs with substantially di erent instruction statistics for the same problem can be very misleading. For most problems of interest, when the operation count is reduced by exploiting the structure of the problem the MFLOPS metric goes down while time also goes down. workload characterization is crucial when benchmarking and existing system or predicting a future system's behavior. care must be taken when averaging performance gures across programs to compare two di erent machines. Control of Datapath Instruction set architecture { determines the function of the instructions when applied to the programmer-visible state of the machine and their sidee ects under exceptions machine instructions - encoding of information from ISA in terms of operand structure classes Problem for Chapter 5 { given state storage (Registers, Memory), and combinational devices (ALU, MUX etc.), generate control signals to set the path of the data from some state location through combinational devices to the destination state locations that are updated and avoid incorrect update of other state elements. Single Cycle Implementation Entire e ect of the intstruction is determined and the update prepared within one cycle largest amount of HW due to need to replicate function maintain to combinational form largest combination delay determines cycle time static instruction choice determines cycle time for all codes even those that do not use long instructions. To set control lines { for each instruction: determine data path from source to destination through combinational devices (and their functions) determine information in instruction and operands needed to determine the path determine the setting of control lines that guarantee this data path exists and performs the correct function in the combinational logic that is adjustable (e.g. ALU). determine the control signals that ensure invalid data present on various lines do not update the state Note 2,3, and 4 yield the truth table entries for the controller combinational logic. Synthesize the controller combinational logic. Multicycle Implementation Less HW since multiple use of same units is possible (at di erent times of course) variable instruction timings result so dynamic instruction counts for a particular program determine execution time. cycle time is determined by the time it takes to do basic combination operations, e.g., one pass through an ALU To desgin the FSM for the controller: separate each instruction into a sequence of steps that satisfy the cycle time and HW contraints. determine the value of the control lines to perform the operations corresponding to eac...

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FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Pipelined ControlUse essentially the same control signals as the single cycle implementation. As before, no control needed for IF and ID stages of pipe, i.e., control does not a ect execution until the EX stage. The opcode is available after the IF
S.F. State - CS - 4101
Pipelined ControlUse essentially the same control signals as the single cycle implementation. As before, no control needed for IF and ID stages of pipe, i.e., control does not a ect execution until the EX stage. The opcode is available after the IF
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Forwarding for StoresStore requires data in the MEM phase for correct execution. Forwarding of data from an instruction that produces data in the EX phase, e.g., R type can be handled by extending the forwarding decision in the EX phase discussed ea
S.F. State - CS - 4101
Forwarding for StoresStore requires data in the MEM phase for correct execution. Forwarding of data from an instruction that produces data in the EX phase, e.g., R type can be handled by extending the forwarding decision in the EX phase discussed ea
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Branch HazardsBranch target address is available after the MEM phase in current pipeline 3 instructions that follow BEQ can be started in the pipe before the target is known predicting branch not taken requires no new PC related HW if the branch is
S.F. State - CS - 4101
Branch HazardsBranch target address is available after the MEM phase in current pipeline 3 instructions that follow BEQ can be started in the pipe before the target is known predicting branch not taken requires no new PC related HW if the branch is
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Exceptions in a PipelineConsider arithmetic over ow exception causing immediate exception handling (like Chapter 5) Occurs when o ending instruction is in EX stage set PC to exception handler ush all instructions in earlier pipeline stages (IF and I
S.F. State - CS - 4101
Exceptions in a PipelineConsider arithmetic over ow exception causing immediate exception handling (like Chapter 5) Occurs when o ending instruction is in EX stage set PC to exception handler ush all instructions in earlier pipeline stages (IF and I
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Memory Hierarchyideally, we want every location in memory whether it contains data or code to be available within a single cycle large and fast memory is prohibitively expensive Di erent technology implies di erent cost per bit and therefore di eren
S.F. State - CS - 4101
Memory Hierarchyideally, we want every location in memory whether it contains data or code to be available within a single cycle large and fast memory is prohibitively expensive Di erent technology implies di erent cost per bit and therefore di eren
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Spatial Localityone word lines do not exploit spatial locality for typical computations spatial locality implies if address A is needed then A + will be needed soon. Caches attempt to exploit spatial locality by using multiple word cache lines. when
S.F. State - CS - 4101
Spatial Localityone word lines do not exploit spatial locality for typical computations spatial locality implies if address A is needed then A + will be needed soon. Caches attempt to exploit spatial locality by using multiple word cache lines. when
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
see pp. 564 { 568 for a discussion of cache performance formulas improving hardware design can reduce hit time and the miss penalty increasing line size (within reason) can decrease the miss rate cold-start misses are unavoidable capacity misses are
S.F. State - CS - 4101
see pp. 564 { 568 for a discussion of cache performance formulas improving hardware design can reduce hit time and the miss penalty increasing line size (within reason) can decrease the miss rate cold-start misses are unavoidable capacity misses are
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
WRITE BACK for WRITE HITSXYXX XYYXYXYX Yafter read Xafter write xafter displacement of xWRITE THROUGH for WRITE HITSXXX XXXY X YX Yafter read X write bufferingafter write xWRITE BACK WITH WRITE ALLOCATE
S.F. State - CS - 4101
WRITE BACK for WRITE HITSXYXX XYYXYXYX Yafter read Xafter write xafter displacement of xWRITE THROUGH for WRITE HITSXXX XXXY X YX Yafter read X write bufferingafter write xWRITE BACK WITH WRITE ALLOCATE
FSU - CS - 4101
WRITE BACK for WRITE HITSXYXX XYYXYXYX Yafter read Xafter write xafter displacement of xWRITE THROUGH for WRITE HITSXXX XXXY X YX Yafter read X write bufferingafter write xWRITE BACK WITH WRITE ALLOCATE
S.F. State - CS - 4101
WRITE BACK for WRITE HITSXYXX XYYXYXYX Yafter read Xafter write xafter displacement of xWRITE THROUGH for WRITE HITSXXX XXXY X YX Yafter read X write bufferingafter write xWRITE BACK WITH WRITE ALLOCATE
FSU - CS - 4101
Virtual Memorylast level of the hierarchy program works in a \virtual&quot; address space the physical address of data is determined dynamically at runtime a particular virtual address may correspond to many di erent physical addresses over the lifetime
S.F. State - CS - 4101
Virtual Memorylast level of the hierarchy program works in a \virtual&quot; address space the physical address of data is determined dynamically at runtime a particular virtual address may correspond to many di erent physical addresses over the lifetime
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
special caches called Translation lookaside bu ers are used to reduce the time it takes to perform virtual to physical translation each entry in the TLB contains a tag (from the virtual page number) and some information from the page table entry, e.g
S.F. State - CS - 4101
special caches called Translation lookaside bu ers are used to reduce the time it takes to perform virtual to physical translation each entry in the TLB contains a tag (from the virtual page number) and some information from the page table entry, e.g
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Fast Address Translationneed virtual to physical address translation to work at a rate consistent with pipeline three typical approaches:{ extra pipeline stages with a physicallyindexed and tagged cache{ virtually addressed cache { virtually in
S.F. State - CS - 4101
Fast Address Translationneed virtual to physical address translation to work at a rate consistent with pipeline three typical approaches:{ extra pipeline stages with a physicallyindexed and tagged cache{ virtually addressed cache { virtually in
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
speed of components{ CPU speed increasing rapidly (50% peryear){ DRAM spead increasing (10% per year) { disk speed increasing (4 to 6 % per year) { I/O is crucial but lagging in improvementafter n years 0 1 2 5 10CPU time 90 60 40 12 1I/O
S.F. State - CS - 4101
speed of components{ CPU speed increasing rapidly (50% peryear){ DRAM spead increasing (10% per year) { disk speed increasing (4 to 6 % per year) { I/O is crucial but lagging in improvementafter n years 0 1 2 5 10CPU time 90 60 40 12 1I/O
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
OS Involvement in I/OMultiprogramming scenarios must be coordinated by OS context switches due to interrupts or page faults require OS complicated low level control of I/O devices easiest to handle in OSsupports three main activities for user:{
S.F. State - CS - 4101
OS Involvement in I/OMultiprogramming scenarios must be coordinated by OS context switches due to interrupts or page faults require OS complicated low level control of I/O devices easiest to handle in OSsupports three main activities for user:{
FSU - CS - 4101
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S.F. State - CS - 4101
( F I0 F @ VrhUI I ( @ G0&amp; d fr92F I G0 rYX B6 qPG #b I di p i D0 &amp; d 9ex f( C I C@ 6 &amp; 64 ( C 6 &amp;II u6 U&amp; 6 q7rqPG QEt&amp;p I8@ 'R2 6 4 F( 2 %44 I( C P'!QfPD0 6 f( I % diI40 % I 7DX74 u VFF (&amp; % )99@ #FIxG( rywv0(sI(C 6 YtfrqPG
FSU - CS - 4101
Why Parallelism/High-performance?High performance is always a relative term. Algorithmic ambition vs. A ordable systems is the main tradeo . Need for larger problems, e.g., more points in a discretization of a contiuous model { improves delity to gi
S.F. State - CS - 4101
Why Parallelism/High-performance?High performance is always a relative term. Algorithmic ambition vs. A ordable systems is the main tradeo . Need for larger problems, e.g., more points in a discretization of a contiuous model { improves delity to gi
FSU - CS - 4101
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S.F. State - CS - 4101
x 'rdeE'Y r W G DQ U f I G Ib'gRa @` zY nU )Y W r5Ude{Rc~d bTR~d }U E`YG rU i WQ i D x DQ Y ` I a I tQ I U i Df I d I t U Q W wr rPlv sv@pgH D u vY D IH |d Y D IE W f WY ` d r `D U I Q W ix Ex I i W f UQ H Q I E Q Q U I I pjoPH pU nml'kjd RI'0h
FSU - CS - 4101
There are two basic classes of network Direct (static) Indirect (dynamic)Interconnection NetworksTraditionally direct networks are used for distributed memory machines and indirect networks are used for shared memory. THERE IS NO REASON FOR THIS
S.F. State - CS - 4101
There are two basic classes of network Direct (static) Indirect (dynamic)Interconnection NetworksTraditionally direct networks are used for distributed memory machines and indirect networks are used for shared memory. THERE IS NO REASON FOR THIS
FSU - CS - 4101
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