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Course: CS 4101, Fall 2008School: S.F. State
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Word Count: 1361
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FSU - CS - 4101
Branch HazardsBranch target address is available after the MEM phase in current pipeline 3 instructions that follow BEQ can be started in the pipe before the target is known predicting branch not taken requires no new PC related HW if the branch is
S.F. State - CS - 4101
Branch HazardsBranch target address is available after the MEM phase in current pipeline 3 instructions that follow BEQ can be started in the pipe before the target is known predicting branch not taken requires no new PC related HW if the branch is
FSU - CS - 4101
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S.F. State - CS - 4101
p (3 4a9 (9 hxc 3 m 1 "B 3 %HUP 3& f4( 9 3 "BG G q ( " q @fHe824@E$ ( 3& 64( onD B 5 3GG 3 $ " `CvUE67f$ 31 ( #%)9q T( 3 FPm 799 " qB ( $ c ( 9 " xrpi%d4xHB3& 64(" 9 3& mB W X W 3f&4( HB CB y sX 64( 3 Hp( 93#16)(h9 5" jd g e 3& " klX %7
FSU - CS - 4101
Exceptions in a PipelineConsider arithmetic over ow exception causing immediate exception handling (like Chapter 5) Occurs when o ending instruction is in EX stage set PC to exception handler ush all instructions in earlier pipeline stages (IF and I
S.F. State - CS - 4101
Exceptions in a PipelineConsider arithmetic over ow exception causing immediate exception handling (like Chapter 5) Occurs when o ending instruction is in EX stage set PC to exception handler ush all instructions in earlier pipeline stages (IF and I
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Memory Hierarchyideally, we want every location in memory whether it contains data or code to be available within a single cycle large and fast memory is prohibitively expensive Di erent technology implies di erent cost per bit and therefore di eren
S.F. State - CS - 4101
Memory Hierarchyideally, we want every location in memory whether it contains data or code to be available within a single cycle large and fast memory is prohibitively expensive Di erent technology implies di erent cost per bit and therefore di eren
FSU - CS - 4101
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S.F. State - CS - 4101
$ B 6! R $ b 7 6 R $ 7 & 7 $ ! WX7 QS& SyB 8C$ Ce8avb 'Y9P7 T4#&CB I)f 4iEW)ge7 XY7! 5 21#"C)B %A%gG ($ 7 31r (E6VG$ V ( !w& $r6&V $ ! b 6 $ w $ 3 w & $ V G 3 7 b & u 3( R b V G 'i9CSUXU%AWCIvcSQ0)& 4b & gA4b b Ce7 RB $ b CevWv)W#GS)7 R $7b1b ( &
FSU - CS - 4101
Spatial Localityone word lines do not exploit spatial locality for typical computations spatial locality implies if address A is needed then A + will be needed soon. Caches attempt to exploit spatial locality by using multiple word cache lines. when
S.F. State - CS - 4101
Spatial Localityone word lines do not exploit spatial locality for typical computations spatial locality implies if address A is needed then A + will be needed soon. Caches attempt to exploit spatial locality by using multiple word cache lines. when
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
see pp. 564 { 568 for a discussion of cache performance formulas improving hardware design can reduce hit time and the miss penalty increasing line size (within reason) can decrease the miss rate cold-start misses are unavoidable capacity misses are
S.F. State - CS - 4101
see pp. 564 { 568 for a discussion of cache performance formulas improving hardware design can reduce hit time and the miss penalty increasing line size (within reason) can decrease the miss rate cold-start misses are unavoidable capacity misses are
FSU - CS - 4101
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S.F. State - CS - 4101
i c$ R$ c !$ ' pdSve`V21!# ! ' 5 $ ) $ 9 1bqY8$ tYabQ fcT 5$ ' ) # qIP8abQi #')# btqabQ 5! G8'`g&$ B fHt6t' c '$ 5 c! g`y g&$ B @fc 9 g&$ B ' ) WG65$ I! B! QV!5 $ c ! 5 c ! 64e`I$ g`y `g&$ B fHt6t' c '$
FSU - CS - 4101
WRITE BACK for WRITE HITSXYXX XYYXYXYX Yafter read Xafter write xafter displacement of xWRITE THROUGH for WRITE HITSXXX XXXY X YX Yafter read X write bufferingafter write xWRITE BACK WITH WRITE ALLOCATE
S.F. State - CS - 4101
WRITE BACK for WRITE HITSXYXX XYYXYXYX Yafter read Xafter write xafter displacement of xWRITE THROUGH for WRITE HITSXXX XXXY X YX Yafter read X write bufferingafter write xWRITE BACK WITH WRITE ALLOCATE
FSU - CS - 4101
WRITE BACK for WRITE HITSXYXX XYYXYXYX Yafter read Xafter write xafter displacement of xWRITE THROUGH for WRITE HITSXXX XXXY X YX Yafter read X write bufferingafter write xWRITE BACK WITH WRITE ALLOCATE
S.F. State - CS - 4101
WRITE BACK for WRITE HITSXYXX XYYXYXYX Yafter read Xafter write xafter displacement of xWRITE THROUGH for WRITE HITSXXX XXXY X YX Yafter read X write bufferingafter write xWRITE BACK WITH WRITE ALLOCATE
FSU - CS - 4101
Virtual Memorylast level of the hierarchy program works in a \virtual" address space the physical address of data is determined dynamically at runtime a particular virtual address may correspond to many di erent physical addresses over the lifetime
S.F. State - CS - 4101
Virtual Memorylast level of the hierarchy program works in a \virtual" address space the physical address of data is determined dynamically at runtime a particular virtual address may correspond to many di erent physical addresses over the lifetime
FSU - CS - 4101
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S.F. State - CS - 4101
T "B Q 4B vCUPDI B(0 @234 $ ( $ $ (B i i HqHpU2" G " T ! " E9 $ G 7 v2#x%wvI"6 34(T 9 & ( 69 `r! GY HU" T(7 u8& 4 q& "& Y ( B ( 9 @P3ii Y 4 I $ (BB 4 t31HpX5HE$ $ ( B i i " ! " e & B9 0 B "! e E9 & B " qPvtDUs8@D#UyffI( i(Y 2`9 TB (
FSU - CS - 4101
special caches called Translation lookaside bu ers are used to reduce the time it takes to perform virtual to physical translation each entry in the TLB contains a tag (from the virtual page number) and some information from the page table entry, e.g
S.F. State - CS - 4101
special caches called Translation lookaside bu ers are used to reduce the time it takes to perform virtual to physical translation each entry in the TLB contains a tag (from the virtual page number) and some information from the page table entry, e.g
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Fast Address Translationneed virtual to physical address translation to work at a rate consistent with pipeline three typical approaches:{ extra pipeline stages with a physicallyindexed and tagged cache{ virtually addressed cache { virtually in
S.F. State - CS - 4101
Fast Address Translationneed virtual to physical address translation to work at a rate consistent with pipeline three typical approaches:{ extra pipeline stages with a physicallyindexed and tagged cache{ virtually addressed cache { virtually in
FSU - CS - 4101
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S.F. State - CS - 4101
0HTA Vvu1T 2 0 A C A 4 R P H 2 ) 2 0 y 0 2 ) C A @ 864 D#V8 PC#1UTSDQ#G uIA !tIVp4 PCIBp53 x 0 H T A 2 0 R R 06 2 2 C A @ 864 Vvu1T !FcXW#uA PCIBp53 x 0HTA 20A 2) 20y02) Vvu1T !IIu8 uIA !tIVp4 PC#1bT1Y#G A i84 e cIVhR Vpr4q5p5G Q0 x CA 4RPH H R 0
FSU - CS - 4101
speed of components{ CPU speed increasing rapidly (50% peryear){ DRAM spead increasing (10% per year) { disk speed increasing (4 to 6 % per year) { I/O is crucial but lagging in improvementafter n years 0 1 2 5 10CPU time 90 60 40 12 1I/O
S.F. State - CS - 4101
speed of components{ CPU speed increasing rapidly (50% peryear){ DRAM spead increasing (10% per year) { disk speed increasing (4 to 6 % per year) { I/O is crucial but lagging in improvementafter n years 0 1 2 5 10CPU time 90 60 40 12 1I/O
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
OS Involvement in I/OMultiprogramming scenarios must be coordinated by OS context switches due to interrupts or page faults require OS complicated low level control of I/O devices easiest to handle in OSsupports three main activities for user:{
S.F. State - CS - 4101
OS Involvement in I/OMultiprogramming scenarios must be coordinated by OS context switches due to interrupts or page faults require OS complicated low level control of I/O devices easiest to handle in OSsupports three main activities for user:{
FSU - CS - 4101
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S.F. State - CS - 4101
( F I0 F @ VrhUI I ( @ G0& d fr92F I G0 rYX B6 qPG #b I di p i D0 & d 9ex f( C I C@ 6 & 64 ( C 6 &II u6 U& 6 q7rqPG QEt&p I8@ 'R2 6 4 F( 2 %44 I( C P'!QfPD0 6 f( I % diI40 % I 7DX74 u VFF (& % )99@ #FIxG( rywv0(sI(C 6 YtfrqPG
FSU - CS - 4101
Why Parallelism/High-performance?High performance is always a relative term. Algorithmic ambition vs. A ordable systems is the main tradeo . Need for larger problems, e.g., more points in a discretization of a contiuous model { improves delity to gi
S.F. State - CS - 4101
Why Parallelism/High-performance?High performance is always a relative term. Algorithmic ambition vs. A ordable systems is the main tradeo . Need for larger problems, e.g., more points in a discretization of a contiuous model { improves delity to gi
FSU - CS - 4101
x 'rdeE'Y r W G DQ U f I G Ib'gRa @` zY nU )Y W r5Ude{Rc~d bTR~d }U E`YG rU i WQ i D x DQ Y ` I a I tQ I U i Df I d I t U Q W wr rPlv sv@pgH D u vY D IH |d Y D IE W f WY ` d r `D U I Q W ix Ex I i W f UQ H Q I E Q Q U I I pjoPH pU nml'kjd RI'0h
S.F. State - CS - 4101
x 'rdeE'Y r W G DQ U f I G Ib'gRa @` zY nU )Y W r5Ude{Rc~d bTR~d }U E`YG rU i WQ i D x DQ Y ` I a I tQ I U i Df I d I t U Q W wr rPlv sv@pgH D u vY D IH |d Y D IE W f WY ` d r `D U I Q W ix Ex I i W f UQ H Q I E Q Q U I I pjoPH pU nml'kjd RI'0h
FSU - CS - 4101
There are two basic classes of network Direct (static) Indirect (dynamic)Interconnection NetworksTraditionally direct networks are used for distributed memory machines and indirect networks are used for shared memory. THERE IS NO REASON FOR THIS
S.F. State - CS - 4101
There are two basic classes of network Direct (static) Indirect (dynamic)Interconnection NetworksTraditionally direct networks are used for distributed memory machines and indirect networks are used for shared memory. THERE IS NO REASON FOR THIS
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Control, Synchronization, SchedulingThree main activities:{ scheduling { deciding what is done where,i.e., assigning speci c pieces of work to speci c processors{ synchronization { deciding when thingsare done, i.e., making sure data that is
S.F. State - CS - 4101
Control, Synchronization, SchedulingThree main activities:{ scheduling { deciding what is done where,i.e., assigning speci c pieces of work to speci c processors{ synchronization { deciding when thingsare done, i.e., making sure data that is
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Spring 2000 CDA 4101 Homework 1Due date: January 26, 2000.ReadingChapters 1,2, and 5. Review Chapters 3, 4, digital design notes and text appendices as needed for prerequisites.Problem 1. Graded based on e ortSuppose you are given a JK ip- op
S.F. State - CS - 4101
Spring 2000 CDA 4101 Homework 1Due date: January 26, 2000.ReadingChapters 1,2, and 5. Review Chapters 3, 4, digital design notes and text appendices as needed for prerequisites.Problem 1. Graded based on e ortSuppose you are given a JK ip- op
FSU - CS - 4101
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S.F. State - CS - 4101
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FSU - CS - 4101
Spring 2000 CDA 4101 Homework 2Due date: February 2, 2000 by the end of class.ReadingChapters 5 and 6.Problem Set 1. Graded based on e ortTextbook problems 5.5,5.15, and 5.24. For problems 5.5.and 5.15 please make sure to include descriptions