Topics
Advanced Fundamentals in Computer
Organization
Introduction to VHDL
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Basic Building Blocks (1)
Register
Data In (N bits)
N
Register
N
Data Out (N bits)
Load
Output Enable (we have Tri-state outputs)
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Basic Building Blocks (2)
Shift Register
Data In N Load Shift Register N
Data Out
Output Enable
Shift Controls (left/right/no shift) 3
Basic Building Blocks (4)
Arithmetic-Logic Unit
N A B
N
Operation
ALU N
Keep in mind: The ALU is a combinational circuit.
Flags Result (carry out, overflow, etc.)
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Buses
A shared collection of wires for exchanging data, with some defined rules
Data Lines (two-way) N M
Address Lines (one-way)
Control Lines (mix of 1 and 2-way lines)
C
Rule 1: Only one device can write to a bus at any time Rule 2: Multiple devices can read the bus at any time
Rule 3: There is usually a bus protocol that is followed strictly by all devices sharing the bus
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3 Registers Sharing a Bus
N
M
C Only one of these OE's can be true at once Only one can
OE1
OE2
OE3
Register 1
Register 2
Register 3
OE's and LOAD's generally determined by the control lines
write to the data LOAD1 line
LOAD2
LOAD3 Several of these can be true at once for input
To write, OE must be enabled. To read, LOAD must be enabled.
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Register-to-Register Data Transfer
Register 1 Register 3
N
M
C
OE1
OE2
OE3
Register 1
Register 2
Register 3
LOAD1
LOAD2
LOAD3
Only one can write to the data line, but more than one registers can receive inputs at the same time 7
Buses & Registers to RAM
Memory Address Register (store address here) M A R
Request (Chip Select)
Read/Write
Memory Control Signals
Wait
Random Access Memory M B R
Slow RAMs usually ask Processor to wait
Memory Buffer Register (exchange data here) 8
I want to build a computer!
Basic Idea #1: The Stored Program Computer Concept
This is an instruction-controlled digital system with a memory A sequence of instructions are stored in memory This set of instructions constitute the program that defines the machine's behavior The same memory also holds the data needed to execute the program
The same memory also holds the outputs produced by the program, as well as any intermediate results The memory is large (ideally, infinite)
Note: This is not the only way to build a computer, but is the most common one.
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The Cycle of Life
Basic Idea #2: The Instruction Cycle
The processor executes the following "infinite loop" forever: Step 1. Fetch the next instruction from memory to a register The register is usually called the instruction register (IR). The address of the next instruction is usually stored in a register called the program counter (PC). So, Fetch does the following: 1) get the instruction address from PC; 2) read the instruction from the memory; 3) transfer the instruction to IR. Step 2. Decode the instruction
Step 3. Fetch any operands needed Step 4. Execute the instruction Step 5. Do internal housekeeping, and Go to Step 1 One important chore is to change the address in the PC to point to the next instruction.
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Structure of a Computer
Address
Central Processing Unit (CPU) The Processor consists of two major parts:
Processor
Read/Write
Data
Memory System
Control Signals
Control
Data Inputs
Datapath
In its simplest form, a computer consists of a processor (CPU) and a memory system.
The Datapath Unit, also called the execution unit, consisting of Registers for temporary data storage and functional unit to perform operation on the data. Main parts: Registers, Shifter, ALU, Buses. The Control Unit, also called the instruction unit. It provides instruction as to what operation to perform
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Put Them Together!
Single Bus Design
The Datapath Unit
Mem ory Addre ss Bus
BUS
Mem ory Da ta Bus
M A R
A P C I R A C M B R
B
ALU
The BUS is like a highway for transferring data from one point to any other point Program Counter (Holds address of NEXT instruction)
Accumulator Involved in most instructions Instruction Register (Holds the fetched instruction)
Note that this one has two outputs 12
Register Transfer Operations
Single Bus Design
BUS
Mem ory Addre ss Bus Mem ory Da ta Bus
M A R
A P C I R A C M B R
B
Register transfer operations:
PC BUS IR BUS AC BUS MBR BUS ALU Result BUS
BUS PC BUS IR BUS AC BUS MBR BUS ALU B BUS MAR
AC ALU A (hardwired)
They all share one bus.
Note, the BUS is treated just like a register
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More Realistic Datapath Unit
Three Bus Design -- Supports more parallelism
Address Bus
Mem ory Addre ss Bus
Result Bus A
M A R
P C
I R
A C B Memory Bus
M B R
Mem ory Da ta Bus
Single bus replaced by three busses:
Memory Bus (MBUS) Result Bus (RBUS) Address Bus (ABUS)
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Add Memory
RBUS MBUS AC A B
Memory Address
ALU S
Memory N bits wide 2M words
MAR ABUS PC MBUS
IR
We simplified our datapath further by assuming that MBR is inside the memory system itself and MBUS has two branches.
Every device in this diagram has control signals that must be operated. 15
Add Control
RBUS
The control unit is a finite state machine (FSM). Every bit of the Instruction Register (IR), every other register's OE and LOAD signals, every control input and flag output of the ALU, and every memory control signal is either an input or an output of the control unit. (Shown in red)
MBUS AC A B
Memory Address
FSM
Opcode
ALU S
Memory N bits wide 2M words
MAR ABUS PC MBUS Control Flow Data Flow
IR
3 for ALU, 1 each for, MAR, and PC. Reality Note #1:The control unit FSM is huge compared to the FSM examples that we've seen thus far!!
Reality Note #2: The diagram above is extremely simplified compared to a real processor
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How does it work? (1)
Let's trace an instruction: AC AC + Mem<address>
1. Instruction Fetch: Move PC to MAR Initiate a memory read sequence Move data from memory to IR
2. Instruction Decode: Opcode bits of IR are input to control FSM Rest of IR bits encode the operand address (see Fig 11.4)
Store Path AC A FSM
Opcode
Load Path
B
ALU
S
Memory Address
Memory N bits wide 2M words
MAR PC
IR
Instruction Path
OPCODE
OPERAND SPECIFIER
3. Operand Fetch: Move operand address from IR to MAR Initiate a memory read sequence
Instruction Format
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How does it work? (2)
Let us trace an instruction: AC AC + Mem<address>
4. Instruction Execute: available Data on load path Move data to ALU input Configure ALU to perform ADD operation Move result S to AC
Store Path AC A FSM
Opcode
Load Path
B
ALU
S
Memory Address
Memory N bits wide 2M words
MAR PC
IR
Instruction Path
5. Housekeeping: Update PC to point at next instruction
OPCODE
OPERAND SPECIFIER
Instruction Format
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The Control Unit
What the Control unit is doing: Transfers data from one register to another Asserts appropriate control signals
We can think about the control unit most easily in terms of a series of register transfers and microoperations, using a programming-like notation Register transfer notation - A way to represent the detailed implementation of register transfer operations Micro-operations-detailed operations for each register transfer Notation.
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Register Transfer Notation
Register to Register moves Instruction fetch: PC MAR; Memory Read; Memory IR; -- move PC to MAR -- assert Memory READ signal -- load IR from Memory
Instruction Decode: IF IR<op code> = ADD_FROM_MEMORY THEN Operand fetch: IR<addr> MAR; Memory Read; Instruction Execution: Memory ALU B; AC ALU A; ALU ADD; Assert Control ALU S AC; Signal -- move operand addr to MAR -- assert Memory READ signal
-- gate Memory to ALU B -- gate AC to ALU A -- instruct ALU to perform ADD -- gate ALU result to AC
-- increment PC
Housekeeping: PC+1 PC;
Repeat the five steps !
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Micro-Operations
Instruction Fetch
Instruction fetch: PC ABUS; ABUS MAR; 1 Read/Write*; MBR MBUS; MBUS IR;
Instruction Decode: IF IR<OpCode> = LOAD_FROM_MEMORY THEN Operand fetch: IR<addr> MAR; 1 Read/Write*; Instruction Execution: MBR MBUS; MBUS ALU B; ALU PASS B; ALU Result RBUS; RBUS AC; Housekeeping: PC+1 PC; 21
Micro-operations
One register transfer operation may be several micro-operations Some operations are directly implemented by functional units:
e.g., ADD, Pass B, 0 PC, PC + 1 PC Some others require multiple control operations: e.g., PC MAR implemented as PC ABUS and ABUS MAR See page 588
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Interrupts, Resets
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Example Task
Read the output of the 4-bit data source every time the push button is pressed, and display the result.
4-bit Data Source
Computer (HC11 chip)
Display
Push Button
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One Method...
4-bit Data Source
START
Computer (HC11 chip) Display
Push Button
BUTTON PRESSED?
YES
NO
Why do we have this?
Software switch debouncing
1 ms delay
This style of computer input/output is called Polled I/O because we're constantly polling the pushbutton
BUTTON PRESSED?
NO
YES READ 4-BIT INPUT UPDATE DISPLAY 25
Is Polling Bad?
Eats up a lot of CPU cycles doing nothing! We're repeatedly checking the button Each time the button is pressed, we delay by 1 ms by going around in a loop, wasting time This is also called "busy wait" We could do better if only we could somehow grab the CPU's attention momentarily whenever the button is pressed! We could do even better if the 1 ms delay could be achieved without a delay loop!
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Introducing Interrupts
A mechanism to interrupt the CPU, i.e., steal it for a little while to service the interrupting device (a button in our example)
An interrupt is an unusual event that requires the CPU to stop normal
program and perform some service related to the unusual event. It can be external or internal. External interrupts can be generated by asserting an interrupt signal to CPU. Internal interrupts can be
hardware components in CPU such as timer, I/O interface function.
Interrupts can also be caused by software errors (overflow,
abnormal operations, ..)
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Why are Interrupts Important?
They allow multiple processes to run on a computer
They allow the CPU to be shared, especiall when I/O is busy, greatly extending its ability
Provide a graceful to exit an application when software errors occur.
Reminding CPU to perform routine tasks For example, the CPU can be doing something else when "waiting" for the button to be pressed
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Interrupt Method
Suppose that the computer is doing something...
useful or otherwise....
START
INITIALIZE
DO SOMETHING USEFUL
Key Pressed
4-bit Data Source
Computer (HC11 chip)
Display
Push Button
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Interrupt Method
The CPU is temporarily interrupted. An Interrupt Service Routine is entered START
Key Pressed READ THE 4-BIT INPUT UPDATE THE DISPLAY DO SOMETHING USEFUL START INTERRUPT SERVICE ROUTINE
INITIALIZE
RETURN FROM INTERRUPT
The CPU now resumes where it left off!
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Interrupts are Transparent
The program that was interrupted does not have a clue that it was interrupted!! Interrupt Service Routines need to leave registers untouched
Interrupt Service Routines need to be extremely short and quick
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Interrupt Sources
Interrupts can come from several sources
Hardware Sources External Pushbuttons Internal Timers I/O interface Serial Communication Systems ...
Software Sources SWI instruction-halt a program STOP-cause the system to halt
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Interrupt Priority
Different Sources can have different priorities
For example, sources requiring a more timely response get higher priority.
At 9600 bits/sec, the RS-232 port on your PC produces an interrupt about once every 2000 CPU cycles. The 68HC11 timer produces an interrupt once every 216 CPU cycles. The timer has higher priority in this case.
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Interrupts: Recap
What is an interrupt? A special event that requires the CPU to stop normal program execution and perform some service related to the event. E.g.: I/O completion, timer time-out, illegal opcodes, arithmetic overflow, divide-by-0 etc.
Functions of Interrupts: - Coordinating I/O activities and preventing CPU from being tied up - Providing a graceful way to exit from errors - Reminding the CPU to perform routine tasks
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Managing Interrupts
Interrupt Maskability: - Interrupts that can be ignored by the CPU are called maskable interrupts. A maskable interrupt must be enabled before it can interrupt the CPU. Masking can change priority. An interrupt is enabled by setting an enable flag. Interrupts that can't be ignored by the CPU are called non-maskable interrupts.
Interrupt priority: - The order in which the CPU will service interrupts when all of them occur (pending) at the same time. Why do we need to use masking and priority to manage interrupts ?
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