Network CSE398: Systems Design
Instructor: Dr. Liang Cheng Department of Computer Science and Engineering P.C. Rossin College of Engineering & Applied Science Lehigh University
March 30, 2005
Outline
Recap
Scaling a network processor
Examples of commercial network processors Design tradeoffs and consequences Summary and homework
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Augmented RISC Processor
Alchemy Semiconductor Inc. Au1000 chip
Instruction cache Data cache
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Embedded Processor Plus Coprocessors
AMCC (Applied Micro Circuits Co.) nP7510 chip
Six nP cores
Programming
Implicit parallelism
Coprocessors
Meter engine for SNMP's RMON
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Pipeline of Homogeneous Processors
Cisco Systems, Inc. Parallel eXpress Forwarding (PXF)
MAC classify Accounting & ICMP FIB & Netflow MPLS classify Access control CAR MLPPP WRED
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Pipeline of Heterogeneous Processors
EZchip Co.
TOPparse: header field extraction and classification TOPsearch: table lookup TOPresolve: queue management and forwarding TOPmodify: packet header and content modification
Onboard SRAM Interface to external DRAM
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Extensive and Diverse Processors
Hifn (IBM)
Embedded processor complex
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Homogeneous Parallel Processors plus Controller
Intel IXP1200
Embeddd RISC processor (StrongARM)
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
StrongARM Role (1)
(a) Single IXP1200 (b) Multiple IXP1200s
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
StrongARM Role (2)
Tasks
Bootstrapping Exception handling Higher-layer protocol processing Interactive debugging Diagnostics and logging Memory allocation User interface and/or interface to the GPP Control of packet processors Other administrative functions
Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/30/05
StrongARM Role (3)
StrongARM characteristics Reduced Instruction Set Computer (RISC) Thirty-two bit arithmetic
Configurable in two modes ?
Vector floating point provided via a coprocessor Byte addressable memory
Virtual memory support Single, uniform address space Includes memories and devices
Built-in serial port Facilities for a kernelized operating system
Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/30/05
Outline
Recap Examples of commercial network processors Design tradeoffs and consequences Summary and homework
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Low Development Cost vs. Performance
The fundamental economic motivation ASIC costs $1M to develop Network processor costs programmer time
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Programmability vs. Processing Speed
Programmable hardware is slower Flexibility costs...
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Speed vs. Functionality
Generic idea
Processor with most functionality is slowest Adding functionality to NP lowers its overall ``speed''
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Speed
Can be evaluated by
Packet rate Data rate Burst size CBR, VBR
Instructor: Dr. Liang Cheng
CSE398: Network Systems Rates Design
03/30/05
Per-Interface vs. Aggregate Rates
Per-interface rate important if
Physical connections form bottleneck System scales by having faster interfaces
Aggregate rate important if
Fabric forms bottleneck System scales by having more interfaces
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Lookaside Coprocessors vs. Flow-Through Coprocessors
Flow-through pipeline
Operates at wire speed Difficult to change
Lookaside
Modular and easy to change Invocation can be bottleneck
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Uniform Pipeline vs. Synchronized Pipeline
Uniform pipeline
Operates in lock-step like assembly line Each stage must finish in exactly the same time
Synchronized pipeline
Buffers allow computation at each stage to differ Synchronization expensive
Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/30/05
Explicit Parallelism vs. Cost and Programmability
Explicit parallelism
Hardware is less complex More difficult to program
Implicit parallelism
Easier to program Slightly lower performance
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Parallelism vs. Strict Packet Ordering
Increased parallelism
Improves performance Results in out-of-order packets
Strict packet ordering
Aids protocols such as TCP Can nullify use of parallelism
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Stateful Classification vs. High-Speed Parallel Classification
Static classification
Keeps no state Is the fastest
Dynamic classification
Keeps state Requires synchronization for updates
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
I/O Performance vs. Pin Count
Bus width
Increase to produce higher throughput Decrease to take fewer pins
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Programming Languages
A three-way tradeoff Can have two, but not three of
Ease of programming Functionality Performance
Instructor: Dr. Liang Cheng
CSE398: Network Systems Design
03/30/05
Multithreading: Throughp...