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Course Number: EECS 122, Fall 2003

College/University: Berkeley

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EE122 Socket Programming Project Report The nal design report is due on Thursday, May 5, 2005. Your report should include the following information: 1. A one page description of your implemented API. List the main functions with a list of their arguments and their return values. It might help to make sure the function names and parameter names are self-explanatory. In case names are not self-explanatory, include...

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Appendix B Interview SummaryInterviewee #1 Demographics Male 25 years old Single No kids Graduate Student Interviewee #2 Interviewee #3 Interviewee #4 Interviewee #5 Interviewee #6 Demographics Female 28 years old In a relationship No kids PhD Stud
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An online photo organization and retrieval systemwww.photocat.org Is213-photocat@sims.berkeley.eduCarrie Burgener carrie@simsScott Fisher sbfisher@simsAndrea Nelson andrea@sims Mike Wooldridge mikew@simsPresentation Overview Project
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Vern Group Assignment: Heuristic EvalHeuristic Evaluation of SIMS Alumni Network Project UI1. Reports:1, Heuristic:HELP, Severity:2 On the login page, the Sign Up Now! link should be highlighted to draw attention to itself as a link 2. Reports:1,
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ID 1 2 3# of ReportsHeuristic Severity 1 HELP 1 MATCH 2 CONSTDescription 2 On the login page, the "Sign Up Now!" link should be highlighted to draw attention to itself as a link 1 On the login page, the submit button really should be labelled "
Berkeley - EECS - 252
University of California College of Engineering Department of Electrical Engineering and Computer ScienceJ. M. Rabaey K. KeutzerTuTh2-3:30pmCS 252: Spring 00 Quiz 1Due Monday March 13 at 10am. Either at Reception of 231 Cory or by e-mail to ja
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Abbreviated Quiz1 Solution: 1. Explain the utility of each of the following DSP architectural features. Demonstrate with the aid of a simple specific example (described in pseudo-code). Circular Buffers o Automatic hardware mechanism does automatic p
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University of California College of Engineering Department of Electrical Engineering and Computer ScienceJ. M. Rabaey K. KeutzerTuTh2-3:30pmCS 252: Spring 00 Quiz 2Due Monday April 17 at 10am. Either at Reception of 231 Cory or by e-mail to ja
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UNIVERITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences NTU 247 B. E. Boser Homework 1 Due Thursday, January 18, 2007 NTU 247 Spring 2007Note: You need to show zoom-in plots of your filter response
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UNIVERITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences NTU 247 B. E. Boser Homework 2 Due Thursday, February 1, 2007 NTU 247 Spring 20071. Design a filter with the following response:s( s2 + 9.83
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UNIVERITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences NTU 247 B. E. Boser Homework 3 Due Monday, February 19, 2007 NTU 247 Spring 2007!1. A full-scale sine wave with frequency f x = 7MHz is inpu
Berkeley - EECS - 247
UNIVERITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences NTU 247 B. E. Boser Homework 4 Due Monday, March 19, 2007 NTU 247 Spring 20071. The graph below shows a histogram of the output codes obtained
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UNIVERITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences NTU 247 B. E. Boser Homework 5 Due Monday, April 2, 2007 NTU 247 Spring 20071. Download the datasheet of the AD7677 A/D converter from www.ana
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UNIVERITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences NTU 247 B. E. BOSER Reference Chi-Hung Lin, and Klaas Bult, A 10-b, 500-MSamples/s CMOS DAC in 0.6mm2, IEEE Journal of Solid-State Circuit, vol.
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Undergraduate IC-MEMS Processing LaboratoryIntroduction and HistoryThe EECS 143 undergraduate course Processing and Design of Integrated Circuits has been designed to familiarize students with fabrication technology, types of device structures, ele
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The TA Manual for EE143Documentation from Fall 2002 Revision #0Table of ContentsThe TA Manual for EE143 . 1 Table of Contents.. 2 Preface/Motivation of Documentation. 3 Head TAs responsibilities:.. 4 Lab TAs responsibilities:. 5 TA Weekly Checkl
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College of Engineering Department of Electrical Engineering and Computer Sciences University of California, Berkeley Below are your weekly quizzes. You should print out a copy of the quiz and complete it before your lab section. Bring in the complete
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Department of Electrical Engineering and Computer Sciences University of California, BerkeleyWeek #3 Quiz-Active Area DefinitionName _ Section _ Date _ (1) How does spin speed and time affect photoresist application?(2) What is the purpose of t
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Department of Electrical Engineering and Computer Sciences University of California, BerkeleyWeek #4 Quiz-Gate OxidationName _ Section _ Date _ (1) What is the purpose of the furnace tube TCA step?(2) Why do we run an additional "control" wafer
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Department of Electrical Engineering and Computer Sciences University of California, BerkeleyWeek #6 Quiz-Gate DefinitionName _ Section _ Date _ (1) Assuming perfect alignment, please draw a top view of what the overlapping alignment markers will
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Department of Electrical Engineering and Computer Sciences University of California, BerkeleyWeek #7 Quiz-Source/DrainName _ Section _ Date _ (1) What is the purpose of the spin-on glass (SOG)?(2) Why is the timing of the pre-diffusion step impo
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Department of Electrical Engineering and Computer Sciences University of California, BerkeleyWeek #8 Quiz-Contact CutName _ Section _ Date _ (1) What layer will we be cutting through today?(2) What etchant (and what concentration) will we be usi
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Department of Electrical Engineering and Computer Sciences University of California, BerkeleyWeek #9 Quiz-MetallizationName _ Section _ Date _ (1) Draw a schematic diagram of the vacuum system, in the detail given in the lab manual. (label all com
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Department of Electrical Engineering and Computer Sciences University of California, BerkeleyWeek #10 Quiz-Metal DefinitionName _ Section _ Date _ (1) At what temperature is the aluminum etchant kept? Why can't the aluminum etchant be used at room
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Department of Electrical Engineering and Computer Sciences University of California, BerkeleyWeek #11 Quiz-CharacterizationName _ Section _ Date _ (1) What is Metrics and what is it used for?(2) What is a HP-4145 and what can it measure?(3) Ho
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Department of Electrical Engineering and Computer Sciences University of California, BerkeleyWeek #12 QuizMEMS Processing & CharacterizationName _ Section _ Date _(1) Unlike MOSFET fabrication where we removed PR of METL layer to prepare for sin
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Fabrication Process Flow:Week 2: Field Oxidation - 5200 AWeek 3: Active Area PhotolithographyWeek 4: Gate Oxidation - 800 AWeek 5: Poly-Si DepositionWeek 6: Gate PhotolithographyWeek 6: Clear Source and DrainWeek 7a: Source-Drain Deposit
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1NMOS Fabrication Process DescriptionModified by Alex Chediak on March 2000. Modified by TAs team (Eric Hobbs, Paul Hung, Paul Friedberg, Min She) in Fall semester, 2002.Part 1) A checklist: what do you need in EE143 lab and microlab?At the beg
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Furnace process tips: 1. When removing the end cap from tube, push it back straightly. If it is stuck to the tube, move it slightly up and down. (Always put on insulating gloves since it is very hot.) You can also apply this process tip to the cylind
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EE143 MEMS DevicesGeneral Comments: MEMS devices were fabricated in the identical process as you performed in the EE143 lab. A XeF2 etch was performed as the last step, to remove some of the Si substrate and free the oxide structures. The structures
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MEMS in EE143Why are MEMS being incorporated into the EE143 mask set?Because MEMS constitute a growing field which has spawned from the robust and widespread microfabrication industry. Many traditional integrated circuit corporations are now invest
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Lab Report 1 Table of Contents1. Profiles & Layout (14 Points) 2. Process Procedures (30 points) 3. Calculations (26 Points) 4. Questions (30 Points) 5. Bonus Questions (10 Points)Total Points = 110 possible (graded out of 100)Please be sure to i
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Metrics TutorialTable of Contents1. 2. 3. 4. 5. 6. 7. Introduction The Set-Up Editor The Project File Manager Data Windows Plot Windows Exporting and Importing Data Linking Metrics and Excel1. IntroductionThe software package, Metrics, can be us
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Device CharacterizationTable of Contents1. Line Width and Misalignment Measurements: (Test Structures 1a, 1b) 2. Resistors: (Test Structures 2a-2b and 2c-2d) 3. Capacitors: (Test Structures 3, 4, 5) 4. Diode: (Test Structure 7) 5. MOSFET: (Test Str
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Tips for Capacitance MeasurementMeasurement set-up:On the source setup page for the CMH source be sure to select the Cp-Q capacitance model (for our values of capacitance this gives better readings than a series model). Also, be sure to choose a ca
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Summary of MOSFET ParametersParameter tox (gate) Measured/Extracted Theoretical UnitsC (gate) oxND NA xD CFB QSS (Qf)eff L (linear)Vt (field oxide) Vt L=4 L=6 L=8 L=10 W=10 W=15 W=20 k L=4 L=6 L=8 L=10 W=10 W=15 W=20
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Lab Report 2Table of Contents1. 2. 3. 4. 5. Measurements (20 points) Parameter Extraction (30 points) Calculations (35 points) Discussion (15 points) MEMS discussion (5 points)TOTAL = 100 points (+ 5 points)This report will summarize characteriz
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Safety, Cleaning, and Chemical Disposal Procedures1. Using AcidsAt many points in the fabrication process strong acids are used as etchants. These cause severe burns if kept in contact with your skin for more than a few seconds, and will cause blin
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Using Vernier ScalesVernier scales allow us to resolve alignment errors much more acurately than the minimum feature size for agiven process. To gain this fine resolution, they depend on accurately spaced lines. The picture on the left is a close re
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. Etch Rates for Micromachining and IC Processing (A/min) v. 4.4 29 July 1996 U.C. Berkeley Microfabrication Laboratory / Berkeley Sensor & Actuator Center / Kirt R. Williams The top etch rate was measured by the author with fresh solutions, clean ch
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EE143XeF2 etch tutorialSpring 2000 TAsXeF2 Etching of Silicon Characteristics: dry, isotropic, vapor-phase etch XeF2 sublimates at its vapor pressure (~3.8 Torr at 25 C) to etch silicon. Important: Wafer surfaces need to be dehydrated immediate
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Laboratory EquipmentProcessing 1 Headway Research Inc. Model EC101 Photoresist Spinner 1 Thermolyne Type 1900 Hot Plate, controlled by Omega CN76000 temperature controller 1 Model HP-A1915B Hot Plate Oven, one Model OV-10600 Hot Plate O
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Kasper Mask Aligner Manual1. IntroductionThe Kasper Wafer Alignment System is an integrated optical-mechanical, pneumatic-electrical system which allows accurate alignment of sensitized semiconductor wafers with a mask and exposes them to ultraviol
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NanoSpec Manual1. BackgroundThe NanoSpec is an instrument for measuring the thickness of optically transparent thin (10 to 4000 nm) films on silicon wafers. The basic operating principle is that the intensity of monochromatic reflected light depend
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Four-Point Probe Manual1. IntroductionThe purpose of the 4-point probe is to measure the resistivity of any semiconductor material. It can measure either bulk or thin film specimen, each of which consists of a different expression. The derivation w
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Description of a Basic Vacuum SystemFigure 1: Configuration of a basic vacuum system. The system, illustrated in Figure 1, contains the essential elements typically required to obtain high vacuum. The most common and reliable systems utilize three
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Cory 218 Aluminum Thermal Evaporator(ATE) 1.0 TitleAluminum thermal evaporator (ATE) in Cory 2182.0 Purpose:This document has specific information about the aluminum thermal evaporator in Cory 218 to help EE143 TAs and students understand its sa
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SUPREM SSUPREM3 and TSUPREM-4 are licensed products, and use is restricted to students in EECS courses at UCB. SSUPREM3:o o o o o o o o o o o o o o o o o o o o o o o o oSSUPREM3 is licensed software from Silvaco International. Please see /usr/pub/
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TSUPREM4 Process Simulation Results for EE143 MOSFET DeviceFall 2002In courtesy of Daewon HaEE143 MicrofabricationWeek 1, Fall 2002Initial 3 <100> WFSi substrateEE143 MicrofabricationWeek 1, Fall 2002Boron Implantation (11B, 3.0x101
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SIMPL Manual1. GETTING STARTED RUNNING SIMPLIn order to run SIMPL on Ara, you need to have an account on the Ara/Cory cluster. If you are running the software directly from the host workstation (e.g. in 111 Cory), you can skip to Section III. If yo
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SAMPLE TUTORIALBarry Paul Linder, Spring 1996.IntroductionSAMPLE is a simulation package that mimics a real processing laboratory. The machines SAMPLE simulates include an Exposure machine, a Developer machine, an E-beam machine, an Ion-beam mach
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N.CHEUNGEE143, Fall 2005 Homework Assignment #1 (Due September 15, 9:40am in class)Required Reading 1)Introduction to Microengineering by Danny Bank in EE143 Reader 2) Streetman, Chap 3, Energy bands and charge carriers in semiconductors in EE143
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N.CHEUNG Homework Assignment # 2 (Due 9/22 Th, 9:40pm) Reading Assignments 1) Chapter 3 of Jaeger on Thermal Oxidation 2) EE143 Reader Chapter 9 of Mayer and Lau on Thermal Oxidation.EE143, Fall 2005*There will be discrepancy in xox , B, and B/A
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N.CHEUNG Homework Assignment #3 (Due Sept 29, Th, 9:40pm) Reading Assignment 1) Chapter 5 of Jaeger on Ion Implantation [Overview] 2) 143Reader : Chapter by Mayer and Lau on Ion Implantation [mechanisms] 3) 143 Reader Projected Range and Straggle dat
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N.CHEUNG Homework Assignment #4 (Due Oct 6 Thur 9:40am)EE143, Fall 2005Note: Different textbooks use either C(x) or N(x) to represent the concentration and Q or to represent the dopant dose. Reading Assignment 1)Jaeger, Chapter 4 on diffusion [
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EE143, Fall 2005 Homework Assignment # 5 (Due Oct 20, Thur ; together with HW#6) Reading Assignment Jaeger, Chap 2 EE143 Reader [in Week #7 Reading Section] Chap 11 by Sze on lithography EE143 Lecture Notes Problem 1 Thermal expansion of glass mask a
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N.CHEUNG EE143, F2005 Homework Assignment # 6 (Due Oct 20, Thur 9:30am , together with HW#5) Reading Assignment A. Chapter 6 of Jaeger ( Sections 6.4.2 and 6.4.3 are not required) B. EE143 Reader: Week #6 1) Vaccum Technology and Sputtering Basics r
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N.CHEUNG Homework Assignment # 7 (Due Oct 27, Thursday ,9:30am)EE143, F2005Reading Assignment 1) EE143 reader Week #8 : Chapter on Etching by G. Anner, Planar Processing Primer 2) EE143 Lecture Notes Problem 1 Etching Profile (a) Poly-Si of the f
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N.CHEUNG Homework Assignment # 8 (Due Nov 3, Thur 9:30am)EE143, Fall 2005Reading Assignment Introduction: Chapter 7 of Jaeger on Interconnect and contacts Brief description of CMP Section 3.8.2 of Jaeger. EE143 Reader,Chapter 15 Campbell on metal
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Fall 2005 Homework Assignment # 9 (Due Nov 17, 9:30am) together with HW#10 Reading Assignment 1)Jaeger, pp.212-221 2)Summary sheet of EE143 layout rules (attached) 3) EE143 Reader Week#11 (Design Rule Basics from Physical Design of CMOS IC Using L-Ed