129
Homework CPE 12B Solution
W. Pilkington
1) Write the VHDL Code for a 3-to-8 Binary Decoder, with Active Low outputs (outputs are '1' for all channels, except the output is '0' for the channel number that matches the binary input code); and with an Active Low strobe enable (ALL outputs are made to be inactive (ALL '1's) if a '1' is received on this input.
3-to-8 Decoder B0 B1 B2
EN
F0 F1 F2 F3 F4 F5 F6 F7
~EN 0 0 0 0 0 0 0 0 1
B1 B1 B0 ~F0 ~F1 0 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
~F2 1 1 0 1 1 1 1 1 1
~F3 1 1 1 0 1 1 1 1 1
~F4 1 1 1 1 0 1 1 1 1
~F5 1 1 1 1 1 0 1 1 1
~F6 ~F7 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1
CPE 129
Homework 12B Solution
W. Pilkington
------------------------------------------------------------ Company: Cal Poly State University -- Engineer: W. Pilkington -- Module Name: BinaryDecoder3to8 - Conditional -- Target Devices: Spartan 3 FPGA ----------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity is BinaryDecoder3to8_EnLow Port ( Binary_In : in STD_LOGIC_VECTOR (2 downto 0); Enable_Low: in STD_LOGIC; Decode_Out : out STD_LOGIC_VECTOR (7 downto 0)); end BinaryDecoder3to8_EnLow; architecture Conditional_version of BinaryDecoder3to8_EnLow is begin -- Using a Selected Signal Assignment "11111111" when (Enable_Low = '1') else -- Handled the Enable_Low first "01111111" when (Binary_In = "111") else "10111111" when (Binary_In = "110") else "11011111" when (Binary_In = "101") else "11101111" when (Binary_In = "100") else "11110111" when (Binary_In = "011") else "11111011" when (Binary_In = "010") else "11111101" when (Binary_In = "001") else "11111110" when (Binary_In = "000") else "11111111" ; -- Just in case
Decode_Out <=
end Conditional_version;
2) BCD to 7 Segment Decoder VHDL Design ( Solution will be part of your CPE 169 Lab Experiment #6 Report! )