Connecting Input/Output: to the Outside World
So far, weve learned how to
Compute with values in registers Move data between memory and registers
Chapter 8 Input/Output
Based on slides McGraw-Hill Additional material 2004/2005 Lewis/Martin Modified by Diana Palsetia
But how do we interact with computers?
Outside World Receiving Information to process Outputting processed information
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Examples of Input/Output (I/O) Devices
Standard Interfaces 1. User output
Console or Prompt (just text), Video Display, printer, speakers
LC-3 I/O
I/O is done via the TRAP instruction
Code OUT GETC Equivalent TRAP x21 TRAP x20 Description Write one character (in R0[7:0]) to console. Read one character from keyboard. Character stored in R0[7:0]. Read (and echo) one character from keyboard. Character stored in R0[7:0]. Write null-terminated string to console. Starting address of string is in R0.
2. User input
Keyboard, mouse, trackball, game controller, scanner, microphone, touch screens, camera (still and video), game controllers
3. Storage
Disk drives, CD & DVD drives, flash-based storage, tape drive
More Communication
Network (wired, wireless, optical, infrared), modem
IN
TRAP x23
Sensor inputs
Temperature, vibration, motion, acceleration, GPS Barcode scanner, magnetic strip reader, RFID reader
PUTS
TRAP x22
Control outputs
Motors, actuators
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Example 1
; Prints ABBCDEFGHI. Each Character is printed on a newline .ORIG x3000 LD R3, A ; R3 = x0041 = A LD R4, J ; R4 = x004A = J NOT R4, R4 ADD R4, R4, #1 ; 2s COMP of R4 PCHAR: AND R0, R0, #0 ; CLEAR R0 ADD R0, R0, R3 ; R0 = R3 OUT ; DISPLAY CHAR AND R0,R0, #0 ; CLEAR R0 LD R0, NEWL ; R0 = x000A OUT ; DISPLAY NEWLINE ADD R3, R3, #1 ; R3 + 1 for NEXT CHAR AND R5, R5, #0 ADD R5, R3, R4 ; CHECK if we reached J BRn PCHAR HALT ; TERMINATE ;*********DATA*********** A: .FILL x0041 NEWL: .FILL x000A J: .FILL x004A .END
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EXAMPLE 2
;Prompt the user to enter a number, quits when pressed 3, prints DONE before terminating
.ORIG x3000 LD R1, VAL3 NOT R1, R1 ADD R1, R1, #1 LEA R0, ENTER PUTS ; displays the string LOOP: IN ; read and echo AND R3, R3, #0 ADD R3,R1, R0 BRnp LOOP LEA R0, ENDMSG ; R0 = starting address of string PUTS HALT ENTER: .STRINGZ "Enter a number from 1 to 9:\n" ENDMSG: .STRINGZ "\nDONE" VAL3: .FILL x0033 .END
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I/O Basics
Control/Status Registers
CPU tells device what to do -- write to control register CPU checks whether task is done -- read status register
Programming Interface
How are device registers identified?
Memory-mapped vs. special instructions
Data Registers
CPU transfers data to/from device
Control/Status I/O Controller Electronics
How is timing of transfer managed?
Asynchronous vs. synchronous
CPU
Data
device
Who controls transfer?
CPU (polling) vs. device (interrupts)
Device electronics
Performs actual operation Pixels to screen, bits to/from disk, characters from keyboard
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Memory-Mapped vs. I/O Instructions
Instructions
Designate opcode(s) for I/O Register and operation encoded in instruction
Transfer Timing
Synchronous
Data supplied at a fixed, predictable rate CPU reads/writes every X time units Infrequently used because of speed difference I/O is much slower than the processor
E.g. A 300 Mhz processor can execute an instruction every 33 nanseconds E.g. Humans dont type as fast as a processor can read
Memory-mapped
Assign a memory address to each device register Use data movement instructions (LD/ST) for control and data transfer Hardware intercepts these address No actual memory access performed
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Asynchronous
Data rate less predictable CPU must synchronize with device, so that it doesnt miss data or write too quickly Handles the speed mismatch
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Transfer Control
Who determines when the next data transfer occurs? Polling
CPU keeps checking status register until new data arrives OR device ready for next data Are we there yet? Are we there yet? Are we there yet?
LC-3 I/O
Memory-mapped I/O
Location I/O Register
Keyboard Status Reg (KBSR) Keyboard Data Reg (KBDR) Display Status Register (DSR) Display Data Register (DDR) (Table A.3 in Appendix A of text)
Function
Bit [15] is one when keyboard has received a new character. Bits [7:0] contain the last character typed on keyboard. Bit [15] is one when device ready to display another char on screen. Character written to bits [7:0] will be displayed on screen.
xFE00 xFE02 xFE04 xFE06
Interrupts
Device sends a special signal to CPU when new data arrives OR device ready for next data CPU can be performing other tasks instead of polling device Wake me when we get there.
Asynchronous devices
Synchronized through status registers Two ways: Polling and Interrupts Well talk first about polling, a bit on interrupts later
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Input from Keyboard
When a character is typed:
Its ASCII code is placed in bits [7:0] of KBDR (bits [15:8] are always zero) The ready bit (KBSR[15]) is set to one Keyboard is disabled -- any typed characters will be ignored
15 8 7 0
Basic Input Routine (GETC)
POLL
NO
keyboard data KBDR KBSR
new char?
YES
LDI R0, KBSRPtr BRzp POLL LDI R0, KBDRPtr ...
1514
0
Polling
ready bit When KBDR is read by processor:
KBSR[15] is set to zero Keyboard is enabled
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read character
KBSRPtr .FILL xFE00 KBDRPtr .FILL xFE02
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LC-3 Von Nuemann Model
Simple Implementation: Memory-Mapped Input
Address Control Logic determines whether MDR is loaded from Memory or from KBSR/KBDR.
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Output to Monitor
When Monitor is ready to display another character:
The ready bit (DSR[15]) is set to one, indicating that the processor can transfer another ASCII code to 15 DDR
15 15 0 8 7 0
Basic Output Routine
POLL
NO
output data DDR DSR
screen ready?
YES
LDI R1, DSRPtr BRzp POLL STI R0, DDRPtr ...
ready bit
Polling
When data is written to Display Data Register:
DSR[15] is set to zero While DSR[15] is zero, the monitor is still processing the previous character Character in DDR[7:0] is displayed
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write character
DSRPtr .FILL xFE04 DDRPtr .FILL xFE06
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Simple Implementation: Memory-Mapped Output
Keyboard Echo Routine (IN)
Usually, input character is also printed to screen
User gets feedback on character typed and knows its ok to type the next character POLL1 LDI BRzp LDI LDI BRzp STI ... R0, KBSRPtr POLL1 R0, KBDRPtr R1, DSRPtr POLL2 R0, DDRPtr
new char?
YES
NO
POLL2
read character
Sets LD.DDR or selects DSR as input.
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KBSRPtr KBDRPtr DSRPtr DDRPtr
.FILL .FILL .FILL .FILL
xFE00 xFE02 xFE04 xFE06
NO
screen ready?
YES
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General I/O
The interactions described can be applied to most I/O devices
The status register in a printer might tell you (via computer) If the printer is printing, or Is out of paper, or out of toner
Interrupt-Driven I/O
Why ? Polling consumes a lot of machine processing cycles, especially for rare events these cycles can be used for more computation Again, I/O devices are slow Example: re-executing again and again the LDI and BR instructions until the Ready bit it set.
Data/Information that is transferred can be more than just a byte
Some device have higher data transfer rate E.g. Disk
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Interrupt-Driven I/O (contd..)
I/O device can. . . Notify the processor that it needs attention Have the processor satisfy the devices needs Force currently executing program to stop (only if it has a higher priority) Resume the stopped program as if nothing happened
To implement an Interrupt mechanism
1. Way for I/O device to signal CPU that its wants service
We already have a Ready bit indicating that
15 14 0
ready bit
Status reg
2. Way to know that device has a right to request service Interrupt enable bit in device register is set by processor
Depending on whether processor wants to give I/O device service
When ready bit is set and IE bit is set, interrupt is signaled I/O device will get service
interrupt enable bit ready bit
1514 13
0
KBSR
interrupt signal to processor
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To implement an Interrupt mechanism (contd..)
3. Whether I/O device has higher priority among multiple I/O requests AND with the current program in execution
Every instruction executes at a stated level of urgency LC-3: 8 priority levels (PL0-PL7) with 7 being higher priority Example:
Payroll program runs at PL0 Nuclear power correction program runs at PL6 Its OK for PL6 device to interrupt PL0 program, but not the other way around A special hardware compare priority levels of the interrupts generated, the one with higher priority gets to use the processor
Maintaining the state of the machine
You were in the middle of adding 2 numbers in your program, but there was interrupt
Did I complete my operation? After I resume, is my data in the registers that I was storing the same as I left of ?
Before FETCH stage in the instruction cycle:
Check for Interrupt If interrupt, then save to memory the state of the machine, i.e. Registers and PC and CCs This way I can come back start executing where I left Load the PC with starting address of the program that is...