Notes EE4733/EE6733 1999
Coprocessors
General View Motivation
S
Want increased performance tailored to need. Ex: floating point arithmetic matrix manipulation fast Fourier transforms graphics
S S
Allows transformation of main processor code to hardware Not just a peripheral distinguished by special coprocessor (cp) interface that allows extension of mains 1. instruction set 2. register set 3. data types 4. memory map interaction between cp and main semitransparant to programmer model is sequential, nonconcurrent => simple to use (but more understanding is needed to exploit underlying concurrency)
MC68000 Family Interface (see MC68881/2 Users Manual) clk1 fc[2:0] a[19:13] 68020 main as ds r/w dsack[1:0] a[4:1] d[31:0] coprocessor interface registers CIRs usual asynchronous bus (so cp could be offboard) cs cp clk2
1
EE4733/EE6733 Notes 1999
CP Instruction Format & Protocol M1 Main fetches Fline instruction (28 words in length) d15 11 9 0 1111 cpid type type dependent fc2 fc0 000101 Motorola 000 68851 PMMU 111 001 68881/2 FP 110111 User cpu space cp communications (recall 1111 is interrupt ack) M2 Main fetches cp command word and writes to command CIR C1 Decode & initiate execution options extensions C2 While main needed 1) request service using response CIR 2) receive service from main C3 No come again in response CIR C4 Complete execution M4 Proceed with next instruction C5 Processing finished in response CIR address bus encoding (cpu space) a31 19 16 15 13 4 0 0 0 0 0 1 0 cpid 0 0 CIR
M3 Read cp response CIR 1) perform service 2) if come again goto M3
Response Register Primitives
S S S S S S S S
busy from previous instruction busy with current instruction pass opcode pass word from instruction stream evaluate & pass EA evaluate EA & transfer data transfer main register transfer multiple cp registers
2
EE4733/EE6733 Notes 1999
Instruction Types 1. general 2. conditional cpGEN cpBcc.x cpScc cpDBcc cpTRAPcc
3. context save 4. context restore Example General MC68881/2 Instruction fsincos.x where sine of <ea>s destination is fps and cosine of <ea>s destination is fpc cpid type(gen) fline ea opword 1111 001 000 0 r/m 0 source fps 0110 fpc command fpm,fpc:fps fsincos.<fmt> <ea>,fpc:fps
Example MC68881/2 CIR Map
$00 $02 $04 $06 $08 $0a $0c $0e $10 $14 $18 $1c
response control save restore operation word command reserved condition operand register select instruction address operand address
3
EE4733/EE6733 Notes 1999
Using the MC68881/2 Coprocessor Hardware Features
S S S S S
eight 80bit data registers highspeed 67bit alu 67bit barrel shifter (1 to 67bit shifts in 1 cycle) ROM constants Floatingpoint data registers added 79 63 0 fp0 fp1
Programming Model
fp7
S
Control, Status and FloatingPoint Instruction Address registers added exception mode enable control 0
fpcr (control) exception status accrued exception quotient fpsr (status) condition code fpiar (instr. addr)
31
FPCR Exception Byte BSUN branch/set on unordered conditional with notanumber (NAN) input SNAN signaling NAN (using a nonIEEE data type) OPERR operand error (operator/operand mismatch) OVFL overflow UNFL underflow DZ divide by zero INEX2 inexact operation INEX1 inexact decimal input Ex. fdiv.p #7e1,fp3 INEX1 INEX2
4
EE4733/EE6733 Notes 1999
FPCR Control Mode Byte RND = FPCR(5:4) 00 round to nearest even 01 toward zero 10 infinity 11 + infinity 00 extended 01 single 10 double
FREC = FPCR(7:6)
FPSR Condition Codes = FPSR(27:24) N (negative), Z (zero), I (infinity), NAN Quotient = FPSR(23:16) 7 least significant bits of Q and sign used in fmod and frem instructions Status = FPSR(15:8) Accrued Exception Byte = AEXC = FPSR (7:3) sticky exception bits and functions FPIAR Used to locate offending instructions
S
four added operand data formats suffix <fmt> single precision real double precision real extended precision real packed decimal strings real (s) (d) (x) (p) exp. bits 8 11 15 man. bits 23(+1) 52(+1) 64
12* 68** *3digit base id **17digit mantissa
5
EE4733/EE6733 Notes 1999
IEEE P754 Short Real (Single Precision) Floating Point Format 8 bits S exponent = E E7 E0 F22 N= 23 bits fraction = F For normalized numbers F0
N = f(m,e) N=m re r=2 m= 1
1.v1(F)
v2(E) =
2v2(E)
n=0 7
" 1.v (F) v jmj t 2
1
where v1(F) = and and
S Fn 2(23n)
22
Special cases: E all 1s and F all 0s implies signed infinity E all 1s and F nonzero implies Not A Number, (NAN) E all 0s and F all 0s implies signed 0 E all 0s and F nonzero implies a denormal (underflow) Ex. 3.0 = 1.5 x 21, therefore v1(F) = 0.5 and v2(E) = 1, 0x40400000 0 10000000 10000000000000000000000 46 Added Instructions 35 arithmetic operations 22 constants available Five classes of instructions (refs: Programmers Ref and MC 68881/2 Man.) 1. moves comversions: MC68881/2 < (to or from) > MC680x0 memory (internal extended precision) (<fmt>, source or destination format) syntax: fmove.<fmt> <ea>,fpn fmove.<fmt> fpm,<ea> fmove.x fpm,fpn fmove.p fpm,<ea>{dn} see page 468 of MC 68881/2 man. fmove.p fpm,<ea>{#k} or page 578,79 of Progammers Ref. move constants: fmovecr.x #ccc, fpn (pi, e, ln(2), etc.) move multiples (see 476,77 of MC 68881/2 man. or 589,90 of Programmers Ref.) fmovem.x with dynamic register list spec...