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EE141- EE141 Spring 2004 Digital Integrated Circuits Lecture 25 Oscillators and Bi-stables Bi- 1 EE141 EE141-S04 Administrative Stuff Homework 8 posted Due on Fr Last software lab THIS week Project on web-site! No class on Th Make-up lecture probably next week Fr 2 EE141 EE141-S04 1 EE141 Class Material Today s lecture Oscillators and multivibrators Timing 3 EE141 EE141-S04 Other Sequential Circuits Schmitt Trigger Monostable Multivibrators Astable Multivibrators 4 EE141 EE141-S04 2 EE141 Schmitt Trigger Vou t In Out V OH VTC with hysteresis Restores signal slopes V OL VM EE141 EE141-S04 VM+ Vi n 5 Noise Suppression using Schmitt Trigger 6 EE141 EE141-S04 3 EE141 CMOS Schmitt Trigger VDD M2 Vin X M4 Vout M1 M3 Moves switching threshold of the first inverter 7 EE141 EE141-S04 Schmitt Trigger Simulated VTC 2.5 2.0 1.5 ) V ( X V 2.5 2.0 VM1 ) V ( x 1.5 V 1.0 0.5 0.0 0.0 VM2 1.0 0.5 0.0 0.0 k=1 k=3 k=2 k=4 0.5 1.0 1.5 Vin (V) 2.0 2.5 0.5 1.0 1.5 Vin (V) 2.0 2.5 Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of the PMOS device M4. The width is k* 0.5m m. 8 EE141 EE141-S04 4 EE141 CMOS Schmitt Trigger (2) VDD M4 M6 M3 In M2 X M1 9 EE141 EE141-S04 Out M5 VDD Multivibrator Circuits R S Bistable Multivibrator flip-flop, Schmitt Trigger T Monostable Multivibrator one-shot Astable Multivibrator oscillator 10 EE141 EE141-S04 5 EE141 Transition-Triggered Monostable In DELAY td Out td 11 EE141 EE141-S04 Monostable Trigger (RC-based) VD D In R A C B Out (a) Trigger circuit. In B VM (b) Waveforms. Out t1 EE141 EE141-S04 t t2 12 6 EE141 Astable Multivibrators (Oscillators) 0 1 2 N-1 Ring Oscillator simulated response of 5-stage oscillator 13 EE141 EE141-S04 Relaxation Oscillator Out1 I1 I2 Out2 R Int C T = 2 (log3) RC 14 EE141 EE141-S04 7 EE141 Voltage Controller Oscillator (VCO) V DD M6 VDD M4 Schmitt Trigger restores signal slopes M2 In M1 Iref Vcontr M5 M3 Iref Current starved inverter 6 tpH L (nsec) 4 2 0.0 0.5 1.5 V co ntr (V) 2.5 propagation delay as a function of control voltage 15 EE141 EE141-S04 Timing Definitions 16 EE141 EE141-S04 8 EE141 Synchronous Timing CLK In R1 Cin Combinational Logic Cout R2 Out 17 EE141 EE141-S04 Latch Parameters D Q Clk T Clk D tc-q PWm thold td-q tsu Q Delays can be different for rising and falling data transitions 18 EE141 EE141-S04 9 EE141 Register Parameters D Q Clk T Clk D tsu Q tc-q Delays can be different for rising and falling data transitions 19 EE141 EE141-S04 thold Clock Uncertainties 4 Power Supply 3 Interconnect Devices 2 6 Capacitive Load 7 Coupling to Adjacent Lines 5 Temperature 1 Clock Generation Sources of clock uncertainty 20 EE141 EE141-S04 10 EE141 Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clocking 21 EE141 EE141-S04 Clock Skew and Jitter Clk tSK Clk tJS Both skew and jitter affect the effective cycle time Only skew affects the race margin 22 EE141 EE141-S04 11 EE141 Clock Skew # of registers Earliest occurrence of Clk edge Nominal /2 Latest occurrence of Clk edge Nominal + /2 Insertion delay Max Clk skew Clk delay 23 EE141 EE141-S04 Positive and Negative Skew In CLK R1 D Q tCLK1 delay (a) Positive skew R1 D Q tCLK1 delay (b) Negative skew 24 EE141 EE141-S04 Combinational Logic R2 D Q tCLK2 Combinational Logic R3 D Q tCLK3 delay In Combinational Logic R2 D Q tCLK2 Combinational Logic R3 D Q tCLK3 delay CLK 12 EE141 Positive Skew TCLK + CLK1 1 TCLK 3 CLK2 2 + th 4 Launching edge arrives before the receiving edge 25 EE141 EE141-S04 Negative Skew TCLK + CLK1 1 TCLK 3 CLK2 2 4 Receiving edge arrives before the launching edge 26 EE141 EE141-S04 13 EE141 Timing Constraints In R1 D Q tCLK1 tc q tc q, cd tsu, thold tlogic tlogic, cd Combinational Logic R2 D Q tCLK2 CLK Minimum cycle time: T + = tc-q tlogic + + tsu Worst case is when receiving edge arrives early (negative ) 27 EE141 EE141-S04 Timing Constraints In R1 D Q tCLK1 tc q tc q, cd tsu, thold tlogic tlogic, cd Combinational Logic R2 D Q tCLK2 CLK Hold time constraint: t(c-q, cd) + t(logic, cd) > thold + Worst case is when receiving edge arrives late (positive ) Race between data and clock 28 EE141 EE141-S04 14 EE141 Impact of Jitter 2 CLK TC LK 4 5 t j itter -tji tte r 6 1 3 In REGS Combinational Logic t log ic t log ic, cd CLK tc-q , tc-q, ts u, thold tjitter cd 29 EE141 EE141-S04 Longest Logic Path in Edge-Triggered Systems TSU Clk TClk-Q TLM T TJI + Latest point of launching Earliest arrival of next cycle 30 EE141 EE141-S04 15 EE141 Clock Constraints in Edge-Triggered Systems If launching edge is late and receiving edge is early, the data will not be too late if: Tc-q + TLM + TSU < T TJI,1 TJI,2 - Minimum cycle time is determined by the maximum delays through the logic Tc-q + TLM + TSU + + 2 TJI < T Skew can be either positive or negative 31 EE141 EE141-S04 Shortest Path Earliest point of launching Clk TClk-Q TLm Clk TH Data must not arrive before this time Nominal clock edge 32 EE141 EE141-S04 16 EE141 Clock Constraints in Edge-Triggered Systems If launching edge is early and receiving edge is late: Tc-q + TLM TJI,1 < TH + TJI,2 + Minimum logic delay Tc-q + TLM < TH + 2TJI+ 33 EE141 EE141-S04 How to counter Clock Skew? Negative Skew REG REG REG In . REG log Out Positive Skew Clock Distribution Data and Clock Routing 34 EE141 EE141-S04 17 EE141 Clock Distribution H-tree CLK Clock is distributed in a tree-like fashion 35 EE141 EE141-S04 More realistic H-tree [Restle98] 36 EE141 EE141-S04 18 EE141 The Grid System GCLK Driver D iver r D rive r GCLK GCLK No rc-matching Large power Driver GCLK 37 EE141 EE141-S04 Example: DEC Alpha 21164 Clock Frequency: 300 MHz - 9.3 Million Transistors Total Clock Load: 3.75 nF Power in Clock Distribution network : 20 W (out of 50) Uses Two Level Clock Distribution: Single 6-stage driver at center of chip Secondary buffers drive left and right side clock grid in Metal3 and Metal4 Total driver size: 58 cm! 38 EE141 EE141-S04 19 EE141 21164 Clocking tcycle= 3.3ns trise = 0.35ns tskew = 150ps Clock waveform final drivers 2 phase single wire clock, distributed globally 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width pre-driver Location of clock driver on die EE141 EE141-S04 Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variation 39 Clock Drivers 40 EE141 EE141-S04 20 EE141 Clock Skew in Alpha Processor 41 EE141 EE141-S04 EV6 (Alpha 21264) Clocking 600 MHz 0.35 micron CMOS tcycle= 1.67ns trise = 0.35ns Global clock waveform tskew = 50ps 2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width PLL Local clocks can be gated off to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking 42 EE141 EE141-S04 21 EE141 21264 Clocking 43 EE141 EE141-S04 EV6 Clock Results ps 5 10 15 20 25 30 35 40 45 50 GCLK Skew (at Vdd/2 Crossings) EE141 EE141-S04 ps 300 305 310 315 320 325 330 335 340 345 GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%) 44 22 EE141 EV7 Clock Hierarchy Active Skew Management and Multiple Clock Domains NCLK (Mem Ctrl) + widely dispersed drivers DLL DLL + DLLs compensate static and lowfrequency variation + divides design and verification effort L2L_CLK (L2 Cache) DLL L2R_CLK (L2 Cache) PLL GCLK (CPU Core) - DLL design and verification is added work + tailored clocks 45 SYSCLK EE141 EE141-S04 Self-timed and Asynchronous Design Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 1) Completion is ensured by careful timing analysis 2) Ordering of events is implicit in logic Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol 46 EE141 EE141-S04 23
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Lecture19-Adders.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: EE141 EE141- Spring 2004 Digital Integrated Circuits Lecture 19 Dynamic Logic - Adders (that is wrap-up) wrap- 1 EE141 EE141-S04 Administrative Stuff Hw 6 due on Th No lab this week Midterm 2 next week Project 2 to be launched week 12 2 EE141 E...
Lecture4-Inverter.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: EE141- Spring 2004 Lecture 4 Metrics CMOS Inverter MOS Transistor Model 1 EE141 EE141 Todays lecture Design Metrics (continued) The CMOS inverter at a glance An MOS transistor model for manual analysis 2 EE141 EE141 1 Important! Labs start next w...
Lecture10-Wires.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: EE141 EE141-Spring 2004 EE141Digital Integrated Circuits Administrative Stuff Homework #4 due today Midterm 1 is next Thursday, Febr 26, 6:30-8pm 277 Cory Review session Febr 25, 6-7:30pm TBD Lecture 10 Introduction to wires 1 EE141 EECS141-S04 E...
soft_lab3_f03.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on September 7, 2003 by Bill Tsang and David Fang (ctsang@eecs.berkeley.edu, dyfang@eecs.berkeley.edu) Borivoje Nikolic 1. Object...
homework2_solutions.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on Jan 24, 2004 by Brian Leibowitz (bsl@eecs.berkeley.edu) Jan Rabaey Homework #2 Due Thursday, February 5, 5pm @558 Cory EECS...
soft_lab2.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on September 8, 2003 by Vladimir Petkov (vlpetkov@eecs.berkeley.edu) Borivoje Nikolic 1. Objective Lab #2: Layout Editing with ...
Lecture21-Power+Sequential.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: EE141 EE141- Spring 2004 Digital Integrated Circuits Lecture 20 Power Sequential Logic - Intro 1 EE141 EE141-S04 Administrative Stuff Midterm 2 Th 6:30pm in 277 Cory Material: Wires Complex logic Arithmetic Review session on We at 5:30pm in 2...
Lecture20-Mult+Power.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: EE141 EE141- Spring 2004 Digital Integrated Circuits Lecture 20 Multipliers Power 1 EE141 EE141-S04 Administrative Stuff Hw 6 due today Midterm 2 next week Material: Wires Complex logic Arithmetic Review session on We 2 EE141 EE141-S04 1 E...
Lecture15-PTL.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: EE141 EE141-Spring 2004 Digital Integrated Circuits Lecture 15 Logical Effort Pass Transistor Logic 1 EE141 EECS141-S04 Administrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw 5 due on Th N...
OtherGateLogicaleffort.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: Chapter 10 Circuit Families So far, we have applied logical effort primarily to analyze static CMOS circuits. High-performance integrated circuits often use other circuit families to achieve better speed at the expense of power consumption, noise mar...
soft_lab6_f03.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on September 29, 2003 by Joshua Garrett (joshuag@eecs.berkeley.edu) Borivoje Nikolic 1. Objective As you have learned in class, t...
ee141_Fa03_Hw3_Sol.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on September 22, 2003 by Nuntachai Poobuapheun (nuntachp@eecs.berkeley.edu) Borivoje Nikolic Homework #3: CMOS Inverters and Desi...
Lecture16-Dynamic.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: EE141 EE141-Fall 2003 Digital Integrated Circuits Lecture 16 Pass-Transistor Logic Dynamic Logic EE141 EECS141 1 Administrative Stuff Homework #6 due next Tuesday Lab 6 (last software lab!) this week Project launch today Reading assignment: Adde...
Lecture14-LE.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: EE141 EE141-Fall 2003 Digital Integrated Circuits Lecture 14 Combinational Logic Sizing for Speed EE141 EECS141 1 Administrative Stuff Homework #5 due next Tuesday Lab 5 this week If you would like to have your midterm regraded, please turn it i...
Lecture24-Sequential.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: EE141 EE141-Fall 2003 Digital Integrated Circuits Lecture 24 Sequential Logic EE141 EECS141 1 Midterm 2 Hi: 39 (Grad: 40) Lo: 7 Median (UG) : 26 Distribution is bimodal, groups around 30 and around 20. EE141 EECS141 2 1 EE141 Administrative...
Lecture27-Memory.pdf
Path: Berkeley >> EE >> 141 Fall, 2008
Description: EE141 EE141-Fall 2003 Digital Integrated Circuits Lecture 27 Memory EE141 EECS141 1 Administrative Stuff Homework 9 due Thursday, 12/4 Homework 10 posted, due never Project phase 4 report due today Complete project reports are due 12/1 Template ...
Exergy.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Primary Energy Carriers and Transformations Intermediate Energy Carriers and Transformations End-use Energy Carriers and Transformations Atmos phere Subsur face CO2 Natural Plant Oxidation Plant Matter Extract ed Petrole um Paper Manufacturing...
Mason_poster.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Eigenstate Visualization for Nanodevices with High Symmetry D. J. Mason1,2 1Department 2The of Physics, Harvard University, Cambridge, MA Molecular Foundry, Lawrence Berkeley National Laboratory Motivation & Method User Interface Static Visualiza...
Viz_final_01.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: EigenstateExplorer2.0 DouglasMason Outline Disclaimer Scien9cBackground Whatsbeendone Whatcanbedone Disclaimer (notwriDenforselfpreserva9on) Background Aclosedsystemhasaresonantfrequencyfor eacheigenstatelikeaguitarstringwithxedends Backgrou...
NickProposalSlides2.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: VisualizingWIRED NicholasKong Whyvisualizetext? Informa>onretrieval MaketextpreaCen>ve Makeseman>cconnec>onsvisuallyexplicit Datamine Iden>fypaCernsinacorpus Adocumentormany,manydocuments Problem 14yearsofWIRED Visualizingtrendsoverthisper...
Mason_midpoint.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: EigenstateExplorerv2.0: TheMidPoint DouglasMason SomeScien>cDevelopments Abilitytocorrelateinforma>onbetween eigenstatesandelectrontransmissionexci>ng newdevelopment Canisolatecontribu>onofanindividualstate, likeastandingwave,totheconductance Can...
Seth-Presentation.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Visualizing Multi-dimensional Data SETH HORRIGAN COMPUTER VISUALIZATION FALL 2008 Motivation Multi-dimensional datasets are common Digital cameras Wall-street stocks Motor vehicles Cellular telephones A mixture of interval, ordinal, and nomin...
NickMidpointSlides.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: VisualizingWIRED VisualizingWIRED usingStatNewssta6s6cs VisualizingWIRED usingStatNewssta6s6cs Planoverview UseStatNewsforimportancesta6s6cs Zoomableuserinterface Representdocumentsbymostrelevantkeyword Keywordsizepropor6onalto#documents Sea...
FA08-MattGedigian-Paper.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Semantic Wiki Visualization Matt Gedigian Abstract Semantic wikis are wikis which incorporate machine-readable semantic structure. The data they expose can be visualized for many different purposes using various tools. One particularly interesting us...
Seth-FinalPoster.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Survis Visualizing comparisons of many ordinal variables Seth Horrigan Objective Visualize many ordinal or categorical variables and their interrelation. Solution Nested Category Map Nested category maps are based on the design of squarified treem...
Severity_Means.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Physical Planner Legibility: Not a problem (1) Overview: Minor problem (2) Search: Major Problem (3) Tediousness: Minor Problem (2) Space Limitations: Minor Problem (2) Google Calendar Text customization: Minor Problem (2) Duplicate assi...
FP-STCAKY-poster.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Palette Assistant Generating Nominal Color Encodings with Simulated Annealing Problem How can unique, quality color palettes for encoding nominal data be produced with minimal human intervention, while taking into account a designers preferences? CS...
FP-STCAKY-initial.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: COLOR PALETTE GENERATION FOR NOMINAL ENCODINGS Ketrina Yim, Calvin Ardi, Simon Tan CS 294-10 | Fall 2008 Problem & Motivation Color serves many functions in visualization Highlighting certain values Creating groupings Facilitating data layering Impr...
Ljuba-Jeremy-Final-Poster.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: GLOBAL ENERGY SYSTEMS NAVIGATOR: AN INTERACTIVE MAP OF ENERGY AND CARBON FLOWS JEREMY HUDDLESTON LJUBA MILJKOVIC The Global Energy Systems Navigator is an interactive map of the ows of carbon and exergy the useful portion of energy through global...
PretzlavMidpointPresentation.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Last.fm Explorer Interactive Visualization of Hierarchical Time-Series Data (Maxwell) Alex Pretzlav Stacked vs Line Future Plans Scented time slider google nance Track Drill Down User Comparison ...
VisProjectProposal.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Visualizing Collaborative Data Entry Forms Kuang Chen & Heather Dolan Data quality is very important The Data Entry problem Data entry is the first opportunity to address data quality Form design is often an ad hoc process New entry modalities...
Seth-MidpointPresentation.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Visualizing Multi-dimensional Questionnaire Data SETH HORRIGAN COMPUTER VISUALIZATION FALL 2008 Initial Concept Nesting charts to visualize many variables Project focus Visualize Likert-type or simple nominal or ordinal questions intuitively ...
Seth-FinalPaper.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Visualizing Relationships among Categorical Variables Seth Horrigan AbstractCenturies of chart-making have produced some outstanding charts tailored specifically to the data being visualized. They have also produced a myriad of less-than-outstanding ...
Severity_Questionnaire.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: SEVERITY QUESTIONAIRE The following 0 to 4 rating scale shall be used to rate the severity of usability and visual problems pertaining to assignment planning (i.e. assignment organization, assignment status, etc): 0 = I don\'t agree that this is a pro...
FP-DavidPoll-JeffBowman-Paper.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Releviz: Visualizing similar search results in two dimensions David Eitan Poll University of California, Berkeley depoll@berkeley.edu Abstract We present Releviz, a system that provides a two-dimensional interface for selecting and displaying multiva...
PretzlavFinalProposal.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Last.fm Explorer Interactive Visualization of Hierarchical Time-Series Data Tons of Data A Few Strong Visualizations Lee Byrons Streamgraph http:/www.leebyron.com/else/streamgraph/download.php? le=stackedgraphs_byron_wattenberg.pdf Last.fm Spiral...
HamlinPoster.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Maps of 3D Environments James F Hamlin Problem and Motivation Automatically-generated 2D maps are now commonly used. The problem of automatically generating maps displaying paths between two locations easily extends to 3D environments. Such maps may ...
PretzlavFinalPaper.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Last.fm Explorer: An Interactive Visualization of Hierarchical Time-Series Data Maxwell A. Pretzlav University of California, Berkeley alex@turnlav.net ABSTRACT This paper describes an interactive web-based visualization of a large and complex datas...
Mason_final.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: 1 Visualizing Eigenstates of Nanotransistors with Arbitrary Shape Douglas J. Mason I. I NTRODUCTION Developing a thorough understanding of physical data from simulated systems have proven a difcult task. In the eld of quantum chemistry large softwa...
FP-STCAKY-midpoint.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Midpoint Design Discussion COLOuR PALETTE GENERATION FOR NOMINAL ENCODINGS Ketrina Yim, Simon Tan, Calvin Ardi CS 294-10 | Fall 2008 Project Q: How can we produce unique, quality palettes with minimal human intervention? A: Algorithmically (simulat...
Mapping_3D_Environments.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Mapping 3D Environments James F Hamlin Edward Tufte. Visual Explanations. Graphics Press, 1997. From Navtej Sadhal. The Presentation of 3D Maps of Building Interiors for Easy Way-Finding. Project Description Generate static and interactive maps sh...
HamlinFinalPaper.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Automatically Generated Maps of 3D Environments James F. Hamlin University of California, Berkeley Abstract A system for generating visualizations of routes in 3D environments is presented. From the input of a 3D triangle mesh, the approximate heigh...
GESN.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: GLOBAL ENERGY SYSTEMS NAVIGATOR: AN INTERACTIVE VISUALIZATION OF ENERGY AND CARBON FLOWS Ljuba Miljkovic UC Berkeley, School of Information ljuba.miljkovic@gmail.com Jeremy Huddleston UC Berkeley, Department of Computer Science jeremyhu@berkeley.edu ...
FP-STCAKY-paper.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Color Palette Generation for Nominal Encodings Calvin Ardi Computer Science University of California, Berkeley Berkeley, CA +1 510 642 8679 calvin@rescomp.berkeley.edu Simon Tan Computer Science University of California, Berkeley Berkeley, CA +1 510 ...
KongCS294-10.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: StatVis: Visualization of Statistical Analysis of News Data Nicholas Kong University of California, Berkeley nkong@eecs.berkeley.edu ABSTRACT We describe a visualization of statistical analysis of news data, specifically the headlines of the New Yo...
NickKongPoster.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: ...
Trellis.jcgs.col-reverse.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: The Visual Design and Control of Trellis Display Richard A. Becker William S. Cleveland Ming-Jen Shyu 1750 V V E-W S-N S-N E-W V 1700 S-N E-W 1650 1600 V S-N E-W V S-N E-W 1550 1500 V V S-N E-W S-N E-W V E-W S-N 1450 Figure 1: Trellis di...
Final_Project_Proposal.pdf
Path: Berkeley >> CS >> 294 Fall, 1924
Description: Global Energy Systems Navigator Ljuba Miljkovic & Jeremy Huddleston CS294 - Visualization Final Project Proposal Climate Change Existing Visualizations Exergy Solar Radiation Solar Radiation 120000 120000 62000 62000 Surface Extra-solar Surfac...
lm2940.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: LM2940/LM2940C 1A Low Dropout Regulator January 2007 LM2940/LM2940C 1A Low Dropout Regulator General Description The LM2940/LM2940C positive voltage regulator features the ability to source 1A of output current with a dropout voltage of typically 0...
LTA-1000G-GreenLEDDisplay.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: ! \" # $ # %+ ,( ),)1 2\'(30)1 22 , ) 4),\', 6,\'.%* (/,-7/\',4\'-( ., 9)2& ,9 ) + )...
lm2937.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: LM2937 500 mA Low Dropout Regulator August 2005 LM2937 500 mA Low Dropout Regulator General Description The LM2937 is a positive voltage regulator capable of supplying up to 500 mA of load current. The use of a PNP power transistor provides a low d...
MMA7260Q-Rev1.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: Freescale Semiconductor Technical Data MMA7260Q Rev 1, 06/2005 1.5g - 6g Three Axis Low-g Micromachined Accelerometer The MMA7260Q low cost capacitive micromachined accelerometer features signal conditioning, a 1-pole low pass filter, temperature c...
ee100Fa08-Lab7-BoostConverter.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: EECS 100 Boost Converter Laboratory L. Chua University of California Berkeley Department of Electrical Engineering and Computer Sciences EECS 100, Professor Leon Chua LABORATORY 7 v3 BOOST CONVERTER In many situations circuits require a differen...
ee100Fall2008-hw13.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: Fill out information below and attach this cover sheet to the FRONT of your HW. If you do not (or enter incorrect information) you WILL loose 10 points on the HW. NAME:_ SID #:_ Circle One: EE42 / EE100 If EE100, Lab Day:_,Time:_ EE 100 Homework # 1...
exam1sol.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: ...
prelab11.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: EE 43/100 - Final Project Audio Amplifier, Part II EE43 Fall 2005 Project: 1: Audio Amplifier, Part II EE 43/100 FINAL PROJECT: AUDIO AMPLIFIER EE 43 PROJECT 1: AN AN AUDIO AMPLIFIER Part 2: Audio Amplifier Prelab Amplifier Block Diagram In this l...
final_review_notes_problems.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: EECS 100 Fall 2004 REVIEW PROBLEMS FOR THE FINAL Muthuswamy, Bharathwaj I. Introduction 1. There are a total of 14 problems in this review handout. Problems 1 through 3 serve as review of basic material. The final exam is going to concentrate on p...
HW01.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: ...
JustinReviewProblems.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: ...
EveningMidtermSolutionsGradingScheme.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: ...
Hw1_EE100-sol.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: EE 100/42 Spring 2009 Solutions to Homework 1 1.9 The positive reference for V is terminal b, where the head of arrow is pointing. Then, we have V V 12V. Also, i is the current entering terminal a, and i is the current leaving terminal a. Then, we ha...
ch06.pdf
Path: Berkeley >> EE >> 06 Fall, 2009
Description: ...
ch06.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: ...
midterm_solutions.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: EE100 Summer 2004 Midterm Solutions ...
final_solutions.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: ...
ch05.pdf
Path: Berkeley >> EE >> 05 Fall, 2008
Description: ...
ch05.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: ...
toolbox.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: ...
rc-guide.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: EECS 100 RC Circuits EE100 Lab 3 Experiment Guide: RC Circuits I. Introduction A. Capacitors A capacitor is a passive electronic component that stores energy in the form of an electrostatic field. The unit of capacitance is the farad (coulomb/volt)...
hw1su.pdf
Path: Berkeley >> EE >> 100 Fall, 2008
Description: ...
