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- Title: hw3
- Type: Notes
- School: Berkeley
- Course: CS 150
- Term: Fall
Coursehero >> California >> Berkeley >> CS 150
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
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Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 150 Fall, 1996
Path: Berkeley >> CS >> 4 Fall, 2008
Path: Berkeley >> CS >> 150 Fall, 1996
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Path: Berkeley >> EE >> 221 Fall, 2008
Path: Berkeley >> EE >> 221 Fall, 2008
Path: Berkeley >> EE >> 221 Fall, 2008
Path: Berkeley >> EE >> 221 Fall, 2008
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of University California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 Spring 2003 Homework #3 This homework is due on Thursday February 13th . Homework will be accepted in the EECS150 homework slot in the cabinet to the right of the main door into 125 Cory. Late homework will be penalized by 50%. No late homework will be accepted after the solution is posted. J. Wawrzynek 1. Multi- level logic. a) Consider the following function expressed in two-level and/or form. Using algebraic manipulation, express the function in three- level or/and/or form: F = ac + ad + bc + bd + e b) Now assume that you can only use two- input and and or gates to implement this function. For both the two-level and the three- level forms, determine the cost in transistors, and the delay in terms of gate delay . 2. From Mano: Problems 3-1, 3-8, 3-12, 3-13, 3-14, 3-15, 3-23. 3. A function F is defined by the true table below. Write F in reduced product-of-sums form using a K-map. abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1100 1011 1101 1110 1111 F 1 1 0 0 0 1 X 1 X 1 1 0 1 X 0 0 ab cd 4. Translate the following verilog code into gates. Some of the code are not completely correct. Correct any minor error that you find. Hint: you may use the synthesis program Syplify Pro on the lab computers to catch the errors or to verify that your translation is correct. a) Module A (a, b, c, d) input a; input [3:0] b, c; output [3:0] d; assign d = endmodule b) Module B (e, f, g, h) input e; input f; input g; output d; always @ (f, g, h) begin if (e) h = f | g; else h = f & g; end endmodule c) Module C (a, b, c, d) input [1:0] a; input [3:0] b, c; output [3:0] d; wire [3:0] x; assign x = c ^ b; always @ (a, b, c) case (a) 2 b00: d = 5; 1: d = ~b; 2: d = x; endcase endmodule a ? ~b : c; 5. In verilog there are many ways of expressing the same circuit. For the following parts please write simple verilog code for the expression: Y = ac + bd + a c d a) Structural description using and() and or() modules. b) Behavior description using assign statements. c) Behavior description using always block.
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lab1Slides.pdf
Path: Berkeley >> CS >> 150 Fall, 1996
Description: EECS 150 Spring 2003 Lab Lecture 1 Instrumentation 1/23/2003 Sandro Pintz (including work from others) Oscilloscopes Can show analog signals and digital signals from CUT (Circuit Under Test) Very good for signal quality, delays, etc Graph of Volta...
quiz2spring03sol.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek & J. Sampson Spring 2003 Quiz #2 Solution (explanations on next page) Name: __ SID: _Lab section number: _ Gi...
quiz11spring03sol.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley EECS EECS150 Spring 2003 Quiz #11 solution Name: _ SID: _Lab section number: _ To first approximation, under a limited voltage range, a reduction in power supply voltage (Vdd) in MOS circuits results in a linear i...
lec8-synthesis.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 10 Logic Synthesis February 13, 2003 John Wawrzynek Spring 2003 EECS150 Lec8-synthesis Page 1 Logic Synthesis Verilog and VHDL started out as simulation languages, but quickly people wrote programs to automatic...
F02-exam1.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 Fall 2002 J. Wawrzynek 9/27/02 Exam I Name:_ ID number:__ This is a closed-book, closed-note exam. No calculators please. ...
lec28-FFs.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 28 More Flip-flops May 1, 2003 John Wawrzynek Spring 2003 EECS150 Lec28-FFs Page 1 Cross-coupled NOR gates R remember, S If both R=0 & S=0, then cross-couped NORs equivalent to a stable latch: NOR 00 1 01 0...
F02-exam3.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 Fall 2002 J. Wawrzynek 12/6/02 Exam III Name:_ ID number:__ This is a closed-book, closed-note exam. No calculators please...
lec31-review3.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 31 Review 3 May 8, 2003 John Wawrzynek Spring 2003 EECS150 Lec31-review3 Page 1 Outline Announcements/reminders List of exam topics Detailed discussion of previous exam Please ask questions throughout! Spri...
lec02-cmos.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 2 - CMOS January 23, 2003 John Wawrzynek Spring 2003 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor circuits basic logic gates tri-s...
quiz9spring03sol.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley EECS EECS150 Spring 2003 Quiz #9 solution Name: _ SID: _Lab section number: _ A certain datapath has four computation units, , , , and . Each computation unit requires an entire clock cycle (minus flip-flop overhe...
lec29-asynch.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 29 - Asynchronous Sequential Circuits May 6, 2003 John Wawrzynek Spring 2003 EECS150 - Lec29-asynch Page 1 Outline Synchronizers Figures from Digital Design, John F. Wakerly Prentice Hall, 2000 An excellent treat...
lec17-mem2.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 17 Memory 2 March 18, 2003 John Wawrzynek Spring 2003 EECS150 Lec17-mem2 Page 1 SDRAM Recap General Characteristics Optimized for high density and therefore low cost/bit Special fabrication process DRAM rare...
projectSpec1.0.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE EECS-150 FINAL PROJECT SPRING 2003 Change notes: Date 2/26/03 Name Sandro Pintz Version Description 1.0 First Release Introduction...
F02-exam2.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 Fall 2002 J. Wawrzynek 11/1/02 Exam II Name:_ ID number:__ This is a closed-book, closed-note exam. No calculators please....
hw7sol.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 Spring 2003 Homework #7 Solutions J. Wawrzynek 1. Delay: O(log n) Cost: O(n) 2. 30 4-LUTs. 3. a) 3, 4, 5, 6, 7, 7 b) Del...
lec03-fpga.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) January 28, 2003 John Wawrzynek Spring 2003 EECS150 - Lec03-FPGA Page 1 Transistor-level Logic Circuits Positive Level-sensitive latch Transistor Level clk Positiv...
lec17-mem2-4up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: SDRAM Recap General Characteristics Optimized for high density and therefore low cost/bit Special fabrication process DRAM rarely merged with logic circuits. Needs periodic refresh (in most applications) Relatively slow because: High capacity ...
lec10-timing-4up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: Outline General Model of Synchronous Systems Performance Limits EECS150 - Digital Design Lecture 10 - Timing February 20, 2003 John Wawrzynek Delay in logic gates Delay in wires Clock Skew Delay in flip-flops Spring 2003 EECS150 Lec10-Tim...
quiz5spring03sol.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley EECS EECS150 Spring 2003 Quiz #5 Solution Name: _ SID: _Lab section number: _ J. Wawrzynek & J. Sampson Design a circuit that takes one-cycle pulses in a 25Mhz clock domain and translates them to one-cycle pulses...
lec20-fsm2-4up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: Outline Moore versus Mealy style state machines. FSM optimization EECS150 - Digital Design Lecture 20 - Finite State Machines 2 April 3, 2003 John Wawrzynek State Reduction State Assignment Spring 2003 EECS150 Lec20-fsm2 Page 1 Spring 2003...
lec29-asynch-2up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 29 - Asynchronous Sequential Circuits May 6, 2003 John Wawrzynek Spring 2003 EECS150 - Lec29-asynch Page 1 Outline Synchronizers Figures from Digital Design, John F. Wakerly Prentice Hall, 2000 An excellent treat...
lec27-2up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: Linear Feedback Shift Registers (LFSRs) These are n-bit counters exhibiting pseudo-random behavior. Built from simple shift-registers with a small number of xor gates. Used for: random number generation counters error checking and correction Q4...
lec06-hdl1-2up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 6 - Hardware Description Languages February 6, 2003 John Wawrzynek Spring 2003 EECS150 - Lec06-HDL Page 1 Outline Netlists Design flow What is a HDL? Verilog history examples Spring 2003 EECS150 - Lec06-HD...
lec13-cl1.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 11 - Combinational Logic Circuits Part 1 - Adders March 4, 2003 John Wawrzynek Spring 2003 EECS150 - Lec13-cl1 Page 1 Adders Full-adder cell (FA) revisited: a bcin a b cin cout s 000 0 0 001 0 1 010 0 1 011 1 0 10...
lec24-HL4-4up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: Simple CPU-core Example Why study CPU cores? 1. Another large design example. 2. More experience with RTL descriptions. 3. A classic controller + Data-path type design example. 4. Novel controller implementation: micro-programming. 5. Complements pr...
lec01-intro-2up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 Components and Design Techniques for Digital Systems John Wawrzynek (Warznek) Professor of EECS johnw@eecs.berkeley.edu 643-9434 631 Soda Hall Office hours: Tu, Th 1-2 Sandro Pintz Visiting Instructor Teaching Assistants: Jack Sampson Norm Z...
lec23-HL3-4up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: Parallelism Parallelism is the act of doing more than one thing at a time. Optimization in hardware design often involves using parallelism to trade between cost and performance. EECS150 - Digital Design Lecture 23 - High-level Design and Optimizati...
hw2sol.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 Homework #2 Solutions 1. Problems from Mano. 2. The equality to be proved is: ab + cd = (ab)(c...
lec01-intro.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 Components and Design Techniques for Digital Systems John Wawrzynek (Warznek) Professor of EECS johnw@eecs.berkeley.edu 643-9434 631 Soda Hall Office hours: Tu, Th 1-2 Sandro Pintz Visiting Instructor Teaching Assistants: Jack Sampson Norm Z...
hw1sol.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 Spring 2003 Homework #1 Solutions 1. Problems from Mano\'s book: 10-13. (a) Four-input NAND CMOS gate J. Wawrzynek A B C ...
week12Slides.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS 150 Spring 2003 Lab Lecture 10 Final Project I 4/10/2003 Sandro Pintz Asynchronous Clock Crossings The world is Asynchronous 100% chance to encounter issues No Exhaustive Simulation Possible Failures could be very sporadic and environmentally ...
lab2Writeup.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Lab 2 FPGA CAD Tool Flow 1. Motivation In this lab you will take a simple design through the FPGA Computer Aided Design (CAD) tool...
hw3sol.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 Spring 2003 Homework #3 Solutions 1. a) F = ac + ad + bc + bd + e = a(c + d) + b(c + d) + e = (a + b)(c + d) + e Two-level ...
lec23-HL3-2up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 23 - High-level Design and Optimization 3, Parallelism and Pipelining April 15, 2003 John Wawrzynek Spring 2003 EECS150 - Lec23-HL3 Page 1 Parallelism Parallelism is the act of doing more than one thing at a time....
Lab4.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 Spring 2007 UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE ASSIGNED: DUE: Week of 2/11 Week of 2/18, 10 minutes after start (xx:20) of your assigned lab section. Lab 4 L...
lec17-mem2.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 17 Memory 2 October 22, 2002 John Wawrzynek Fall 2002 EECS150 Lec17-mem2 Page 1 SDRAM Recap General Characteristics Optimized for high density and therefore low cost/bit Special fabrication process usually o...
lec01-intro-6up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 Components and Design Techniques for Digital Systems John Wawrzynek (Warznek) Professor of EECS johnw@eecs.berkeley.edu 643-9434 631 Soda Hall Office hours: Tu, Th 1-2 Teaching Assistants: Vinay Krishnan Liang Teck Pang Yury Markovskiy Yatish...
lec13-cl-2up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 13 - Combinational Logic & Arithmetic Circuits Part 3 October 8, 2002 John Wawrzynek Fall 2002 EECS150 - Lec13-cla3 Page 1 Multiplication a3 b3 X a3b1 a2b2 a1b3 a3b0 a2b1 a1b2 a0b3 . a2 b2 a2b0 a1b1 a0b2 a1 b1 a1b...
lec20-fsm2-2up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 20 - Finite State Machines 2 October 31, 2002 John Wawrzynek Fall 2002 EECS150 Lec20-fsm2 Page 1 Outline Moore versus Mealy style state machines. FSM optimization State Reduction State Assignment Fall 2002 ...
lec23-HL3-2up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 23 - High-level Design and Optimization 3, Parallelism and Pipelining Nov 12, 2002 John Wawrzynek Fall 2002 EECS150 - Lec23-HL3 Page 1 Parallelism Parallelism is the act of doing more than one thing at a time. Opt...
lec27-asynch-2up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 27 - Asynchronous Sequential Circuits Nov 26, 2002 John Wawrzynek Fall 2002 EECS150 - Lec27-asynch Page 1 Outline SR Latches and other storage elements Synchronizers Figures from Digital Design, John F. Wakerly ...
lec11-cl1-2up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 11 - Combinational Logic Circuits Part 1 - Adders October 1, 2002 John Wawrzynek Fall 2002 EECS150 - Lec11-cl1 Page 1 Adders Full-adder cell (FA) revisited: a bcin a b cin cout s 000 0 0 001 0 1 010 0 1 011 1 0 10...
lec03-timing.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 3 - Timing September 3, 2002 John Wawrzynek Fall 2002 EECS150 - Lec03-Timing Page 1 Outline Finish up from lecture 2 General Model of Synchronous Systems Performance Limits Announcements Delay in logic...
lec08-hdl1.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 8 - Hardware Description Languages September 19, 2002 John Wawrzynek Fall 2002 EECS150 - Lec08-HDL Page 1 Outline Netlists Design flow What is a HDL? Verilog history examples Fall 2002 EECS150 - Lec08-HDL ...
lec23-HL3-4up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: Parallelism Parallelism is the act of doing more than one thing at a time. Optimization in hardware design often involves using parallelism to trade between cost and performance. EECS150 - Digital Design Lecture 23 - High-level Design and Optimizati...
Checkpoint2.5.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 Spring 2008 Checkpoint 2.5 UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE CHECKPOINT 2.5 FOUR PORT ARBITER AND USER INTERFACE 1.0 MOTIVATION Please note that this check...
Lab1.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150: Lab 1, FPGA CAD Tools UC Berkeley College of Engineering Department of Electrical Engineering and Computer Science 1 Time Table Friday, August 29th Week 3: September 7th 13th , 10 minutes after your lab section starts ASSIGNED DUE 2 Mo...
lec05-verilog.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 - Digital Design Lecture 4 - Verilog Introduction Feb 3, 2009 John Wawrzynek Spring 2009 EECS150 - Lec05-Verilog Page 1 Outline Background and History of Hardware Description Brief Introduction to Verilog Basics Lots of examples struc...
Homework4Solutions.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 Homework4Solutions Fall2008 Problem1:Youhavea100MHzclock,andneedtogenerate3separateclocksat differentfrequencies:20MHz,1kHz,and1Hz.Howmanyflipflopsdoyouneedto implementeachclockifyouuse: a)aringcounter? b)abinarycounter? Showanexampleofeac...
chk_pt4rev.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS 150 Fall 2000 R. Katz N. Zhou Checkpoint 4 Packet Transmission Reception 1 Objective For this checkpoint you will make additi...
Midterm2Solutions.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 Midterm2Solutions Fall2008 1)Shortanswerquestionsontheproject: a) GiventhefollowingsynthesismessagefromSynplifyPro: @W:CG133:\"C:\\Test.v\":26:15:26:19|NoassignmenttoIfOut Isthissynthesismessageanote,awarning,oranerror?WhatlineinTest.v trig...
lec05-FSM.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS 150 - Components and Design Techniques for Digital Systems FSMs 9/11/2007 Sarah Bird Electrical Engineering and Computer Sciences University of California, Berkeley Slides borrowed from David Culler Fa04 and Randy Katz Sp07 Sequential Logic Im...
lec26-misc1-6up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: Endgame Today: Miscellaneous 1 clock skew multi-port memory FIFOs, implementation version 1 EECS150 - Digital Design Lecture 26 - Miscellaneous 1 April 30, 2002 John Wawrzynek Thursday 5/2: Miscellaneous 2 FIFO version 2 LFSR Division ...
lab2.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: EECS150 Spring 2002 Lab 2 Logic Gates UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 2 Logic Gates 1 Motivation In this lab you will get to build and test a simple combinat...
lab7.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences CS 150 Fall 1998 Lab 7 Wire-Wrap and SRAMS J. Wawrzynek and N. Weaver Later revisions by R. Fearing, X. Zhang, and B. Choi 1 Obj...
lab6.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: 8QLYHUVLW\\ RI ROOHJH RI (QJLQHHULQJ \'HSDUWPHQW RI (OHFWULFDO (QJLQHHULQJ DQG 6 6SULQJ - :DZU]\\QHN DQG 1 :HDYHU 5HYLVHG E\\ 5 )HDULQJ DQG & (QJ /DE 1DVW\\ 5HDOLWLHV 2EMHFWLYHV )RU WKLV ODE \\RX ZLOO OHDUQ...
check2.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 Fall 1998 R. Fearing and Kevin Cho Checkpoint 2 Video Interface 1. Objective In this checkpoint, you will: 1. Wire-up the ...
check1.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS 150 Fall 1998 Checkpoint 1 Serial Transmitter J. Wawrzynek and N. Weaver Later revisions by R. Fearing, J. Shih and D. Chinn...
soln7-12.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: Problem 7.12 The sequence for the Johnson counter gives a state transition table which looks like this: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q3 Q2 Q1 Q0 Q3+ Q2+ Q1+ Q0+ 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 x x x x 0 0 1 1 0 0 0 1 0 1 0 0 x x x ...
soln7-12.pdfPath: Berkeley >> CS >> 4 Fall, 2008
Description: Problem 7.12 The sequence for the Johnson counter gives a state transition table which looks like this: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q3 Q2 Q1 Q0 Q3+ Q2+ Q1+ Q0+ 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 x x x x 0 0 1 1 0 0 0 1 0 1 0 0 x x x ...
week8_1_6up.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: Outline m Last time: Introduction to number systems: sign/magnitude, ones complement, twos complement Review of latches , flip flops, counters Clocked Synchronous Finite-State Machines m Example: Consider the student association coffee vending mac...
soln7-10.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: Problem set 4 solutions 7.10 Were designing a counter that counts from 0 to 9 and returns to 0, so well implement with 4 bits, and encode the states in binary. Because we only need 10 states, well have six rows of dont care, which will make the imple...
soln7-10.pdfPath: Berkeley >> CS >> 4 Fall, 2008
Description: Problem set 4 solutions 7.10 Were designing a counter that counts from 0 to 9 and returns to 0, so well implement with 4 bits, and encode the states in binary. Because we only need 10 states, well have six rows of dont care, which will make the imple...
soln3-2.pdfPath: Berkeley >> CS >> 150 Fall, 1996
Description: 3.2a) F= a\\b\\c+\\ac+\\ab A \\B \\C \\A C \\A B 3.2b) F=(\\a+\\b+\\c)(\\a+\\b) (\\a+\\c) \\A \\B \\C \\A \\B A B C A B \\A \\C A C 3.2c) F=\\ab+a+\\c+\\d \\A B A \\C \\D \\A B \\A C D ...
soln3-2.pdfPath: Berkeley >> CS >> 4 Fall, 2008
Description: 3.2a) F= a\\b\\c+\\ac+\\ab A \\B \\C \\A C \\A B 3.2b) F=(\\a+\\b+\\c)(\\a+\\b) (\\a+\\c) \\A \\B \\C \\A \\B A B C A B \\A \\C A C 3.2c) F=\\ab+a+\\c+\\d \\A B A \\C \\D \\A B \\A C D ...
midterm_solutions.pdfPath: Berkeley >> EE >> 221 Fall, 2008
Description: EECS 221 A Part A: Denitions Midterm Solutions Fall 2008 (a) A matrix P Cnn is called positive denite if (i) P = P (Hermitian) and (ii) for all v = 0, we have v P v > 0. (b) The Cauchy-Schwartz inequality asserts that is an inner-product space ...
sol5.pdfPath: Berkeley >> EE >> 221 Fall, 2008
Description: EECS 221 A 1 (a) Let f (x, t) = x1 + et cos(x1 x2 ) x2 + 15 sin(x1 x2 ) Solutions # 5 (1) then, given a xed time t, the Jacobian of f is: J(x) = 1 et sin(x1 x2 ) et sin(x1 x2 ) 15 cos(x1 x2 ) 1 15 cos(x1 x2 ) (2) and its innity induced no...
hw1.pdfPath: Berkeley >> EE >> 221 Fall, 2008
Description: EECS 221 A Issued: September 5, 2008 Assignment # 1 Due: September 12, 2008 1 Vector Spaces Determine conclusively which of the following are elds: (a) GLn = the set of all n n nonsingular matrices. (b) GF2 = the set {0, 1} with addition being bin...
sol9.pdfPath: Berkeley >> EE >> 221 Fall, 2008
Description: EECS 221 A 1 Consider the system x = Ax + Bu, where: 3 6 13 7 B= 1 A = 2 4 2 1 2 4 3 (a) Lets compute the controllabitlity matrix: 3 2 5 C = B AB A2 B = 1 0 2 1 1 1 thus rank(C) = 3 and the pair (A, B) is controllable. Solutions # 9 ...
closedloop.pdfPath: Berkeley >> EE >> 221 Fall, 2008
Description: EECS 221 A A State Feedback B Observers C Output Feedback D Integral Error Feedback E Gain Scheduling LTI Systems: Feedback Aspects 1 A. State Feedback 1 Introduction We begin with the transfer function H(s) of some m input, p output linear time...