Coursehero >> California >> Berkeley >> CS 150

Course Hero has millions of student submitted documents similar to the one below including study guides, homework solutions, papers, exam answer keys and textbook solutions.

150 EECS Midterm 2 Solutions Fall 2008 1) Short answer questions on the project: a) Given the following synthesis message from Synplify Pro: @W: CG133 :"C:\Test.v":26:15:26:19|No assignment to IfOut Is this synthesis message a note, a warning, or an error? What line inTest.v triggered this message? This is a synthesis warning triggered by line 26. 2 points total: 1 point for recognizing this was a synthesis warning 1 point for recognizing it was triggered by line 26 b) Name one potential problem if you write the following piece of code: input wire [31:0] A; input wire [31:0] B; output wire [63:0] C; assign Out = (A * B) / C + A % 5 As you may have learned in lecture by now, multipliers and dividers take extremely sophisticated combinational logic to implement. Thus, the critical path delay of your design so long that the place and route tools have no hope to get your design to meet timing at any reasonable frequencies. Some answers also accepted for full credit include Out being defaulted to a 1-bit wire due to lack of declaration and missing semicolon. 2 points total: 2 points for any of the answers above 1 point if you added stuff that did not make sense, even if you had one of the answers above c) If your place and route process is taking an extremely long time, what kinds of things might you want to look at first before you look at your code? Place and Route report, critical path, synthesis report and RTL schematic all received full credit. 2 points total: 2 points for any of the answers above 1 point if you added stuff that did not make sense, even if you had one of the answers above Page 1 of 13 EECS 150 Midterm 2 Solutions Fall 2008 d) Is there a known number of cycles of delay between the video encoder's address output and the data input? Why/why not? No, the number of cycles of delay between the video encoder s address output and data input is unknown. This is because the address counter is allowed to request addresses independently of the video encoder FSM. When we hit a blanking region, there could be hundreds or thousands of cycles between when the address is first requested and when the video encoder actually takes the data. 3 points total: 1 point for recognizing that the number of cycles is unknown 2 points for a reasonable explanation of why it is unknown e) Why is it absolutely pointless to look at the Clock signal in Chipscope? Chipscope always samples its data or trigger inputs on the positive edge of the Clock input. Thus, if you put in the Clock signal as a data or trigger input into Chipscope, you will always see a constant value. 3 points total: 3 points for saying that Chipscope samples on the Clock or that the value you see will be a constant 1 point for adding anything that did not make sense, even if you had the right answer f) Why are there two address counters inside of the Video Encoder? What is the purpose of each? The first address counter is in charge of sending addresses, to either VideoROM or the Arbiter, in order to request active video data for future use by the Video Encoder. The second address counter decides which signals to sent to the Video Encoder chip, such as EAV, SAV, blanking, or active video. We did not accept the answer of the two counters being an AddressLine and an AddressPair counter, as it is clearly defined that a single address counter consists of both a line and a pair counter. 3 points total: 3 points for correctly describing the differences between the two counters 1 point for adding anything that did not make sense, even if you had the right answer Page 2 of 13 EECS 150 Midterm 2 Solutions Fall 2008 2) Assume that you have an SRAM organized as 256x8 with CS and WE control inputs (similar to the one in CLD2). The SRAM contains 256 unsigned integers. Design a system to count the number of integers in the SRAM which are greater than the MEAN of all the integers in the SRAM. This count should be written into memory location 0x0F. The system should start this operation when a GO line is asserted, and it should stay in an idle state and assert DONE when the result is ready. You may use one 16 bit adder in your design. You may need to take 2 passes through the SRAM. Think carefully about how you calculate the mean. Try to be efficient (e.g. do not build a separate comparator use the adder). a) Clearly show the components and wiring of the datapath. In addition to the adder and SRAM, you may use registers, counters, MUXes, and logic gates. Clearly indicate the width of all registers, busses, etc. At a high level, we need to compute the mean (average) of all numbers in memory, and then count the integers greater than this mean. As a first step, consider how an average is calculated. To take the average of 256 numbers, we need to take their sum and divide by 256. This operation maps to hardware nicely due to the fact that we are working with powers of two: First, we need to read 256 unsigned 8 bit integers from SRAM. We need to assert Chip Select (CE), de assert Write Enable (WE), and iterate through the entire 8 bit address space (An SRAM containing 256 addressable locations will have an 8 bit address). A trivial way to iterate through all possible values of an 8 bit wire is to use an 8 bit counter. The values read out of the SRAM will appear sequentially on a bidirectional DQ bus. Recall that we can compute the running sum of a stream of numbers using an accumulator circuit (refer to early homework assignments). The register is crucial in this circuit, as it prevents a combinational loop, a condition that almost always results in erroneous behavior (See for yourself using ModelSim). Another important note is the extended range of the accumulator. If we sum 256 8 bit unsigned integers and store the result in an 8 bit register, we may lose data due to overflow. Luckily, a 16 bit adder and register are available to us, so we can avoid this issue by extending the range of our numbers from 8 bits to 16 bits. The last step in computing the mean is division. Our accumulator register stores the sum of the 256 numbers contained in SRAM, so to find the average we must divide this sum by 256. Normally, division in hardware is a messy thing, but fortunately we only need to divide by a power of two (256 = 28). Dividing by powers of two in binary is akin to dividing by powers of 10 in the decimal system: we can simply shift to the right. Division by 256 of a 16 bit number in binary comes down to taking the high order byte, and throwing away the low order byte a circuit that involves no logic! Page 3 of 13 EECS 150 Midterm 2 Solutions Fall 2008 There is no need to use another register to store the mean. We can simply use the sum stored in the accumulator because we do not need to change this value once it is computed. We now need to count the number of integers in SRAM greater than the mean. We can re use the address counter to iterate through every integer in memory. This will, again, give us a stream of integers which we need to compare to the mean. To accomplish this, we need a means of comparing two integers. We need not build a comparator circuit because an adder can be used for this purpose. An integer of interest will produce a negative number when we subtract it from the mean. Recall that an adder can be used to subtract two s complement integers due to the number representation. 8 bit unsigned integers are identical to a two s complement representation when extended to 16 bits, so to build a subtractor we simply need to negate the extended integers from SRAM (invert all bits and add 1 using the adder s carry input). The comparison output is the top bit of the result, which determines whether the output is negative. In short, we can use the Neg output of an adder/subtractor circuit as the result of our comparison. Students were not expected to build this circuit, and were instead allowed to use the ALU block as shown above. A counter can be used to count (amazingly) conditionally by controlling the enable input. We would like to increment the counter every time we come across a number greater than the mean. In other words, we would like to increment every time the output of the adder is negative while iterating through memory for the 2nd time. The count will be at most 256 (actually far less), so an 8 bit counter can be used for convenience. Page 4 of 13 EECS 150 Midterm 2 Solutions Fall 2008 Finally, after iterating through the SRAM twice, we have obtained the number of all integers in SRAM greater than the mean. This count is stored in the counter. We need to write this 8 bit integer into the SRAM at location 0xFF, so we need a MUX it in at the SRAM s address input (see datapath diagram). We need to assert Chip Select (CE), assert Write Enable (WE), and place the counter output on the DQ bus. We will allow two cycles for a write because asserting WE on the same cycle the address is asserted can lead to a bad write into the SRAM. The last challenge in the problem comes from dealing with the bidirectional nature of this bus. The word bidirectional usually implies tristate buffer (refer to Checkpoints 2 and 3). In fact, we need one for the input from SRAM. There are a few optimizations we can perform on the datapath described above. We never need to de assert Chip Select (CE), so there s no need for using a control signal to control this port. Similarly, the address counter never needs to be disabled. Several control inputs to datapath can be tied to one control signal. We can tie the tristate control, and the address MUX select bit to a WriteBack control signal (see datapath and control diagrams). Similarly, we can use a Counting signal to control the ALU MUX, the counter s enable, and the ALU s Sub input. we Finally, can use the GO signal to reset all state in our datapath and re start our control. It is essential not to forget to assert the DONE signal once the datapath has completed its task. We used an AddressFF signal (address counter about to roll over this is just the normal RCO of the counter) to simplify control logic. The complete datapath diagrams follows: b) List the control lines in the datapath. Our solution had the following lines driven by the control: WriteBack Page 5 of 13 EECS 150 Midterm 2 Solutions Fall 2008 WE Counting Accumulate Increment DONE (These signals are marked in red on the datapath above). The inputs to the control were Go, Neg, and AddressFF. c) Draw a state diagram of the controller for the system. This part of the problem comes down to tracing your system s behavior starting with the Go signal. See when the control signals in part b) need to change based on the control inputs. The bubble arc diagram should be a Moore machine, and should have all transitions and outputs labeled. A good way to label the outputs is through an output table where each state and its corresponding output values are tabulated. State \ Signal Accumulate Accumulating 1 b1 Counting 1 b0 Page 6 of 13 WriteBack 1 b0 WE 1 b0 Done 1 b0 EECS 150 Midterm 2 Solutions Fall 2008 Counting 1 b0 1 b1 1 b0 1 b0 1 b0 WriteBack 1 1 b0 1 b0 1 b1 1 b0 1 b0 WriteBack 2 1 b0 1 b0 1 b1 1 b1 1 b0 Done 1 b0 1 b0 1 b0 1 b0 1 b1 The Increment control signal can be tied to (Neg & Counting) Note: Some outputs in this table can be replaced with don t cares. Grading: We recognize the difficulty of coming up with a clean, optimal datapath and control in a midterm setting. We therefore considered a number of factors including the quality of your datapath and state diagrams, clear presentation of design, rather than the sheer correctness of your solution. The problem is worth 25pts, distributed as follows: a) 10 points +2 for a datapath reasonably fit for the task in the problem statement. Up to a maximum of 3 points for clarity of the datapath diagram: 3 points for a clear, well labeled datapath diagram. 2 points for a diagram lacking some of: bus widths, key labels on signals and busses, clearly shown connections, or clear labels on datapath elements. 1 point for a diagram lacking many of: bus widths, key labels on signals and busses, clearly shown connections, or clear labels on datapath elements. 0 points for something that isn t a datapath diagram. Up to a maximum of 5 points for key concepts illustrated in the datapath: +1 for an 8 bit SRAM address counter. +1 for a MUX on the SRAM addresses line, selecting address 0x0F. +1 for tristate gate on the SRAM DQ bus. +1 for zero padding to extend the 8 bit memory output to 16 bits. +1 for a 16 bit register used with the ALU/Adder as an accumulator. +1 for the use of the ALU/Adder as comparator using the Negative flag. +1 for the clear, correct use of the ALU/Adder as a subtractor. +1 for an 8 bit counter to count integers greater than the mean. +1 for the use of a bit shift (clearly illustrated) as a divider. b) 5 points +2 for a list in agreement with the datapath in part a. +2 for a list in agreement with the state outputs in part c. +1 for a reasonably correct list of control signals, including DONE. c) 10 points Page 7 of 13 EECS 150 Midterm 2 Solutions Fall 2008 +2 for labeled transitions in the state machine diagram. +1 for unambiguous transitions and transition conditions. +2 states have defined outputs (within the state diagram, or tabulated). +2 state outputs correspond to the control signals shown in a) and b) +3 if control allows the task in the problem statement to be completed given the control signals shown in a) and b). Page 8 of 13 EECS 150 Midterm 2 Solutions Fall 2008 3) Any specifics refer to the SDRAM on the Calinx II boards. a) Why is the bit storage array square? Specifically, why not have either 16 bit words to avoid having to multiplex from words to columns, or have 16 words and more columns per word? There are two main reasons to make the bit array square (2 points each): 1) Improve the geometry on the chip. Lots of square blocks are easier to place on the IC than the long skinny blocks you would have if you did not multiplex the words to columns, or if there were only 16 words. 2) A square bit array also allows for reasonably a reasonably sized address decoder and column MUX. Specifically, the bit array of the Micron SDRAM is (8192 rows) x (512 columns) x (16 bits per column). If instead we had 16 bit words (essentially just a single column), we would need to have 4,194,304 outputs from the address decoder! That would require 22 address bits instead of 16, which also increases the cost of the chip since external pins are very costly. On the other hand, having only 16 words means we would need 262,144 columns with 16 bits/column. If we can t get through a 512:1 MUX in one clock cycle, think how bad the performance would be with a 262,144:1 MUX b) Why do SDRAMs have a row register, when SRAMs do not? (2 points) SDRAMs need a row register because Reads are destructive. SDRAM stores data on a capacitor, and Reading the data drains that charge off the capacitor when it is connected to the bit line through the access transistor. Therefore, we need the Row Register to store the data as soon as it is read out so we don t lose the data. SRAM reads are not destructive, so a Row Register is not needed. If you said the row register is necessary for the refresh operation, you got one point. c) What is the purpose of the refresh counter? Describe its effect on the bit array. (4 points) The refresh counter cycles through all the addresses of the SDRAM so all the rows can be refreshed. The counter keeps track of the next row that will be refreshed. SDRAM data is stored on a capacitor, and the charge on that capacitor leaks off with time. In order to prevent data loss, the charge on the capacitor needs to be refreshed periodically. During a Refresh, the refresh counter provides the address to select a row. That row of data is read into the Row Register, then written back into the same address. Page 9 of 13 EECS 150 Midterm 2 Solutions Fall 2008 DO NOT: Draw 32 copies of the same thing Draw a bubble that says control Put control logic in your datapath List control signals that aren t asserted in state diagram Hook problem inputs (i.e. READ) directly to control inputs (e.g. LD_ADDR) Instead, use your FSM! Page 10 of 13 EECS 150 Problem #4 Midterm 2 Solutions Fall 2008 This problem asked you to create a 16 bit Carry Lookahead Adder (CLA). Henceforth, Lookahead will be abbreviated LA. Points were assigned as follows: 1. (+10 points) Draw any additional layers and wiring a. +2 for drawing the second LA block on the second LA level (LA #5 in the diagram). b. +2 for drawing the last LA block (LA #7 in the diagram). c. +6 wires i. +2 for the wires connecting each adder block ii. +2 for connecting the wires related to LA #5. iii. +2 for connecting the wires related to LA #7. Full credit (+2) given for drawing all wires related to each part. Partial credit (+1) given if some wires were missing. No credit (+0) given if most/all wires were missing/going into the wrong place. 2. (+4 points) Write down CLA block equations: +1 was given for each correct equation. No partial credit was given for any partially correct equation. 3. (+16 points) Write down at what time the Sum and Carry outputs are generated. +1 was given for each correct Sum value +1 was given for each correct Carry value 3 was deducted if you thought the P and G arrived from the Sum blocks @ time 1. Although this is the book s convention, the problem clearly stated that P and G are generated two gate delays after the arrival of A and B 3 was deducted for other time shift errors. In other words, if you missed one time value and all of your other time values were shifted over by the corresponding amount, you lost 3 instead of 7 points. o This rule only applies if this was your only error (i.e. if the time values that depended on your error were only shifted by the one incorrect time value). If you had other errors on Page 11 of 13 EECS 150 Midterm 2 Solutions Fall 2008 top of the time shift error, you lost the full 1/incorrect time. +2 was given by default if you had at least one correct sum/carry answer. +0 was given by default otherwise. No points were deducted if you built your CLA as a CLA adder should be built (i.e. used the LA block carry outs to drive the carry ins to later blocks). Under normal circumstances, using the LA blocks to drive the carry ins will result in a faster adder (this is the whole point of CLA circuits). Unfortunately, P and G arriving @ time 2 makes it so that just using the carry outputs of the first level LA blocks (1, 2, 3 and 4) derive a just as fast if not fater circuit. Note the hanging lines out of the LA blocks. Ideally, those lines could be hooked up to the lower levels to drive carry in (because they are generated faster than the carry outs from each level 1 LA block). In the diagram, all point worthy carry/sum values are marked in purple. Page 12 of 13 EECS 150 Midterm 2 Solutions Fall 2008 Page 13 of 13

Find millions of documents here - Study Guides, Homework Solutions, Papers, Exam Answer Keys and more. Course Hero has millions of course related materials that will enable you to learn better, faster and get an A in all your courses.
Below is a small sample set of documents: