COMPRESSION LOSSLESS ALGORITHMS FOR POST-OPC IC LAYOUT Allan Gu and Avideh Zakhor Department of Electrical Engineering and Computer Sciences University of California at Berkeley, CA 94720, USA
ABSTRACT An important step in todays Integrated Circuit (IC) manufacturing is optical proximity correction (OPC). While OPC increases the delity of pattern transfer to the wafer, it also results in signicant increase in IC layout le size. In this paper, we develop two techniques for compressing post-OPC layout data while remaining compliant with existing industry standard data formats such as OASIS and GDSII. The motivation for doing so is for the resulting compressed les to be viewed and edited by any industry standard CAD tools without a decoder. Our approach is to eliminate redundancies in the representation of the geometric data by nding repeating groups of polygons between multiple cells as well as within a cell. We refer to the former as inter-cell sub-cell detection and the later as intra-cell sub-cell detection. Both problems are NP hard, and as such, we propose two sets of greedy algorithms to solve them. We show the results of our proposed inter-cell and intra-cell algorithms on actual 90nm, 130nm, and 180nm IC layouts. Index Terms IC layout, compression, OPC, repeating geometries 1. INTRODUCTION As the semiconductor industry moves toward denser designs with smaller feature sizes, pattern transfer from reticles to wafers, referred to as lithography, becomes more challenging. To correctly fabricate these circuits using current lithographic machines, Resolution Enhancement Techniques (RET) such as optical proximity correction (OPC) are routinely performed on the layout. Denser circuit design plus increased usage of RET have resulted in signicant explosion of layout data volume. Specically, The International Technology Roadmap for Semiconductors shows that the size of a single layer of an uncompressed fractured layout is likely to exceed 400 Gigabytes in 2007 ...
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