Design Platform-Based and Software Design Methodology for Embedded Systems
Alberto Sangiovanni-Vincentelli
University of California, Berkeley
Grant Martin
Cadence Design Systems
Embedded products have become so complex and must be developed so quickly that current design methodologies are no longer adequate. The authors vision for the future of embeddedsystem design involves two essential components: a rigorous methodology for embedded software development and platform-based design.
THE ESSENCE OF embedded-systems design is implementing a specic set of functions while satisfying constraints on characteristics such as performance, cost, emissions, power consumption, and weight. The choice of implementation architecture determines whether designers will implement a function as a hardware component or as software running on a programmable component. In recent years, the functions demanded for embedded systems have grown so numerous and complex that development time is increasingly difcult to predict and control. This complexity, coupled with constantly evolving specications, has forced designers to consider intrinsically exible implementationsthose they can change rapidly. For this reason, and because hardware-manufacturing cycles are more expensive and time-consuming, software-
based implementation has become more popular. Processors increased computational power and correspondingly decreased size and cost let designers move increasingly more functionality to software. However, along with this move comes increasing difculty in verifying design correctness. This verication is critical due to safety considerations in several application domains transportation and environment monitoring, for example. In traditional, PC-like software applications, these safety issues typically dont come up. In addition, the software world has paid little attention to hard constraints on softwares reaction speed, memory footprint, and power consumptionall crucial issues for embedded systemsbecause they are relatively unimportant in traditional software development. In embedded-systems design, such hard software characteristics are unavoidable. It is no wonder, then, that there is a crisis in embedded-software design. Along with the pressure on system designers to choose exible implementations, the industry is also witnessing IC manufacturers growing preference for chips that will work for several designs. This lets manufacturers amortize development cost over a large number of units, as discussed in the sidebar, Motivations for platform-based design. This alignment of designers and manufacturers has resulted in the birth of platform-based design,1,2 in which reuse and programmability are key. We believe that addressing the embedded
0740-7475/01/$10.00 2001 IEEE
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Roadmaps and Visions
Motivations for platform-based design
IC technology lets us integrate so many functions onto a single chip that we can indeed implement an environment-to-environment system on a chip. However, we cannot simply view SoCs as an extension of the application-specic IC methodology that has been in vogue for the past 10 years. The economics of SoCs in the ASIC framework are not appealing. The cost of designing and manufacturing SoCs is too high, given the relatively few parts typical in ASIC production. Our platform-based design methodology is an outgrowth of the SoC debate. The overall goal of electronic system design is to balance production costs with development time and cost in view of performance and functionality constraints. Manufacturing cost depends mainly on a products hardware components. Minimizing chip size to reduce production cost implies tailoring the hardware to product functionality. The cost of a state-of-the-art fabrication facility continues to rise. A new 300-mm, 0.13- or 0.10-micron, high-volume manufacturing plant today costs about $3.5 billion.1 The ITRS predicts that although manufacturing complex SoC designs will be feasibleat least down to 50-nm minimum feature sizesproducing practical masks and exposure systems will likely be a major bottleneck for such chips development. That is, the cost of masks will grow even more rapidly for these ne geometries. A single mask set and probe card for a next-generation chip costs more...
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