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Design A of Complex Impedance Meter A Design Project Report Presented to the Engineering Division of the Graduate School of Cornell University in Partial Fulfillment of the Requirements for the Degree of Master of Engineering (Electrical) by Yi Zhang Project Advisor: Bruce Land Degree Date: January 2007 Abstract Master of Electrical Engineering Program Cornell University Design Project Report Project Title: A...

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Design A of Complex Impedance Meter A Design Project Report Presented to the Engineering Division of the Graduate School of Cornell University in Partial Fulfillment of the Requirements for the Degree of Master of Engineering (Electrical) by Yi Zhang Project Advisor: Bruce Land Degree Date: January 2007 Abstract Master of Electrical Engineering Program Cornell University Design Project Report Project Title: A Design of Complex Impedance Meter Author: Yi Zhang Abstract: The Complex Impedance Meter presented in this report is a high precision, low power consumption impedance measurement system which provides programmable frequency sweep and tuning capability for impedance measurement from 5k to 1.1M with system accuracy of 2%. The system is built with an AVR microcontroller ATmega32, an Analog Devices network analyzer AD5933, two analog multiplexers ADG706, a CTS low jitter clock oscillator MXO45HS, two accurate resistor networks with designed resistance values and a liquid crystal display RCM2034R. It allows an unknown external impedance to be excited with a known frequency. The response signal from the impedance is sampled by the on board ADC, and the DFT is processed by a DSP engine which returns a real and imaginary data word at each excitation frequency. The magnitude of these data words is further scaled by calibrated Gain Factor in order to return the actual impedance value. The prototype of the system is implemented and system calibration is done to improve the overall accuracy. Report Approved by Project Advisor: Date: Executive Summary A prototype of a Complex Impedance Meter is designed and implemented. The system is a microcontroller based, high precision and low power device. Due to the simple structure, it can be made as a portable impedance measurement device, which is used in a lot of scientific and industrial fields such as electrochemical analysis, bioelectrical impedance analysis and material property analysis. The accuracy of 2% is realized through the appropriate design and system calibration. This accuracy is good enough for most of the biomedical impedance measurement applications. The system has been designed as an intelligent and friendly device, which does not need any adjustment or configuration before a measure. The maximum system response time is 0.5 second, which means in the worst case users can read the measured impedance on the LCD within half a second. If the impedance being measured is out of range, it will also give a message on the display indicating the error. The hardware design was implemented on several prototype boards. The values of the precision resistance were carefully calculated and chosen so that good linearity and measurable range (5k to 1.1M) can be achieved. Operating software was designed and implemented to realize the intelligence and easy-to-use features. The design trades off the maximum system response time with the intelligence and keeps a good balance between these two specs. Finally calibration was carried out and two methods were used to further improve the linearity of the system. Introduction From biological cell analysis to fuel cell tests, from coatings to cement paste quality control, Complex Impedance Measurement (CIM) has become a powerful tool in the vast environment of those applications. The basic principle of CIM is modeling the unit under test (UUT) in a combination of electrical components, applying small amplitude of AC voltage or current to the ends of UUT, over the frequency band of interest. For each frequency in the range, the measured impedance is a complex ratio between the input and output signal. Fig.1 Top Level Diagram In the design presented in this report, this principle is adopted into the architecture of the system. As Figure 2 shows, the on board frequency generator generates stimulus signal with known frequencies. The external unknown impedance is connected between the input and output ports. The response current from the impedance is converted into voltage by a trans-impedance amplifier. The output voltage of this amplifier is sampled by an on board ADC and the DFT is processed by a DSP engine at each excitation frequency. The real and imaginary results from the DSP are further processed by the microcontroller. They are compared with the results obtained from a known precise resistance using the same configuration on the signal path. The actual impedance value can be calculated from the known resistance together with the above measured results. Gain Control DDS Output Resistor Network Z Input Real Resistor Network DSP Imag VDD/2 Fig.2 System Block Diagram The Principle of Measurement The basic measurement method of AD5933 is comparing the two measured results from the unknown impedance and the calibrated (known) resistance. And then the value of the unknown impedance is obtained through calculation. As the signal path shown in Figure 3, VOUT, the output of the signal generator, can be modeled as a voltage source. The unknown impedance is connected between VOUT and VIN. VIN is biased at VDD/2 causing the AC current through Zunknown and RFB to be equal to VOUT/ Zunknown. If VOUT, RFB and the gain along the signal path is known, the unknown impedance can be calculated by sampling and processing the voltage at the output of low pass filter. Fig. 3 AD5933 Signal Path For accurate measure of the impedance, it is important that the receive stage is operating in its linear region. This requires careful selection of the excitation signal range, current-to-voltage gain resistor, and PGA gain. The gain through the system shown in Figure 3 is given by SystemGain = OutputExci tationVolt ageRange GainSettin g Re sistor PGAGain Z Unknown --------------------- (1) There are two issues related to the signal saturation problem. First, current from the external unknown impedance flows through the VIN pin and into a trans-impedance amplifier which has a user determined external resistor across its feedback path. The output voltage of the trans-impedance amplifier is determined by the closed loop gain -RFB/Zunknown and VOUT. The positive node of the amplifier is biased at a fixed value of VDD/2, large difference between the positive and negative nodes can saturate the output the amplifier. The RFB and the VOUT should be chosen so that this voltage remains in the linear region. Second, the gain of the PGA should be properly set to make best use of the dynamic range of the ADC but not to saturate the following stages. Both of these issues rely on an approximation of the Zunknown and proper selection on the feedback resistor. As the datasheet of AD5933 suggests, to get best accuracy, the RFB/Zunknown ratio should be within 0.066~0.2. The resistance values of the feedback network are determined as 4.7k, 10k, 27k, 57k, 200k, 470k, 1M. The measurable impedance range is then divided into 7 segments. One of the values is picked after the range of the unknown impedance is estimated. The way to estimate the unknown impedance is discussed in the software design part. System Design The microcontroller is the control unit and data processor in the system. It controls the AD5933 and two analog switches during the measures. After calculation and calibration based on the data from AD5933, the microcontroller sends the results to the LCD, where users can read the impedance values. The hardware connections between the microcontroller and the functional chips are shown below. Name AD5933 ADG706 (1) ADG706 (2) RCM2034R Connection Type I2C Parallel Parallel Parallel Line numbers 2 4 4 7 Description AD5933 control and data transfer Feedback resistor selection Calibration resistor selection LCD control and data transfer Table.1 Intrasystem Connection The microcontroller used in this project has four 8-bit I/O ports. All I/O pins are shared with alternate function pins. By setting the I/O ports to a proper status, they can be used as either general digital I/O or I/O pins of functional blocks in ATmaga32. I2C bus I2C bus is a Serial Interface Protocol. The AD5933 is connected to this bus as a slave device, under the control of a master device, which is the ATmega32 here. The AD5933 has a 7-bit serial bus slave address. When the device is powered up, it will do so with a default serial bus address, 0001101. Figure 4 shows the timing diagram for general read and write operations using the I2C interface. Fig. 4 General I2C protocol The master initiates data transfer by establishing a start condition, defined as a high to low transition on the serial data line (SDA) while the serial clock line (SCL) remains high. This indicates that a data stream follows. The slave responds to the start condition and shifts in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus an R/W bit, which determines the direction of the data transfer. That is, whether data is written to or read from the slave device (0 = write, 1 = read). The slave responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, then the master writes to the slave device. If the R/W bit is 1, the master reads from the slave device. Data is sent over the serial bus in sequences of nine clock pulses, 8 bits of data followed by an acknowledge bit, which can be from the master or slave device. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction telling the slave device to expect a block write, or it may be a register address that tells the slave where subsequent data is to be written. Data can flow in only one direction as defined by the R/W bit. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as a no acknowledge (NACK). The master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. LCD connection and control The RCM2034R is a reflective TN type liquid crystal module with a built-in controller / driver LSI and a display capacity of 16 characters with 2 lines. It supports both 4-bit and 8-bit operations. That is, data transfer with two transmissions of 4 bits at a time or one transmission of 8 bits at once. When using 4-bit operation mode, data is transferred along DB4 through DB7 buses and DB0 through DB3 buses are not used. (DB0-DB7 is the bi-directional data bus on RCM2034R.) Data transfer is completed after two transfers of 4 bit data. First the upper nibble (contents of DB4 through DB7 during 8-bit interfacing) is transferred and then the lower nibble (contents of DB0 through DB3 during 8-bit interfacing) is transferred. The 4-bit operation mode is used in this system so that a single 8-bit port connection is enough for this operation mode. Besides 4-bit data bus, three control lines need to be connected to complete the hardware connection between the microcontroller and the LCD. Table-2 shows the connection details and their functions. Symbol RS R/W Input/output Input Input Function Register selection signal. Reading and writing selection signal Data reading and writing start signal 4-bit operation data bus MCU Connection PD0 PD1 E DB4-DB7 Input Input/output PD2 PD4-PD7 Table.2 LCD Connection Analog Switches control The ADG706 is a low-voltage, CMOS analog multiplexers comprising 16 single channels. The ADG706 switches one of 16 inputs (S1S16) to a common output, D, as determined by the 4-bit binary address lines A0, A1, A2, and A3. An EN input is used to enable or disable the device. When disabled, all channels are switched off. An 8-bit parallel port is just good for two switches with both of the EN inputs are tied to VCC. They are used to switch the resistor networks between VOUT, VIN and RFB. The common terminals of these two switches are connected to VOUT and VIN respectively. The reference resistors are connected together to RFB on one end while the other ends are connected to different inputs on the switch. Similarly, the calibration resistors are connected together to VIN on one side. Figure 5 shows the connection of the resistor networks and switches. Fig. 5 Precision resistor networks Crystal Oscillator The frequency generator in AD5933 is based on DDS technique. There are two choices to get the reference frequency. The AD5933 has an on chip RC oscillator, which has an output frequency of 16.7MHz0.2 MHz with a 330ppm jitter spec. Relatively high phase noise of this internal oscillator can seriously affect the output stimulus signal, thus the accuracy of the measured impedance because all the following calculation is based on the nominal output frequency. The other choice is using an external clock to feed the 16.6MHz reference. A crystal oscillator with high stability of 50ppm is used. Though it consumes extra power, the frequency accuracy of the output signal can be greatly improved. Software design I2C bus Since the commands and data bytes between microcontroller and AD5933 are transferred through I2C bus, it is necessary to establish a function library containing all the read and write functions for the communication before applying high level application commands. In this design, the function library is divided into two levels. As shown in Figure 6, the low level functions complete the basic operations including register setting, reading and writing. The high level functions are based on the low level one. They use these basic register operations, as well as appropriate timing and protocol of AD5933, to complete all the communication operations AD5933 supports. Those functions include byte writing/reading, block writing/reading, address point setting. They are the routines called by the application level. Fig. 6 I2C bus function library LCD display There are existing functions for LCD control in ATmage32 function library. But most of them are low level functions which can only complete such tasks as putting one character on the screen, move the cursor to certain point or clear the screen. Higher level functions are needed to bridge the low level to the application level. Since the only information that needs to be shown on the screen are the current testing frequency and the measured impedance, the format of the displayed words are similar. A function with two inputs, the frequency and impedance, is written as the interface to the application level. After every measurement, the application program calls this function to output the measured results. Estimate the unknown impedance The AD5933 is capable of measuring impedance values by providing the real (R) and imaginary (I) code. The magnitude of the real and imaginary data contents is given by Magnitude( f ) = R 2 + I 2 . This magnitude value is equal to a scaled value of the actual impedance under test at the frequency point f. In order to determine actual impedance value users must multiply the magnitude by a number called Gain Factor GF(freq, Vdd, temp), which is a value representing the accumulative gain through the signal path of the system for known calibration impedance for a specified value of output gain voltage/pre ADC gain and feedback resistor settings. Therefore the actual impedance at any sample instance is given by the following, Im pedance ( f ) = GainFactor Magnitude ( f ) The Gain Factor is measured using a known external impedance, e.g., a precision resistor, connected between Vout and Vin as close as possible to the pins. Calculating the GF in this way calibrates out the parasitic impedance between Vout and Vin at a given frequency. The parasitic impedance is made up of a parallel capacitance between Vout and Vin as well as a series resistance and series inductance mainly due to the bond wires and solder joints. As there are several gain settings on the signal path, any adjustment to the supply voltage, calibration frequency, output excitation level, external feedback resistance value, and pre-ADC voltage gain will require a recalculation of the GF. If the GF is not recalculated after any system gain parameter adjustment then the impedance value returned by the AD5933 will have an error associated with it. Therefore the accuracy of final results depends upon the value of the GF. The gain factor is dependant upon the ratio of the trans-impedance feedback resistance value RFB to the impedance under test, Zunknown. In order for the AD5933 to return accurate values, it is necessary to ensure that the largest signal is returned to the ADC while ensuring that gain factor will not vary significantly over the unknown impedance range. Minimising the gain factor variation is achieved by placing the AD5933 operating point in the flat region the variation of the gain factor. The ratio of feedback resistance to calibration impedance should lie in the range of 0.2~0.066, recommended in the data sheet. These two values are chosen based on the knowledge of the range of unknown impedance. A straightforward and good way to estimate the unknown impedance is trial and error. Figure 7 shows the impedance estimation flow diagram. The estimation starts from the middle of the measurable impedance range, e.g., 27k-57k. The feedback resistor corresponding to this impedance range is chosen. Then the magnitude code of this unknown impedance under this feedback situation can be obtained. Compare this value with the upper and lower limit of the magnitude codes, which are the boundary values for the input signal staying in the linear range. If the measured value is not within the limits, the estimation process will stay in the loop and go through the steps discussed above again with a changed impedance range/feedback resistor. When the magnitude is larger than the upper limit, the next larger resistor will be chosen. When smaller, the next smaller resistor will be chosen. The loop will keep running until it finds a proper feedback resistor which makes the magnitude code within the limits or the unknown impedance is out of range. In either way, the loop stops. The magnitude code is recorded as one of the outputs of the loop when the impedance range is found while an error routine is called when it is out of range. Fig. 7 Impedance Estimation Flow Diagram System test and calibration The prototype of system is implemented with resistor networks consisting of high precision resistor (0.5%). Since these resistors are only accurate under low frequency, the test and calibration is conducted within its precision range. According to the discussion above, a proper feedback and calibration resistor should be chosen so as to get the best measurement accuracy. However, even if the case, the measurement results may not be within the accuracy range of 2%. An important assumption of the measurement is that the gain factor within one of those defined impedance ranges is constant. That is, the magnitude code is simply a linear function of the impedance. But the real situation is that the magnitude code becomes non-linear gradually as the unknown impedance approaches the boundaries of the defined impedance range. If the magnitude code of the calibration impedance is still used as a reference for such cases, results are not accurate. Figure 8 shows the linearity of magnitude code from 33K to 72K. It can be seen that if the unknown impedance is located in the lower part of this impedance range, the results may have large errors due to the non-linearity. Linearity of Mag Code 25000 20000 Mag Code 15000 10000 5000 0 0 10000 20000 30000 40000 50000 60000 70000 80000 Impedance (Ohm) Fig. 8 Linearity of magnitude code There are two to ways decrease the effect of this phenomenon. The first is to divide the impedance range into more sections. It is easy to see that if we can divide the impedance range shown in Figure 8 into 3 sections, 33K~45K~56K~72K, each of which is much more linear inside the range. However the cost of this way is to complicate the resistor networks, thus the whole system and more important, the measurement speed will be greatly lowered because of the nature of the impedance estimation method. In the worst case, the measurement time increases by three times as one impedance range is divided into three. The second way is to take advantage of the feature of signal path gain control on AD5933 to linearize the system. Since the magnitude code has linear relation to the gain through the system and the gain can be expressed as (1), changing the magnitude of output signal and/or the gain of the preamplifier has the same effect of changing the value of feedback resistor (gain setting resistor) on the magnitude code. So we can use two adjacent values of the feedback resistors (one in the impedance range where the unknown impedance located and the other in the adjacent range) to cover the same impedance range. Since the feedback resistors used in these two measurements are different, two different linearity curves can be obtained, which can be used to linearize the magnitude code to the desirable linearity. This needs to completely plot the linearity curves for all the impedance ranges and finely tune the parameters to get the best combination of these two linearity curves. But all these work can be done in the design stage. So it will not affect the measurement time during the use. The final design of this project adopted both of the two ways and the slowest measurement takes 0.5 second, which occurs in very low frequency range. Figure 9 shows the system linearity of the final design for the whole measurement range. The linearity can be calculated as Linearity = L arg estDeviationFromTheIdealCurve 21K = = 1.9% TheFullMeasurementRange 1100 5 K System Linearity 1200 1000 Measured Impedance (KOhm) 800 600 400 200 0 0 200 400 600 Actual Impedance (KOhm) 800 1000 1200 Fig. 9 System Linearity Conclusions and Future work A prototype of complex impedance meter is designed and implemented. The system is a microcontroller based, high precision and low power device. Due to the simple structure, it can be made as a portable impedance measurement device, which is used in a lot of scientific and industrial fields such as electrochemical analysis, bioelectrical impedance analysis and material property analysis. The accuracy of 2% is realized through the appropriate design and system calibration. This accuracy is good enough for most of the biomedical impedance measurement applications. Due to the limitation of the precision resistor networks used in the system, the accuracy is only proved in relatively low frequency. For the next step, frequency independent high precision resistors can be adopted and the system needs recalibrated for the best results. The second thing for the future work is the prototype can be further implemented on a PCB board to achieve less parasitic parameters and low noise. This may further increase the accuracy of the measurement. Acknowledge Designing a measurement device begins with a great deal of excitement. However, during the system design, chip ordering and implementation many unexpected issues need to be studied and solved. I got the initial idea and successfully completed this project under the guidance of Mr. Bruce Land. It is only appropriate that I express my best appreciation to him here. During the design work, I obtained quite a few valuable advice and suggestion from Mr. Land. Whats more, he provided me lots of electrical components which were not easy to get by myself. This greatly facilitated the design progress and finally helped me complete a good job. Reference [1] ATmega32 data sheet, Atmel Corporation 2002. [2] AD5933 data sheet, Analog Devices 2005. [3] AD5933 evaluation board data sheet, Analog Devices 2005. [4] ADG706 data sheet, Analog Devices 2002. [5] MXO45 data sheet, CTS Communications Components Inc. 2002. [6] RCM2034R data sheet, NOHM [7] AVR SKT500 User Guide, Atmel Corporation 2001 [8] Cornell ECE476 website, Bruce Land Appendix Words define Since both the operation of I2C bus and control of AD5933 have lots of command and status words, it is convenient for use by defining those hex numbers to more meaningful constants. Similarly, all the register addresses in AD5933 are defined in the same way. /********************************************* This program was written by Yi Zhang in the design of a Complex Impedance Meter email: yz226@cornell.edu Project : A Design of Complex Impedance Meter Version : 1.0 Chip type : ATmega32 Program type : Application Clock frequency : 16.000000 MHz Memory model : Small External SRAM size : 0 Data Stack size : 512 *********************************************/ /* Use an 1x16 alphanumeric LCD connected to PORTA as follows: [LCD] [Mega32 pin] 1 GND- GND 2 +5V- VCC 3 VLC 10k trimpot wiper (trimpot ends go to +5 and gnd) 4 RS - PC0 5 RD - PC1 6 EN - PC2 11 D4 - PC4 12 D5 - PC5 13 D6 - PC6 14 D7 - PC7 */ #include <mega32.h> #include <math.h> #include <Delay.h> #include <stdio.h> #asm .equ __lcd_port=0x1b #endasm #include <lcd.h> //LCD driver routines //Reference Code range #define CodeMax 25000 #define CodeMin 10000 #define CodeMid 21000 #define LCDwidth 16 //LCD characters #define startfreq 5 //Start Frequency #define incfreq 100 //Incremental Frequency #define SUCCESS 0xff //Command #define Start 0xa4 #define Stop 0x94 //Flag #define Trans 0x84 #define ACK 0xc4 //I2C bus Status #define START 0x08 #define ReSTART 0x10 #define SLA_W 0x1a #define SLA_R 0x1b #define MT_SLA_ACK 0x18 #define MT_SLA_NACK 0x20 #define MR_SLA_ACK 0x40 #define MR_SLA_NACK 0x48 #define MT_DATA_ACK 0x28 #define MT_DATA_NACK 0x30 #define MR_DATA_ACK 0x50 #define MR_DATA_NACK 0x58 #define TWINT 0x80 //AD5933 control codes #define Init 0x10 //Initialize with start Freq #define Sweep 0x20 //Start Frequency Sweep #define IncFreq 0x30 //Increment Frequency #define RepFreq 0x40 //Repeat Frequency #define MeaTemp 0x90 //Measure Temperature #define PowerDown 0xa0 //Power down mode #define Standby 0xb0 //Standby mode #define Range2V 0x00 //Output Voltage range 2V #define Range1V 0x06 //Output Voltage range 1V #define Range400mV 0x04 //Output Voltage range 400mV #define Range200mV 0x02 //Output Voltage range 200mV #define gainx5 0x00 //PGA gain x5 #define gainx1 0x01 //PGA gain x1 //AD5933 Register addresses #define Control_high 0x80 #define Control_low 0x81 #define Freq_high 0x82 #define Freq_mid 0x83 #define Freq_low 0x84 #define FreqInc_high 0x85 #define FreqInc_mid 0x86 #define FreqInc_low 0x87 #define NumInc_high 0x88 #define NumInc_low 0x89 #define NumSettle_high 0x8a #define NumSettle_low 0x8b #define Status 0x8f #define Temp_high 0x92 #define Temp_low 0x93 #define Real_high 0x94 #define Real_low 0x95 #define Imag_high 0x96 #define Imag_low 0x97 /******************************************************************** ******** Function : char Init_TWI(void) Setup the TWI module Baudrate : 250kHz @ 16MHz system clock Own address : OWN_ADR (Defined in TWI_driver.h) ********************************************************************* *******/ unsigned char Init_TWI(void) { //TWAR = OWN_ADR; //Set own slave address TWBR = 0x18; //Set baud-rate to 250 KHz at 16 MHz xtal TWCR = 0x04; //Enable TWI-interface return 1; } /******************************************************************** ******** Function : void Wait_TWI_int(void) Loop until TWI interrupt flag is set ********************************************************************* *******/ void Wait_TWI_int(void) { while(!(TWCR & TWINT)); } /******************************************************************** ******** Function :unsigned char Send_start(void) Send a START condition to the bus and wait for the TWINT to be set and see the result. If it failed, return the TWSR value, if succeeded, return SUCCESS. ********************************************************************* *******/ unsigned char Send_start(void) { TWCR=Start; //Send START Wait_TWI_int(); //Wait for TWI interrupt flag to be set if((TWSR & 0xF8)!=START || (TWSR & 0xF8)!=ReSTART) return TWSR; //If it failed, return the TWSR value return SUCCESS; //If succeeded, return SUCCESS } /******************************************************************** ******** Function : void Send_stop(void) Send a STOP condition to the bus ********************************************************************* *******/ void Send_stop(void) { TWCR = Stop; //Send a STOP condition } /******************************************************************** ******** Function : unsigned char Send_adr(unsigned char adr) Send a SLA+W/R to the bus ********************************************************************* *******/ unsigned char Send_adr(unsigned char adr) { Wait_TWI_int(); //Wait for TWI interrupt flag set TWDR = adr; TWCR = Trans; Wait_TWI_int(); //Clear int flag to send byte //Wait for TWI interrupt flag set if((TWSR & 0xF8)!= MT_SLA_ACK || (TWSR & 0xF8)!= MR_SLA_ACK) return TWSR; //If NACK received return TWSR return SUCCESS; } //Else return SUCCESS /******************************************************************** ******** Function : unsigned char Send_byte(unsigned char data) Send one byte to the bus. ********************************************************************* *******/ unsigned char Send_byte(unsigned char data) { Wait_TWI_int(); //Wait for TWI interrupt flag set TWDR = data; TWCR = Trans; Wait_TWI_int(); //Clear int flag to send byte //Wait for TWI interrupt flag set if((TWSR & 0xF8)!= MT_DATA_ACK) return TWSR; //If NACK received return TWSR return SUCCESS; } /******************************************************************** ******** Function : unsigned char Set_pointer(unsigned char reg_loc) Set the pointer to a register location. ********************************************************************* *******/ unsigned char Set_pointer(unsigned char reg_loc) { Send_start(); Send_adr(SLA_W); Send_byte(0xb0); //Pointer command code '1011 0000' Send_byte(reg_loc); //a register location at which the pointer points return 1; } /******************************************************************** ******** Function : unsigned char Byte_write(unsigned char reg_addr, unsigned char data) Write a byte to AD5933. //Else return SUCCESS ********************************************************************* *******/ unsigned char Byte_write(unsigned char reg_addr, unsigned char data) { Send_start(); Send_adr(SLA_W); Send_byte(reg_addr); Send_byte(data); Send_stop(); return 1; } /******************************************************************** ******** Function : unsigned char Block_write(unsigned char reg_loc, unsigned char byte_num, unsigned char* data_p) Write a block of data to AD5933. ********************************************************************* *******/ unsigned char Block_write(unsigned char reg_loc, unsigned char byte_num, unsigned char* data_p) { unsigned char i; Set_pointer(reg_loc); //set the pointer location Send_start(); //write the data block Send_adr(SLA_W); Send_byte(0xa0); //Block write command code '1010 0000' Send_byte(byte_num); //Num of data to be sent for(i = 0;i < byte_num;i++) //Send the data bytes { Send_byte(*(data_p+i)); } Send_stop(); return 1; } /******************************************************************** ******** Function : unsigned char Byte_read(unsigned char reg_loc) Read a byte from AD5933. ********************************************************************* *******/ unsigned char Byte_read(unsigned char reg_loc) { Set_pointer(reg_loc); //set the pointer location //Receive a byte Send_start(); Send_adr(SLA_R); TWCR = Trans; Wait_TWI_int(); return TWDR; } /****************************************************...

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Cornell - CS - 211
CS211 Computers and ProgrammingOverview: CS211 - Spring 2KInstructors:Professor Graeme Bailey Office: 5156 Upson Phone: 255-9210 Email: bailey@cs.cornell.edu Office hours: TBA Professor Khalid Mughal Office: 486 Rhodes Phone: 255-1543 Email: mugha
Cornell - CS - 211
GUIOverview: JFC - Java Foundation Classes Containers and Components containment hierarchy: Component layout using layout managers Event driven programming: events, listeners and sources Implementing listeners using: Adapter Classes Anonymous
Cornell - CS - 211
Cornell - CS - 211
Cornell - CS - 211
Cornell - CS - 211
Cornell - CS - 211
Object-oriented Programming - IOverview Reference: A Programmer's Guide to Java Certification: A Comprehensive Primer Chapter 4 &amp; Chapter 6 Object Model (OM) Values, Variables and Types Defining classes Instance and static members Method sign
Cornell - CS - 411
CS411 Notes 7 Lexical ScopeA. Demers 13 Feb 2001In a sense our denition of the copy rule as a function leads directly to a semantics for programs with expression abstractions. Suppose e is an expression with no free variables. Then to show e, 0 ,
Cornell - CS - 411
CS411 Notes 6 Copy Rule DenitionA. Demers 12 Feb 2001As threatened, we now give a formal development of a copy rule for which we can give lazy evaluation proof rules.1SubstitutionWe start with a formal denition of substitution. We will deno
University of California, Merced - CSE - 140
Chapter 1Computer Abstractions and Technology1.1 IntroductionThe Computer RevolutionProgress in computer technologyUnderpinned by Moores LawMakes novel applications feasibleComputers in automobiles Cell phones Human genome project World Wid
University of California, Merced - CSE - 140
CSE 140Computer ArchitectureCSE 140Instructor: Ming-Hsuan Yang (mhyang@ucmerced.edu) Teaching assistant: Chao Qin (cqin@ucmerced.edu) Lectures:COB 288, Monday/Wednesday 3:00 pm to 4:15 pmLab session:SE 154, Friday 4:00 pm to 7:50 pmWeb site
University of California, Merced - U - 0030
Advanced Topics in Learning and VisionMing-Hsuan Yang mhyang@csie.ntu.edu.twL ECTURE 1Information Course: 944 U0030/922 U3320 Advanced topics in learning and vision Web site: http:/www.csie.ntu.edu.tw/mhyang/course/u0030 Instructor: Ming-Hsu
University of California, Merced - CSE - 140
Chapter 2Instructions: Language of the Computer2.1 IntroductionInstruction SetThe repertoire of instructions of a computer Different computers have different instruction setsBut with many aspects in commonEarly computers had very simple inst
University of California, Merced - JRAYMOND - 2
Photosynthesis Research 75: 277285, 2003. 2003 Kluwer Academic Publishers. Printed in the Netherlands.277HypothesisThe FMO protein is related to PscA in the reaction center of green sulfur bacteriaJohn M. Olson1, &amp; Jason Raymond2of Biochemis
Cornell - AERC - 1106
The Relationship between Poverty and Maternal Morbidity and Mortality in Sub-Saharan AfricaA presentation for the AERC/Hewlett Foundation Workshop, Poverty and Economic Growth: The Impact of Population Dynamics and Reproductive Health Outcomes in A
Cornell - GB - 78
3/11/2007Garrick BlalockCornell University Dept. of Applied Economics and Management 346 Warren Hall Ithaca, NY 14850 http:/www.aem.cornell.edu/faculty_sites/gb78 +1 (607) 255-0307 voice +1 (607) 255-9984 garrick.blalock@cornell.edu US citizen, ma
Cornell - DTN - 4
The International CAPM When Expected Returns are Time VaryingDavid Tat-Chee Ng Department of Applied Economics and Management Cornell University July 16, 2001Abstract This paper extends Campbell (1996)s intertemporal CAPM to an international enviro
Cornell - DTN - 4
Corruption and International Valuation: Does Virtue Pay?By Charles M. C. Lee Johnson Graduate School of Management Cornell University, Ithaca, NY 14853 David Ng* Department of Applied Economics and Management Cornell University, Ithaca, NY 14853Fi
Cornell - GB - 78
10/16/2008Garrick BlalockCornell University Dept. of Applied Economics and Management 346 Warren Hall Ithaca, NY 14850 http:/www.aem.cornell.edu/faculty_sites/gb78 +1 (607) 255-0307 voice +1 (607) 255-9984 garrick.blalock@cornell.edu US citizen, m
Cornell - GB - 78
9/17/02Garrick BlalockCornell University Dept. of Applied Economics and Management 444 Warren Hall Ithaca, NY 14850 http:/www.aem.cornell.edu/faculty_sites/gb78 +1 (607) 255-0307 voice +1 (607) 255-9984 gb78@cornell.edu US citizen, marriedEducat
Cornell - DTN - 4
The Sovereign Ceiling and Emerging Market Corporate Bond Spreads Erik Durbin and David Tat-chee Ng September 3, 2001Abstract We use the spreads of emerging market bonds traded in secondary markets to study investors perception of country risk. Spe
Cornell - GB - 78
2/24/2006Garrick BlalockCornell University Dept. of Applied Economics and Management 346 Warren Hall Ithaca, NY 14850 http:/www.aem.cornell.edu/faculty_sites/gb78 +1 (607) 255-0307 voice +1 (607) 255-9984 garrick.blalock@cornell.edu US citizen, ma
Cornell - LWT - 1
Estimates of Individual Dairy Farm Supply ElasticitiesLoren W. TauerThis is Working Paper, WP98-08, of the Department of Agriculture, Resource, and Managerial Economics, Cornell University, July 1998.AbstractMilk supply elasticities were estim
Cornell - NLB - 4
Chautauqua County Farmland Protection PlanHistory and Statistics Chapter 1Chautauqua County is one of 12 Metropolitan Statistical Areas in New York State, being so designated on the basis of its two urbanized areas, one centered in the City of Jam
Cornell - NLB - 4
December 1997THE P's OF FARMLAND PROTECTIONEditors Note: This issue launches a new series on farmland protection incentives and policies that are currently at the forefront of state, regional, and national agricultural land use debates. This first
Cornell - NLB - 4
Cornell - NLB - 4
January 1998AGRICULTURE AND TAXES ON FARM REAL ESTATE Introduction As noted in the previous issue, taxation of farm real estate has concerned the farm community for many years. Beginning in the 1950s, farmers looked to state legislatures for relief
Cornell - NLB - 4
May 1998FUNDING NEW YORK PUBLIC EDUCATION AND THE ROLE OF AGRICULTURE Background As indicated in our last issue, the property tax and its effects on farming is a perennial issue for New York agriculture. Despite arrangements for tax concessions, ta
Cornell - NLB - 4
August 1998Tax Preferences on Farm Real Estate and the Redistribution of the School Tax Tax Relief Mechanisms for Farm Real Estate In 1996 the New York State legislature provided school tax relief to agriculture in the form of an income tax credit.
Cornell - GB - 78
Hitting the Jackpot or Hitting the Skids: Entertainment, Poverty, and the Demand for State LotteriesGarrick Blalock, David R. Just, and Daniel H. Simon December 14, 2004Abstract State-sponsored lotteries are a lucrative source of revenue. Despite
Cornell - NELS - 39
The relation between phonetic and phonological encoding in perception: Interactive or autonomous? Michael Key University of Massachusetts, Amherst Much previous work on the influence of phonological knowledge in perception has found evidence that lis
Cornell - NELS - 39
Reduplication in Compounding Contexts: Morphological Doubling vs. Correspondence Jason D. Haugen, Williams College Given a compound construction Z, composed of two stems X and Y (thus, [X-Y]Z), there are at least eight theoretically possible ways, ig
Cornell - NELS - 39
T-extension and null subject licensing Ivona Ku erov , UCL c a I argue that grammatical licensing of null subjects (NS) in the sense of identication and/or recoverability (regardless of whether the NS is referential pro, PRO, or a bound variable; Cho
Cornell - NELS - 39
An Interface Approach to Stranded Prepositions: A Case of Swiping Kayono Shiobara Bunkyo Gakuin University This paper examines the interface properties of stranded P(reposition)s in English swiping. Offering empirically and theoretically based argume
Cornell - NELS - 39
At the Interfaces: Deriving and Interpreting Focus and Anaphora in VP-Ellipsis Dan Parker Eastern Michigan University Recent research suggests that a full understanding of the interaction between ellipsis and anaphora must involve more than the synta
Cornell - NELS - 39
NELS39 Abstract * August 2008 * Anne-Michelle TessierUSELISTEDERROR: A grammatical account of lexical exceptions in phonological acquisition Anne-Michelle Tessier, University of Alberta Overview This talk presents an analysis of lexical exceptions
Cornell - NELS - 39
Laryngeal (dis)harmony, perception and the Dispersion Theory of Contrast Gillian Gallagher Massachusetts Institute of Technology In this talk, I extend the Dispersion Theory of Contrast (Flemming 1995, 2004, 2006) to cases of laryngeal harmony and di
Cornell - NELS - 39
PASSIVE AGREEMENT IN ACEHNESE JULIE ANNE LEGATE UNIVERSITY OF PENNSYLVANIA The Problem: Lawler (1977) argued that Acehnese exhibits a passive in which the agent in the byphrase triggers subject agreement, (1a). Duries (1988) reply revealed errors in
Cornell - NELS - 39
Classifiers as morphosyntactic licensors of NP Ellipsis: English vs. Romance Artemis Alexiadou &amp; Kirsten Gengel (Universitt Stuttgart) 1. Aim of the paper. In the recent literature on NP ellipsis (NPE), the view has prevailed that NPE should be analy
Cornell - NELS - 39
Overt Evidence from Left-Branch Extraction in Polish for Punctuated PathsBartosz Wiland (University of Pozna) 1. Outline. In Polish, wh-questions are formed by pied-piping of an entire wh-NP or by the extraction of a left-branch wh-phrase (LBE). A q
Cornell - NELS - 39
The V-to-I parameter revisited Kristine Bentzen, University of TromsThis paper takes a closer look at the nature of the V-to-I parameter. I will argue that the traditional Vto-I movement comes in (at least) two distinct types, which are linked to tw
Cornell - NELS - 39
Indenites, Choice Functions, and Discourse Anaphora Jonathan Brennan, New York University Choice functions are a widely accepted tool used to explain the scope properties of indenite expressions (Reinhart, 1997; Kratzer, 1998; Winter, 2004, a.o.). St
Cornell - NELS - 39
Comparison with indeterminateness: a multidimensional approachOsamu Sawada University of Chicago sawadao@uchicago.edu Introduction: In Japanese the meaning of free choice is expressed by indeterminate pronouns and the particle mo in comparative envi
Cornell - NELS - 39
39th Meeting of theNorth East Linguistic SocietyCornell University November 7-9, 2008NE 39 Sinvited speakersArto AnttilaStanford Universityspecial session: linguistics at the interfacesThe design of the grammar is standardly assumed to be
Cornell - NELS - 39
Whats so Special about D-Linking? Rebecca Shields University of Wisconsin-Madison Since Pesetsky 1987, it has been recognized that D-linking does funny things. In particular, some D-linked questions are exempt from certain otherwise strict conditions
Cornell - NELS - 39
Multiple Exponence and the phonology-morphology interface Gabriela Caballero University of California, Berkeley/SUNY Stony Brook The theoretical relevance of Multiple Exponence (ME), a one-to-many mapping between meaning and form (Matthews 1974), has
Cornell - NELS - 39
Extraposition, Syntactic Doubling and CED effects Marco Nicolis (nicolis@gmail.com) Georgetown University Background: Iatridou and Embick (1997) (I &amp;E henceforth) show that pro contrasts with overt it type expletives in its inability to have a C/IP a
Cornell - NELS - 39
Learning Phonological Grammars for Output-Driven MapsBruce Tesar Department of Linguistics, Rutgers University, New Brunswick tesar@rutgers.edu The challenge of simultaneously learning a lexicon of underlying forms and a constraint ranking has been
Cornell - NELS - 39
Carlos Buesa Garca University of Connecticut The interaction between locality and the subject-gap restriction in Spanish questions This talk provides a new account of the subject-gap restriction (Torrego 84, Goodall 04, Ausn &amp; Mart 99) in Spanish WH-
Cornell - NELS - 39
Kristine M. Yu (UCLA) NELS 39 abstract The sound of ergativity: syntax-prosody mapping in Samoan There is a long-standing debate on how much syntactic information gets passed to prosody: are syntactic category labels erased, leaving just XP edges, cf