5 Pages

Lecture10

Course: CSCE 451, Spring 2008
School: UNL
Rating:
 
 
 
 
 

Word Count: 410

Document Preview

Layout Address Memory spaces x 1 Memory a linear array of bytes Physical address space that supported by the hardware y MAX starting at address 0, going to address MAX MAXP Logical address space a processs view of memory Program P y http://www.cse.unl.edu/~goddard/Courses/CSCE451 starting at address 0, going to address MAXP 0 Memory Management Basics x But where do addresses come from? MOV r0,...

Register Now

Unformatted Document Excerpt

Coursehero >> Nebraska >> UNL >> CSCE 451

Course Hero has millions of student submitted documents similar to the one
below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.

Course Hero has millions of student submitted documents similar to the one below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.
Layout Address Memory spaces x 1 Memory a linear array of bytes Physical address space that supported by the hardware y MAX starting at address 0, going to address MAX MAXP Logical address space a processs view of memory Program P y http://www.cse.unl.edu/~goddard/Courses/CSCE451 starting at address 0, going to address MAXP 0 Memory Management Basics x But where do addresses come from? MOV r0, 0xfffa620e 0 goddard@cse.unl.edu CSCE 451/851 Operating Systems Principles 2 Steve Goddard CSCE 451/851 Steve Goddard Lecture 10 CSCE 451/851 Steve Goddard Page 2 Lecture 10 Page 1 Address Generation The compilation pipeline 0 1000 Simple Memory Management Schemes Fixed-sized partitions MAX x Library Routines Library Routines 1100 : : : jmp 175 : ... : : : jmp 1175 : ... Two variations: Jobs queue for partitions y Py Px prog P : : foo() : : end P P: : push ... inc SP, x jmp _foo : foo: ... 0 : push ... inc SP, x jmp 75 : ... 100 addressing done by the linker/loader Jobs queue for memory y P3 P2 P1 dynamic relocation required Program P 75 175 1175 x Scheduling maximize performance maximize memory utilization Pa 0 Compilation Assembly Linking Loading 3 4 CSCE 451/851 Steve Goddard Lecture 10 Page 3 CSCE 451/851 Steve Goddard Lecture 10 Page 4 Dynamic Program Relocation Program compilation x Dynamic Program Relocation Base + Limit registers MAX MEMORY EXCEPTION Logical Addresses Code relocated at run-time P: : push ... inc SP, x jmp _foo : foo: ... 0 : push ... SP, inc x jmp 75 : ... 0 1000 Library Routines prog P : : foo() : : end P 100 : : : jmp 175 : ... 1100 Library Routines : : : jmp 175 : ... n CPU 500 y + 1000 Physical Addresses 1500 Program Ps PAS 1000 75 175 1175 MAX Compilation Assembly Linking Loading (No relocation) 0 Program Ps LAS Limit Register Base Register 0 6 5 CSCE 451/851 Steve Goddard Lecture 10 Page 5 CSCE 451/851 Steve Goddard Lecture 10 Page 6 Memory Management Issues Fragmentation MAX x Simple Memory Management Schemes Variable-sized partitions x Internal fragmentation Program Qs PAS x Allocate a partition when a process is admitted into the system Keep track of... full-blocks empty-blocks (holes) MAX Program P1 P x P5 Program P2 External fragmentation x Allocation strategies first-fit best-fit worst-fit 0 Program P3 Program P4 8 Program 0 Rs PAS 7 CSCE 451/851 Steve Goddard Lecture 10 Pa...

Find millions of documents on Course Hero - Study Guides, Lecture Notes, Reference Materials, Practice Exams and more. Course Hero has millions of course specific materials providing students with the best way to expand their education.

Below is a small sample set of documents:

UNL - CSCE - 351
CSCE 351 Operating System Kernels TerminalsSteve Goddardgoddard@cse.unl.eduhttp:/www.cse.unl.edu/~goddard/Courses/CSCE3511Terminal Hardware2Memory Mapped Terminalsx xCPU writes data to special memory called Video RAM The video controll
UNL - CSCE - 351
Intel Architecture Software Developer's ManualVolume 2: Instruction Set ReferenceNOTE: The Intel Architecture Software Developer's Manual consists of three volumes: Basic Architecture, Order Number 243190; Instruction Set Reference, Order Number 2
UNL - CSCE - 451
The UNIX Operating SystemHistoryx1The original UNIX Main variants (Standards)x An experimental operating system developed by Ken Thompson & Dennis Ritchie in the late 60s System Vy POSIXdeveloped by AT&T, now owned by UNIX International
UNL - CSCE - 451
Virtual Memory ManagementFundamental issuesx1Placement strategyxReplacement strategiesxLoad control strategieshttp:/www.cse.unl.edu/~goddard/Courses/CSCE451Virtual Memory: Load Control & Performance When & how much of a process's vir
UNL - JDEP - 284
JDEP 284H Foundations of Computer SystemsGiving credit where credit is dueMost of slides for this lecture are based on slides created by Drs. Bryant and O'Hallaron, Carnegie Mellon University. I have modified them and added new slides.The Memory
UNL - CSCE - 855
Two Types of Processes1xHeavyweight process normal process that does not share memory with other processesparent pc Stack Data Codechild pc Stack Data Codehttp:/www.cse.unl.edu/~goddard/Courses/CSCE855xLightweight process: Threads me
UNL - CSCE - 451
CSCE 451/851 Operating Systems PrinciplesHistory of Operating Systems & Basic Operating System Concepts Prof. Steve Goddard goddard@cse.unl.eduPage 1http:/www.cse.unl.edu/~goddard/Courses/CSCE451CSCE 451/851 Introduction & History of OS Steve G
UNL - CSCE - 855
CORBAx1Common Object Request Broker Architecturey y specification for object-request architecturesI.e. match object requests with implementations distributed object platform/frameworky CORBA is not a working productCSCE 455/855 Distribu
UNL - CSCE - 351
CSCE 351 Operating System Kernels The UNIX/MINIX Operating System Processes & IPCSteve Goddardgoddard@cse.unl.eduhttp:/www.cse.unl.edu/~goddard/Courses/CSCE3511UNIX HistoryxThe original UNIX An experimental operating system developed by K
UNL - CSCE - 230
CSCE 230J, Spring 2004 Final Project: Malloc Lab: Writing a Dynamic Storage Allocator Assigned: Thurs Apr. 8, Due: Friday Apr. 30, 09:00PMByron Blunk (bblunk@unlnotes.unl.edu) is the lead person for this assignment.1 IntroductionIn this lab you
UNL - CSCE - 310
Team Evaluation FormYour name _ Date _PERSONNEL EVALUATION : Please enter the names of your team members in the first row and complete thefollowing personnel evaluation. 1 = Excellent, 2 = Good, 3 = Acceptable, 4 = Marginal, 5 = UnacceptableNam
UNL - CSCE - 310
Fall 2004 Team AssignmentsTeam 1:Joel DaviesMeagan LongoriaDerrick StoleeAmar GuptaYuliy PisetskyTeam 2:Christine TroshynskiJeremy Stack-EllsworthTravis MeindersBen FluehrBrett MelonisTeam 3:Cliff SmolinskyDan MorrisDaniel Rowe
UNL - CSE - 413
9. Evaluation of QueriesQuery evaluation 19.1 Quantifier Elimination and SatisfiabilityExample:Logical Level: Constraint level: r S y1,.yn eliminate x r' S'Infinite relation r(x, y1,.yn) equivalent to constraint relation S. Infinite rel
UNL - CSE - 413
7. Refinement QueriesThree different assumptions about the input database:Tuple Inside Closed World Open World Possible World True True May beTuple Outside False May be False1UOR Universal Object Relation all attributes in one constraint r
UNL - CSE - 413
6. Constraint AutomataConstraint Automaton set of states, set of state variables, transitions between states, domain of state variables, and initial values of state variables. Transition ground constraints ? assignment statements Ground constraint
UNL - CSE - 413
16.DataVisualization IsometricColorBands ValuebyAreaCartograms AnimationofMovingObjectsTwosnapshotsofCaliforniagullranges(1970) (1990)WildernessAreaatt=0WildernessAreaatt=10WildernessID X Y T G x y t P P x y t x y tx<=1
UNL - CSCE - 476
; Save the follwoing in your home directory as ".emacs"(load "/usr/dist/pkgs/acl501/eli/fi-site-init")(setq fi:common-lisp-image-name "/usr/dist/pkgs/acl501/lisp")
UNL - CSCE - 990
Dynamic Variable Ordering In CSPsFahiem Bacchus and Paul Van RunContents 1. Introduction 1.1 Basic concept of tree search algorithm 1.2 Dynamic Variable Ordering (DVO) 2. A methodology for adding DVO 2.1 Notation 2.2 BackTracking (BT) 2.3 Forward
UNL - CSCE - 351
Nios II IDE Help System101 Innovation Drive San Jose, CA 95134 www.altera.comNios II IDE Version: Document Version: Document Date:7.2 1.4 October 2007UG-N2IDEHELP-1.4Table Of ContentsAbout This Document..1 Welcome to the Nios II IDE. 3 Wha
UNL - CSCE - 351
Name:_SID: _CSCE 351: Operating System Kernels Lab 1 User-Level Thread ManagementBasic Setup: Accessibility to a Linux workstation Copy jumplab.tar from ~ylu/share/csce351/ directory Objectives: The objectives of this lab are as follows: Fam
UNL - CSCE - 351
8. Exception HandlingNII52006-7.2.0IntroductionThis chapter discusses how to write programs to handle exceptions in the Nios II processor architecture. Emphasis is placed on how to process hardware interrupt requests by registering a user-defin
UNL - CSCE - 351
6. Developing Programs Using the Hardware Abstraction LayerNII52004-7.2.0IntroductionThis chapter discusses how to develop programs for the Nios II processor based on the Altera hardware abstraction layer (HAL). This chapter contains the followi
UNL - CSCE - 351
16. Timer CoreNII51008-7.2.0Core OverviewThe timer core with Avalon interface is a 32-bit interval timer for Avalonbased processor systems, such as a Nios II processor system. The timer provides the following features: Controls to start
UNL - CSCE - 351
Exception Handling in Nios IIYing LuCSCE351-Operating System KernelsGiven Credit Where It is Due Most of the lecture notes are based on slides by Dr. Witawas Srisa-an I have modified them and added new slidesInterrupts Used for communication
UNL - CSE - 230
CSCE 230, Spring 2009Homework 2 (Chapter 2) Due: Tuesday, 2/5/2009 before classNote: Recall from the syllabus that: 1. Although homework assignment s carry a relatively small fraction (10%) of the course, doing them will certainly help you in doing
UNL - CSE - 230
CSCE 230, Spring 2009Homework 1 (Chapter 1) Due: Tuesday, 1/27/2009 before classNote: Recall from the syllabus that: 1. Although homework assignment s carry a relatively small fraction (10%) of the course, doing them will certainly help you in doin
UNL - CSE - 932
IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 12, DECEMBER 1981987[3] F. P. Preparata, "Universal logic modules of a new type," IEEE Trans. Comput., vol. C-21, pp. 585-587, June 1972. [4] R. P. Voith, "ULM implicants for minimization of universa
UNL - CSE - 488
CSCE488 Project Proposal "RFID Pet Door"Team #2 Andrew Parr Conner Rocole Ben Peetz Eric SturmPrepared for Dr. Sharad SethOctober 30, 2006IntroductionThe objective of the project is to develop a secure system to regulate a domesticated anima
UNL - CSE - 488
Project ProposalTeam Apocalypse: Paul Bartunek, Kevin Farrell, and Hayder MouhammedComputer Science and Engineering 488 Homework Five October 30, 2006IntroductionTeam Apocalypse has chosen to create a remote automobile control system. This sys
UNL - CSE - 488
The Car Monitor SystemOctober 30, 2006Team Five: Joshua Rupiper James Dicke Tyler AndrewsTeam Five 2 Purpose of the Project: The Car Monitor System's primary goal is to further connect the driver to the car. The driver will be able to easily obt
UNL - CSE - 488
Follow up to Challenger MovieOctober 16, 2007Roger BoisjolyDo you think he did all that was possible for him to do to prevent the illfated launch of the space shuttle? If not, what more could he have done? What would you have done if you w
UNL - CSE - 488
RFID Pet DoorEE 494, Fall 2006Andrew Parr Conner Rocole Ben Peetz Eric Sturm IntroductionTo design and build an automated system to regulate and monitor a pet's movement into and out off a structure with minimal human intervention.
UNL - CSE - 488
TheCarMonitorJoshRupiper JamesDicke TylerAndrewsMotivationConnecttheDrivertotheCarErrorcodesrecognized EfficiencyReports DrivingHabitsAteenagersfirstcar TractormonitoringExpandabilityGPS ODB-II SensorUSB HubOdometer + Speed
UNL - CSE - 488
Remote Vehicle Control SystemPaul Bartunek Kevin Farrell Hayder MouhammedProject Idea Provideremote control functionalities to an automobile via Wi-Fi Assumptions made Entirearea covered by Wi-Fi Interface to digital climate controlWhy W
UNL - CSE - 488
WirelessLocalization SystemUsingPropagation TimingBrianDake BrianVaughan SeanBrennan Basics Localizationusingpropagationtiming Locationtrackedinrealtime Canbeusedtocontrolservosfortracking Spotlights,cameras,laserpointer,etcFunction 1m
UNL - CSE - 488
Team 7 Homework 5Localization and Targeting System Project ProposalThis report defines the outline, plan, and design for creating a localization system. This system will be electronic and wireless and will take three people one semester to complet
UNL - CSE - 932
CSCE 932, Spring 2009Fault Coverage Analysis1Fault Simulation2Problem and MotivationProblem: Given Determine A circuit A sequence of test vectors A fault model Fault coverage fraction (or percentage) of modeled faults detected by t
UNL - CSE - 932
CSCE 932, Spring 2009 Basics of Testing1The Chip Testing ProcessTest Responses RUnit Under Test (UUT)Comparator R' Expected Responses TestsPass: R=R' Fail: otherwiseTest Patterns TATEATE: Automatic Test Equipment2Fault ModelingDef
UNL - CSE - 932
CSCE 932, Spring 2009Syllabus1Contact InformationMy web page: cse.unl.edu/~seth AvH 359, seth@cse.unl.edu, 4725003 Office Hours: Flexible2Required Background Logic design, Boolean algebra Basic math background: probability theory, discret
UNL - CSE - 932
CSCE 932, Spring 2009Yield Analysis and Product Quality1OutlineYield, defect level, and manufacturing cost Clustered defects and yield model Test data analysis Example: SEMATECH chip Summary2Test PerformanceALL CHIPSTest FAIL PASS (Te
UNL - CSE - 932
BIST - Built-In Self-Tests s sssDefinition of BIST Pattern generator s LFSR Response analyzer s MISR s Aliasing probability BIST architectures s Test per scan s Test per clock s Circular self-test s Memory BIST SummaryBIST 1Copyright 2005,
UNL - CSE - 932
CSCE 932, Spring 2009Test Generation for Combinational Logic1OutlineFundamental Concepts Test Generation AlgorithmsMultivalued Algebras Complexity of test generation PODEM BooleanSatisfiability BasedStructure vs. Function Boolean Difference
UNL - CSE - 430
Study Guide for CSCE430/830 Prerequisite Test (Overview of CSCE230: Computer Organization), Fall 2006 General Knowledge of Computer Organization: 1. Successful software development requires knowledge of computer organization. 2. Instructions and data
UNL - CSE - 430
UNL - CSE - 488
Programmable Computer RemoteSilicon Samurai Kyle Brown John Vogel Luke WilsonMarch 28, 2008Abstract: Though remote control devices for computer programs are commercially available, all are either limited-functionality or special-purpose. The PCR
UNL - CSE - 488
A Portable and Scalable Interactive Manikin SystemSubmitted to Microsoft by Team iDoll: Caleb Ho Johnny Ho Alan Huang Noel WuThe University of British Columbia Vancouver, British Columbia, Canada May 18, 20071. Executive Summary Cardiopulmonary
UNL - CSE - 488
Networked Braille Learning Environment"Gh. Asachi" Technical University of Iasi, Romania, EUNetworked Braille Learning Environment Team: Smart WritersTeam members: Bogdan Holmanu, Bogdan Tanasa Ionel Vuza Alexandru VranescuMentor: Florin Pant
UNL - CSE - 430
UNL - CSE - 489
CSCE 489, Spring 2009 Prerequisite Test1 [Amdahl's law]: Suppose we make an enhancement to a computer that improves some mode of execution by a factor of 20. Enhanced mode is used 25% of the time, measured as a percentage of the execution time when
UNL - CSE - 430
Computer ArchitectureFall 2007Instructor: Dr. Hong Jiangjiang@cse.unl.edu Cse.unl.edu/~jiang/cse430CSCE430/830472-6747Department of Computer Science & EngineeringUniversity of Nebraska-LincolnClassroom: 109 Avery Hall; Time: 11:30am-12:2
UNL - CSE - 430
Homework Assignment V
UNL - CSE - 488
Multi-functional SystemBased on Palm Print FeatureTeam members:Licong ZHANG Chenqi WANG Yanhui XIAO Dandan LI Clarence1106@gmail.com cikymi@126.com 03281142@bjtu.edu.cn 03281186@bjtu.edu.cnMentor:Xiaoming DING xmding@bjtu.edu.cnInnobeyond, a
UNL - CSE - 430
Homework Assignment III
UNL - CSE - 432
UNL - CSE - 488
TRIUMVIRATEdorMouseFinal ReportDavid Kim, Erick Lang, BinhAn Ta 5/2/2008This document is the final report on the project dorMouse: a project to develop an accelerometer based solution which addresses problems found in traditional computer mice
UNL - CSE - 430
Homework Assignment IV
UNL - CSE - 430
An Introduction to FPGA and SOPC Development BoardYong WangOutline What are Programmable Logic Devices? Architecture and Examples Why FPGA? Vendors and Devices Development on Altera Device SummaryProgrammable Logic Devices Programmable di
UNL - CSE - 488
CSCE 488: Computer Engineering Professional Development Getting Started With ProjectsYuyan Xue and Sharad SethOutlineIntroduction to Senior Design Project Available Resources Previous Projects Attractive Contests Useful Links8/29/2006Getti
UNL - CSE - 430
Homework Assignment III
UNL - CSE - 430
Term Project OverviewYong WangIntroduction Goal familiarize with the design and implementation of a simple pipelined RISC processor What to do Build a processor from scratch (single-cycle implementation) Add some functions Pipeline datapath