R3000UM-rabbit3000_user_manual
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R3000UM-rabbit3000_user_manual

Course Number: ECE 477, Fall 2008

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Rabbit 3000 Microprocessor Users Manual 0190108 040731O Rabbit 3000 Microprocessor Users Manual Part Number 019-0108 040731O Printed in U.S.A. 20022004 Rabbit Semiconductor All rights reserved. Rabbit Semiconductor reserves the right to make changes and improvements to its products without providing notice. Trademarks Rabbit and Rabbit 3000 are registered trademarks of Rabbit Semiconductor. Dynamic C is a...

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3000 Rabbit Microprocessor Users Manual 0190108 040731O Rabbit 3000 Microprocessor Users Manual Part Number 019-0108 040731O Printed in U.S.A. 20022004 Rabbit Semiconductor All rights reserved. Rabbit Semiconductor reserves the right to make changes and improvements to its products without providing notice. Trademarks Rabbit and Rabbit 3000 are registered trademarks of Rabbit Semiconductor. Dynamic C is a registered trademark of Z-World, Inc. Rabbit Semiconductor 2932 Spafford Street Davis, California 95616-6800 USA Telephone: (530) 757-8400 Fax: (530) 757-8402 www.rabbitsemiconductor.com Rabbit 3000 Microprocessor TABLE OF CONTENTS Chapter 1. Introduction 1 1.1 Features and Specifications Rabbit 3000..............................................................................................2 1.2 Summary of Rabbit 3000 Advantages ..................................................................................................6 1.3 Differences Rabbit 3000 vs. Rabbit 2000 .............................................................................................7 Chapter 2. Rabbit 3000 Design Features 9 2.1 The Rabbit 8-bit Processor vs. Other Processors................................................................................10 2.2 Overview of On-Chip Peripherals and Features .................................................................................11 2.2.1 5 V Tolerant Inputs ....................................................................................................................11 2.2.2 Serial Ports .................................................................................................................................11 2.2.3 System Clock .............................................................................................................................12 2.2.4 32.768 kHz Oscillator Input .......................................................................................................12 2.2.5 Parallel I/O .................................................................................................................................13 2.2.6 Slave Port ...................................................................................................................................14 2.2.7 Auxiliary I/O Bus .......................................................................................................................15 2.2.8 Timers ........................................................................................................................................15 2.2.9 Input Capture Channels ..............................................................................................................16 2.2.10 Quadrature Encoder Inputs ......................................................................................................17 2.2.11 Pulse Width Modulation Outputs .............................................................................................17 2.2.12 Spread Spectrum Clock ............................................................................................................18 2.2.13 Separate Core and I/O Power Pins ...........................................................................................18 2.3 Design Standards ................................................................................................................................18 2.3.1 Programming Port ......................................................................................................................18 2.3.2 Standard BIOS ...........................................................................................................................19 2.4 Dynamic C Support for the Rabbit .....................................................................................................19 Chapter 3. Details on Rabbit Microprocessor Features 21 3.1 Processor Registers .............................................................................................................................21 3.2 Memory Mapping ...............................................................................................................................23 3.2.1 Extended Code Space .................................................................................................................26 3.2.2 Separate I and D Space - Extending Data Memory ...................................................................27 3.2.3 Using the Stack Segment for Data Storage ................................................................................29 3.2.4 Practical Memory Considerations ..............................................................................................30 3.3 Instruction Set Outline ........................................................................................................................32 3.3.1 Load Immediate Data to a Register ............................................................................................33 3.3.2 Load or Store Data from or to a Constant Address ....................................................................33 3.3.3 Load or Store Data Using an Index Register .............................................................................34 3.3.4 Register-to-Register Move .........................................................................................................35 3.3.5 Register Exchanges ....................................................................................................................35 3.3.6 Push and Pop Instructions ..........................................................................................................36 3.3.7 16-bit Arithmetic and Logical Ops ............................................................................................36 3.3.8 Input/Output Instructions ...........................................................................................................39 3.4 How to Do It in Assembly LanguageTips and Tricks ....................................................................40 3.4.1 Zero HL in 4 Clocks ...................................................................................................................40 3.4.2 Exchanges Not Directly Implemented .......................................................................................40 3.4.3 Manipulation of Boolean Variables ...........................................................................................40 3.4.4 Comparisons of Integers ............................................................................................................41 3.4.5 Atomic Moves from Memory to I/O Space ...............................................................................43 Users Manual 3.5 Interrupt Structure .............................................................................................................................. 44 3.5.1 Interrupt Priority ........................................................................................................................ 44 3.5.2 Multiple External Interrupting Devices ..................................................................................... 46 3.5.3 Privileged Instructions, Critical Sections and Semaphores ....................................................... 46 3.5.4 Critical Sections ......................................................................................................................... 47 3.5.5 Semaphores Using Bit B,(HL) .................................................................................................. 47 3.5.6 Computed Long Calls and Jumps .............................................................................................. 48 Chapter 4. Rabbit Capabilities 49 4.1 Precisely Timed Output Pulses .......................................................................................................... 49 4.1.1 Pulse Width Modulation to Reduce Relay Power ..................................................................... 50 4.2 Open-Drain Outputs Used for Key Scan............................................................................................ 51 4.3 Cold Boot ........................................................................................................................................... 52 4.4 The Slave Port .................................................................................................................................... 53 4.4.1 Slave Rabbit As A Protocol UART ........................................................................................... 54 Chapter 5. Pin Assignments and Functions 55 5.1 LQFP Package.................................................................................................................................... 56 5.1.1 Pinout ......................................................................................................................................... 56 5.1.2 Mechanical Dimensions and Land Pattern ................................................................................ 57 5.2 Ball Grid Array Package ................................................................................................................... 59 5.2.1 Pinout ......................................................................................................................................... 59 5.2.2 Mechanical Dimensions and Land Pattern ................................................................................ 60 5.3 Rabbit Pin Descriptions...................................................................................................................... 62 5.4 Bus Timing......................................................................................................................................... 64 5.5 Description of Pins with Alternate Functions .................................................................................... 65 5.6 DC Characteristics.............................................................................................................................. 68 5.7 I/O Buffer Sourcing and Sinking Limit.............................................................................................. 69 Chapter 6. Rabbit Internal I/O Registers 71 6.1 Default Values for all the Peripheral Control Registers..................................................................... 73 Chapter 7. Miscellaneous Functions 79 7.1 Processor Identification...................................................................................................................... 79 7.2 Rabbit Oscillators and Clocks ............................................................................................................ 80 7.3 Clock Doubler .................................................................................................................................... 83 7.4 Clock Spectrum Spreader................................................................................................................... 86 7.5 Chip Select Options for Low Power .................................................................................................. 87 7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN .......................................................................... 90 7.7 Time/Date Clock (Real-Time Clock) ................................................................................................. 91 7.8 Watchdog Timer................................................................................................................................. 93 7.9 System Reset ...................................................................................................................................... 95 7.10 Rabbit Interrupt Structure................................................................................................................. 97 7.10.1 External Interrupts ................................................................................................................... 99 7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 .......................................................... 100 7.11 Bootstrap Operation ....................................................................................................................... 101 7.12 Pulse Width Modulator .................................................................................................................. 103 7.13 Input Capture.................................................................................................................................. 105 7.14 Quadrature Decoder ....................................................................................................................... 110 Chapter 8. Memory Interface and Mapping 8.1 8.2 8.3 8.4 115 Interface for Static Memory Chips................................................................................................... 115 Memory Mapping Overview............................................................................................................ 117 Memory-Mapping Unit .................................................................................................................... 117 Memory Interface Unit..................................................................................................................... 119 Rabbit 3000 Microprocessor 8.5 Memory Bank Control Registers ......................................................................................................120 8.5.1 Optional A16, A19 Inversions by Segment (/CS1 Enable) .....................................................121 8.6 Allocation of Extended Code and Data ............................................................................................123 8.7 Instruction and Data Space Support..................................................................................................124 8.8 How the Compiler Compiles to Memory .........................................................................................127 Chapter 9. Parallel Ports 129 9.1 Parallel Port A...................................................................................................................................130 9.2 Parallel Port B ...................................................................................................................................131 9.3 Parallel Port C ...................................................................................................................................132 9.4 Parallel Port D...................................................................................................................................133 9.5 Parallel Port E ...................................................................................................................................137 9.6 Parallel Port F ...................................................................................................................................140 9.6.1 Using Parallel Port A and Parallel Port F ................................................................................141 9.7 Parallel Port G...................................................................................................................................143 Chapter 10. I/O Bank Control Registers Chapter 11. Timers 145 149 11.1 Timer A...........................................................................................................................................150 11.1.1 Timer A I/O Registers ............................................................................................................151 11.1.2 Practical Use of Timer A .......................................................................................................155 11.2 Timer B ...........................................................................................................................................156 11.2.1 Using Timer B ........................................................................................................................159 Chapter 12. Rabbit Serial Ports 161 12.1 Serial Port Register Layout.............................................................................................................164 12.2 Serial Port Registers........................................................................................................................166 12.3 Serial Port Interrupt ........................................................................................................................179 12.4 Transmit Serial Data Timing ..........................................................................................................180 12.5 Receive Serial Data Timing ............................................................................................................181 12.6 Clocked Serial Ports........................................................................................................................182 12.7 Clocked Serial Timing ....................................................................................................................185 12.7.1 Clocked Serial Timing With Internal Clock ..........................................................................185 12.7.2 Clocked Serial Timing with External Clock ..........................................................................185 12.8 Synchronous Communications on Ports E and F............................................................................187 12.9 Serial Port Software Suggestions....................................................................................................192 12.9.1 Controlling an RS-485 Driver and Receiver ..........................................................................193 12.9.2 Transmitting Dummy Characters ...........................................................................................193 12.9.3 Transmitting and Detecting a Break ......................................................................................194 12.9.4 Using A Serial Port to Generate a Periodic Interrupt .............................................................194 12.9.5 Extra Stop Bits, Sending Parity, 9th Bit Communication Schemes .......................................194 12.9.6 Parity, Extra Stop Bits with 7-Data-Bit Characters ...............................................................195 12.9.7 Parity, Extra Stop Bits with 8-Data-Bit Characters ...............................................................195 12.9.8 Supporting 9th Bit Communication Protocols .......................................................................196 12.9.9 Rabbit-Only Master/Slave Protocol .......................................................................................196 12.9.10 Data Framing/Modbus .........................................................................................................196 Chapter 13. Rabbit Slave Port 199 13.1 Hardware Design of Slave Port Interconnection ............................................................................204 13.2 Slave Port Registers ........................................................................................................................204 13.3 Applications and Communications Protocols for Slaves................................................................206 13.3.1 Slave Applications .................................................................................................................206 13.3.2 Master-Slave Messaging Protocol .........................................................................................207 Users Manual Chapter 14. Rabbit 3000 Clocks 209 14.1 Low-Power Design......................................................................................................................... 210 Chapter 15. EMI Control 211 15.1 Power Supply Connections and Board Layout .............................................................................. 212 15.2 Using the Clock Spectrum Spreader .............................................................................................. 212 Chapter 16. AC Timing Specifications 215 16.1 Memory Access Time .................................................................................................................... 215 16.2 I/O Access Time............................................................................................................................. 223 16.3 Further Discussion of Bus and Clock Timing ................................................................................ 225 16.4 Maximum Clock Speeds ................................................................................................................ 227 16.5 Power and Current Consumption ................................................................................................... 229 16.6 Current Consumption Mechanisms................................................................................................ 232 16.7 Sleepy Mode Current Consumption ............................................................................................... 233 16.8 Memory Current Consumption ...................................................................................................... 234 16.9 Battery-Backed Clock Current Consumption ................................................................................ 235 16.10 Reduced-Power External Main Oscillator.................................................................................... 236 Chapter 17. Rabbit BIOS and Virtual Driver 237 17.1 The BIOS........................................................................................................................................ 237 17.1.1 BIOS Services ....................................................................................................................... 237 17.1.2 BIOS Assumptions ................................................................................................................ 238 17.2 Virtual Driver ................................................................................................................................. 238 17.2.1 Periodic Interrupt ................................................................................................................... 238 17.2.2 Watchdog Timer Support ...................................................................................................... 238 Chapter 18. Other Rabbit Software 241 18.1 Power Management Support .......................................................................................................... 241 18.2 Reading and Writing I/O Registers ................................................................................................ 242 18.2.1 Using Assembly Language .................................................................................................... 242 18.2.2 Using Library Functions ........................................................................................................ 242 18.3 Shadow Registers ........................................................................................................................... 243 18.3.1 Updating Shadow Registers .................................................................................................. 243 18.3.2 Interrupt While Updating Registers ....................................................................................... 243 18.3.3 Write-only Registers Without Shadow Registers .................................................................. 244 18.4 Timer and Clock Usage.................................................................................................................. 244 Chapter 19. Rabbit Instructions 247 19.1 Load Immediate Data ..................................................................................................................... 250 19.2 Load & Store to Immediate Address.............................................................................................. 250 19.3 8-bit Indexed Load and Store ......................................................................................................... 250 19.4 16-bit Indexed Loads and Stores .................................................................................................... 250 19.5 16-bit Load and Store 20-bit Address ............................................................................................ 251 19.6 Register to Register Moves ............................................................................................................ 251 19.7 Exchange Instructions .................................................................................................................... 252 19.8 Stack Manipulation Instructions..................................................................................................... 252 19.9 16-bit Arithmetic and Logical Ops................................................................................................. 252 19.10 8-bit Arithmetic and Logical Ops................................................................................................. 253 19.11 8-bit Bit Set, Reset and Test......................................................................................................... 254 19.12 8-bit Increment and Decrement.................................................................................................... 254 19.13 8-bit Fast A Register Operations .................................................................................................. 255 19.14 8-bit Shifts and Rotates ................................................................................................................ 255 19.15 Instruction Prefixes ...................................................................................................................... 256 Rabbit 3000 Microprocessor 19.16 19.17 19.18 19.19 Block Move Instructions...............................................................................................................256 Control Instructions - Jumps and Calls.........................................................................................257 Miscellaneous Instructions ...........................................................................................................257 Privileged Instructions ..................................................................................................................258 Chapter 20. Differences Rabbit vs. Z80/Z180 Instructions Chapter 21. Instructions in Alphabetical Order With Binary Encoding Appendix A. The Rabbit Programming Port 259 261 269 A.1 Use of the Programming Port as a Diagnostic/Setup Port ...............................................................270 A.2 Alternate Programming Port ............................................................................................................270 A.3 Suggested Rabbit Crystal Frequencies.............................................................................................271 Appendix B. Rabbit 3000 Revisions 273 B.1 Discussion of Fixes and Improvements ...........................................................................................276 B.1.1 Rabbit Internal I/O Registers ...................................................................................................277 B.1.2 Peripheral and ISR Address ....................................................................................................280 B.1.3 Revision-Level ID Register .....................................................................................................282 B.1.4 System/User Mode ..................................................................................................................283 B.1.5 Memory Protection ..................................................................................................................284 B.1.6 Stack Protection .......................................................................................................................289 B.1.7 RAM Segment Relocation .......................................................................................................291 B.1.8 Secondary Watchdog Timer ....................................................................................................292 B.1.9 New Opcodes ..........................................................................................................................293 B.1.10 Expanded I/O Memory Addressing .......................................................................................295 B.1.11 External I/O Improvements ...................................................................................................296 B.1.12 Short Chip Select Timing for Writes .....................................................................................297 B.1.13 Pulse Width Modulator Improvements .................................................................................311 B.1.14 Quadrature Decoder Improvements ......................................................................................314 B.2 Pins with Alternate Functions ..........................................................................................................316 Appendix C. System/User Mode 317 C.1 System/User Mode Opcodes ............................................................................................................318 C.2 System/User Mode Registers ...........................................................................................................319 C.3 Interrupts ..........................................................................................................................................321 C.3.1 Peripheral Interrupt Prioritization ...........................................................................................322 C.4 Using the System/User Mode...........................................................................................................324 C.4.1 Memory Protection Only .........................................................................................................324 C.4.2 Mixed System/User Mode Operation ......................................................................................325 C.4.3 Complete Operating System ....................................................................................................326 Appendix D. Rabbit 3000A Internal I/O Registers Notice to Users Index 327 335 337 Users Manual Rabbit 3000 Microprocessor 1. INTRODUCTION Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in small and medium-scale controllers. The first microprocessor was the Rabbit 2000. The second microprocessor, now available, is the Rabbit 3000. Rabbit microprocessor designers have had years of experience using Z80, Z180, and HD64180 microprocessors in small controllers. The Rabbit shares a similar architecture and a high degree of compatibility with these microprocessors, but it is a vast improvement. The Rabbit 3000 has been designed in close cooperation with Z-World, Inc., a long-time manufacturer of low-cost single-board computers. Z-Worlds products are supported by an innovative C-language development system (Dynamic C). Z-World is providing the software development tools for the Rabbit 3000. The Rabbit 3000 is easy to use. Hardware and software interfaces are as uncluttered and are as foolproof as possible. The Rabbit has outstanding computation speed for a microprocessor with an 8-bit bus. This is because the Z80-derived instruction set is very compact, and the timing of the memory interface allows higher clock speeds for a given memory speed. Microprocessor hardware and software development is easy for Rabbit users. In-circuit emulators are not needed and will not be missed by the Rabbit developer. Software development is accomplished by connecting a simple interface cable from a PC serial port to the Rabbit-based target system or by performing software development and debugging over a network or the Internet using interfaces and tools provided by Rabbit Semiconductor. Users Manual 1 1.1 Features and Specifications Rabbit 3000 128-pin LQFP package. Operating voltage 1.8 V to 3.6 V. Clock speed to 54+ MHz. All specifications are given for both industrial and commercial temperature and voltage ranges. Rabbit microprocessors are low-cost. Industrial specifications are for 3.3 V 10% and a temperature range from -40C to +85C. Modified commercial specifications are for a voltage variation of 5% and a temperature range from -40C to 70C. 1-megabyte code-data space allows C programs with 50,000+ lines of code. The extended Z80-style instruction set is C-friendly, with short and fast opcodes for the most important C operations. Four levels of interrupt priority make a fast interrupt response practical for critical applications. The maximum time to the first instruction of an interrupt routine is about 0.5 s at a clock speed of 50 MHz. Access to I/O devices is accomplished by using memory access instructions with an I/O prefix. Access to I/O devices is thus faster and easier compared to processors with a distinct and narrow I/O instruction set. As an option the auxiliary I/O bus can be enabled to use separate pins for address and data, allowing the I/O bus to have a greater physical extent with less EMI and less conflict with the requirements of the fast memory bus.(Further described below.) Hardware design is simple. Up to six static memory chips (such as RAM and flash memory) connect directly to the microprocessor with no glue logic. A memory-access time of 55 ns suffices to support up to a 30 MHz clock with no wait states; with a 30 ns memory-access time, a clock speed of up to 50 MHz is possible with no wait states. Most I/O devices may be connected without glue logic. The memory read cycle is two clocks long. The write cycle is 3 clocks long. A clean memory and I/O cycle completely avoid the possibility of bus fights. Peripheral I/O devices can usually be interfaced in a glueless fashion using the common /IORD and /IOWR strobes in addition to the user-configurable IO strobes on Parallel Port E. The Parallel Port E pins can be configured as I/O read, write, read/write, or chip select when they are used as I/O strobes. EMI reduction features reduce EMI levels by as much as 25 dB compared to other similar microprocessors. Separate power pins for the on-chip I/O buffers prevent high-frequency noise generated in the processor core from propagating to the signal output pins. A built-in clock spectrum spreader reduces electromagnetic interference and facilitates passing EMI tests to prove compliance with government regulatory requirements. As a consequence, the designer of a Rabbit-3000-based system can be assured of passing FCC or CE EMI tests as long as minimal design precautions are followed. The Rabbit may be cold-booted via a serial port or the parallel access slave port. This means that flash program memory may be soldered in unprogrammed, and can be reprogrammed at any time without any assumption of an existing program or BIOS. 2 Rabbit 3000 Microprocessor A Rabbit that is slaved to a master processor can operate entirely with volatile RAM, depending on the master for a cold program boot. There are 56 parallel I/O lines (shared with serial ports). Some I/O lines are timer synchronized, which permits precisely timed edges and pulses to be generated under combined hardware and software control. Pulse-width modulation outputs are implemented in addition to the timer-synchronization feature (see below). Four pulse width modulated (PWM) outputs are implemented by special hardware. The repetition frequency and the duty cycle can be varied over a wide range. The resolution of the duty cycle is 1 part in 1024. There are six serial ports. All six serial ports can operate asynchronously in a variety of commonly used operating modes. Four of the six ports (designated A, B, C, D) support clocked serial communications suitable for interfacing with SPI devices and various similar devices such as A/D converters and memories that use a clocked serial protocol. Two of the ports, E and F, support HDLC/SDLC synchronous communication. These ports have a 4-byte FIFO and can operate at a high data rate. Ports E and F also have a digital phase-locked loop for clock recovery, and support popular data-encoding methods. High data rates are supported by all six serial ports. The asynchronous ports also support the 9th bit network scheme as well as infrared transmission using the IRDA protocol. The IRDA protocol is also supported in SDLC format by the two ports that support SDLC. A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a master processor. The 8-bit slave port has six 8-bit registers, 3 for each direction of communication. Independent strobes and interrupts are used to control the slave port in both directions. Only a Rabbit and a RAM chip are needed to construct a complete slave system, if the clock and reset control are shared with the master processor There is an option to enable an auxiliary I/O bus that is separate from the memory bus. The auxiliary I/O bus toggles only on I/O instructions. It reduces EMI and speeds the operation of the memory bus, which only has to connect to memory chips when the auxiliary I/O bus is used to connect I/O devices. This important feature makes memory design easy and allows a more relaxed approach to interfacing I/O devices. The built-in battery-backable time/date clock uses an external 32.768 kHz crystal oscillator. The suggested model circuit for the external oscillator utilizes a single tiny logic active component. The time/date clock can be used to provide periodic interrupts every 488 s. Typical battery current consumption is about 3 A. Numerous timers and counters can be used to generate interrupts, baud rate clocks, and timing for pulse generation. Two input-capture channels can be used to measure the width of pulses or to record the times at which a series of events take place. Each capture channel has a 16-bit counter and can take input from one or two pins selected from any of 16 pins. Two quadrature decoder units accept input from incremental optical shaft encoders. These units can be used to track the motion of a rotating shaft or similar device. Users Manual 3 A built-in clock doubler allows -frequency crystals to be used. The built-in main clock oscillator uses an external crystal or a ceramic resonator. Typical crystal or resonator frequencies are in the range of 1.8 MHz to 30 MHz. Since precision timing is available from the separate 32.768 kHz oscillator, a low-cost ceramic resonator with percent error is generally satisfactory. The clock can be doubled or divided down to modify speed and power dynamically. The I/O clock, which clocks the serial ports, is divided separately so as not to affect baud rates and timers when the processor clock is divided or multiplied. For ultra low power operation, the processor clock can be driven from the separate 32.768 kHz oscillator and the main oscillator can be powered down. This allows the processor to operate at approximately between 20 and 100 A and still execute instructions at the rate of up to 10,000 instructions per second. The 32.768 kHz clock can also be divided by 2, 4, 8 or 16 to reduce power. This sleepy mode is a powerful alternative to sleep modes of operation used by other processors. Processor current requirement is approximately 65 mA at 30 MHz and 3.3 V. The current is proportional to voltage and clock speedat 1.8 V and 3.84 MHz the current would be about 5 mA, and at 1 MHz the current is reduced to about 1 mA. To allow extreme low power operation there are options to reduce the duty cycle of memories when running at low clock speeds by only enabling the chip select for a brief period, long enough to complete a read. This greatly reduces the power used by flash memory when operating at low clock speeds. The excellent floating-point performance is due to a tightly coded library and powerful processing capability. For example, a 50 MHz clock takes 7 s for a floating add, 7 s for a multiply, and 20 s for a square root. In comparison, a 386EX processor running with an 8-bit bus at 25 MHz and using Borland C is about 20 times slower. There is a built-in watchdog timer. The standard 10-pin programming port eliminates the need for in-circuit emulators. A very simple 10-pin connector can be used to download and debug software using Z-Worlds Dynamic C and a simple connection to a PC serial port. The incremental cost of the programming port is extremely small. Figure 1-1 shows a block diagram of the Rabbit. 4 Rabbit 3000 Microprocessor SMODE0 RESOUT /BUFEN /IORD /WDTOUT SMODE1 /RESET /IOWR STATUS D[7:0] Data Buffer External Interface CPU A[19:0] ADDRESS BUS Address Buffer Spectrum Spreader Memory Management/ Control Clock Doubler CLK Memory Chip Interface Parallel Ports Port A Port B Port C Port D Port E Port F /CS2, /CS1, /CS0 /OE1, /OE0 /WE1, /WE0 (8 bits) PA [7:0] PB[7:0] PC[7:0] PD[7:0] PE[7:0] PF[7:0] PG[7:0] XTALA1 XTALA2 Fast Oscillator Global Power Save & Clock Distribution Timer A Port G Serial Port A Timer B CLK32K Asynch Synch Serial Serial Asynch Synch Bootstrap Bootstrap Asynch Serial IrDA IrDA Bootstrap TXA, RXA, CLKA, ATXA, ARXA 32.768 kHz Clock Input DATA BUS Real-Time Clock Watchdog Timer Periodic Interrupt Serial Ports B,C,D (8 bits) Asynch Serial Synch Serial Asynch Serial IrDA TXB, RXB, CLKB, ATXB, ARXB TXC, RXC, CLKC TXD, RXD, CLKD Serial Ports E, F Asynch Serial HDLC SDLC Asynch Serial IrDA HDLC/SDLC IrDA TXE, RXE TCLKE, RCLKE TXF, RXF TCLKF, RCLKF ID[7:0] IA[5:0] I[7:0] External I/O Chip Interface Pulse Width Modulation Quadrature Decoder Input Capture Slave Port Slave Interface Bootstrap Interface PWM[3:0] QD1A, QD1B QD2A, QD2B AQD1A, AQD1B AQD2A, AQD2B PC[7,5,3,1] PD[7,5,3,1] PF[7,5,3,1] PG[7,5,3,1] SD[7:0] SA[1:0], /SCS, /SRD, /SWR, /SLAVEATTN INT0A, INT1A INT0B, INT1B External Interrupts Figure 1-1. Rabbit 3000 Block Diagram Users Manual 5 1.2 Summary of Rabbit 3000 Advantages The glueless architecture makes it is easy to design the hardware system. There are a lot of serial ports and they can communicate very fast. Precision pulse and edge generation is a standard feature. EMI is at extremely low levels. Interrupts can have multiple priorities. Processor speed and power consumption are under program control. The ultra low power mode can perform computations and execute logical tests since the processor continues to execute, albeit at 32 kHz or even as slow as 2 kHz. The Rabbit may be used to create an intelligent peripheral or a slave processor. For example, protocol stacks can be off loaded to a Rabbit slave. The master can be any processor. The Rabbit can be cold-booted so unprogrammed flash memory can be soldered in place. You can write serious software, be it 1,000 or 50,000 lines of C code. The tools are there and they are low in cost. If you know the Z80 or Z180, you know most of the Rabbit. A simple 10-pin programming interface replaces in-circuit emulators and PROM programmers. The battery-backable time/date clock is included. The standard Rabbit chip is made to industrial temperature and voltage specifications. The Rabbit 3000 is backed by extensive software development tools and libraries, especially in the area of networking and embedded Internet. 6 Rabbit 3000 Microprocessor 1.3 Differences Rabbit 3000 vs. Rabbit 2000 For the benefit of readers who are familiar with the Rabbit 2000 microprocessor the Rabbit 3000 is contrasted with the Rabbit 2000 in the table below. Feature Maximum clock speed Maximum crystal frequency main oscillator (may be doubled internally) 32.768 kHz crystal oscillator Maximum operating voltage Maximum I/O input voltage Current consumption Number of package pins Size of package Rabbit 3000 54 MHz 30 MHz External 3.6 V 5.5 V 2 mA/MHz @ 3.3 V 128 16 16 1.5 mm LQFP 10 10 1.2 mm TFBGA Rabbit 2000 30 MHz 32 MHz Internal 5.5 V 5.5 V 4 mA/MHz @5 V 100 24 18 3 mm PQFP Spacing between package pins Separate power and ground for I/O buffers (EMI reduction) Clock Spectrum Spreader (EMI reduction) Clock Modes Power Down Modes 0.4 mm (16 mils) LQFP 0.65 mm (26 mils) PQFP 0.8 mm TFBGA Yes Yes 1x, 2x, /2, /3, /4, /6, /8 Sleepy (32 kHz) Ultra-Sleepy (16, 8, 2 kHz) Short CS (CLK /4 /6 /8) Self Timed (32,16,8,2 kHz) Yes 7 Yes 6 4 (A, B, C, D) 2 (E, F) 6 No Rabbit 2000B and Rabbit 2000C versions. 1x, 2x, /4, /8 Sleepy (32 kHz) Low Power Memory Control (Chip Select) Extended memory timing for high freq. operation Number of 8-bit I/O ports Auxiliary I/O Data/Address bus Number of serial ports Serial ports capable of SPI/clocked serial Serial ports capable of SDLC/HDLC Asynch serial ports with support for IrDA communications None No 5 None 4 2 (A, B) None None Users Manual 7 Feature Serial ports with support for SDLC/HDLC IrDA communications Maximum asynchronous baud rate Input capture unit Rabbit 3000 2 clock speed/8 2 Rabbit 2000 None clock speed/32 None 8 Rabbit 3000 Microprocessor 2. RABBIT 3000 DESIGN FEATURES The Rabbit 3000 is an evolutionary design. The processor and instruction set are nearly identical to the immediate predecessor processor, the Rabbit 2000. Both the Rabbit 3000 and the Rabbit 2000 follow in broad outline the instruction set and the register layout of the Z80 and Z180. Compared to the Z180 the instruction set has been augmented by a substantial number of new instructions. Some obsolete or redundant Z180 instructions have been dropped to make available efficient 1-byte opcodes for important new instructions. (see Chapter 20, Differences Rabbit vs. Z80/Z180 Instructions,.) The advantage of this evolutionary approach is that users familiar with the Z80 or Z180 can immediately understand Rabbit assembly language. Existing Z80 or Z180 source code can be assembled or compiled for the Rabbit with minimal changes. Changing technology has made some features of the Z80/Z180 family obsolete, and these features have been dropped in the Rabbit. For example, the Rabbit has no special support for dynamic RAM but it has extensive support for static memory. This is because the price of static memory has decreased to the point that it has become the preferred choice for medium-scale embedded systems. The Rabbit has no support for DMA (direct memory access) because most of the uses for which DMA is traditionally used do not apply to embedded systems, or they can be accomplished better in other ways, such as fast interrupt routines, external state machines or slave processors. Our experience in writing C compilers has revealed the shortcomings of the Z80 instruction set for executing the C language. The main problem is the lack of instructions for handling 16-bit words and for accessing data at a computed address, especially when the stack contains that data. New instructions correct these problems. Another problem with many 8-bit processors is their slow execution and a lack of numbercrunching ability. Good floating-point arithmetic is an important productivity feature in smaller systems. It is easy to solve many programming problems if an adequate floatingpoint capability is available. The Rabbits improved instruction set provides fast floatingpoint and fast integer math capabilities. The Rabbit supports four levels of interrupt priorities. This is an important feature that allows the effective use of fast interrupt routines for real-time tasks. Users Manual 9 2.1 The Rabbit 8-bit Processor vs. Other Processors The Rabbit 3000 processor has been designed with the objective of creating practical systems to solve real world problems in an economical fashion. A cursory comparison of the Rabbit 3000 compared to other processors with similar capabilities may miss certain Rabbit strong points. The Rabbit is a processor that can be used to build a system in which EMI is nearly absent, even at clock frequencies in excess of 40 MHz. This is due to the split power supply, the clock doubler, the clock spectrum spreader and the PC board layout advice (or processor core modules) that we provide. Low EMI is a huge timesaver for the designer pressed to meet schedules and pass government EMI tests of the final product. Execution speed with the Rabbit is usually a pleasant surprise compared to other processors. This is due to the well-chosen and compact instruction set partnered with and excellent compiler and library. We have many benchmarks, comparing the Rabbit to 186, 386, 8051, Z180 and ez80 families of processors that prove the point. The Rabbit memory bus is an exceptionally efficient and very clean design. No external logic is required to support static memory chips. Battery-backed external memory is supported by built-in functionality. During reduced-power slow-clock operation the memory duty cycle can be correspondingly reduced using built-in hardware, resulting in low power consumption by the memories. The Rabbit external bus uses 2 clocks for read cycles and 3 clocks for write cycles. This has many advantages compared to a single-clock design, and on closer examination the advantages of the single-clock system turn out to be mostly chimerical. The advantages include: easy design to avoid bus fights, clean write cycles with solid data and address hold times, flexibility to have memory output enable access times greater than of the bus cycle, and the ability to use an asymmetric clock generated by a clock doubler. The supposed advantage that single-clock systems have of double-speed bus operation is not possible with real-world memories unless the memory is backed with fast-cache RAM. The Rabbit 3000 operates at 3.6 V or less, but it has 5 V tolerant inputs and has a second complete bus for I/O operations that is separate from the memory bus. This second auxiliary bus can be enabled by the application as a designer option. These features make it easy to design systems that mix 3 V and 5 V components, and avoid the loading problems and the EMI problems that result if the memory bus is extended to connect with many I/O devices. The Rabbit may be remotely programmed, including complete cold-boot, via a serial link, Ethernet, or even via a network or the Internet using built in capabilities and/or the RabbitLink ethernet network accessory device. These capabilities proven and inexpensive to implement. The Rabbit 3000 on-chip peripheral complement is huge compared to competitive processors. 10 Rabbit 3000 Microprocessor The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data bus. Because the Rabbit makes the most of its external 8-bit bus and because it has a compact instruction set, its performance is as good as many 16-bit processors. We hesitate to compare the Rabbit to 32-bit processors, but there are undoubtedly occasions where the user can use a Rabbit instead of a 32-bit processor and save a vast amount of money. Many Rabbit instructions are 1 byte long. In contrast, the minimum instruction length on most 32-bit RISC processors is 32 bits. 2.2 Overview of On-Chip Peripherals and Features The on-chip peripherals were chosen based on our experience as to what types of peripheral devices are most useful in small embedded systems. The major on-chip peripherals are the serial ports, system clock, time/date oscillator, parallel I/O, slave port, motion encoders, pulse width modulators, pulse measurement, and timers. These and other features are described below. 2.2.1 5 V Tolerant Inputs The Rabbit 3000 operates on a voltage in the range of 1.8 V to 3.6 V, but most Rabbit 3000 input pins are 5 V tolerant. The exceptions are the power supply pins, and the oscillator buffer pins. When a 5 V signal is applied to 5 V tolerant pins, they present a high impedance even if the Rabbit power is off. The 5 V tolerant feature allows 5 V devices that have a suitable switching threshold to be directly connected to the Rabbit. This includes HCT family parts operated at 5 V that have an input threshold between 0.8 and 2 V. NOTE: CMOS devices operated at 5 V that have a threshold at 2.5 V are not suitable for direct connection because the Rabbit outputs do not rise above VDD, which cannot exceed 3.6 V, and is often specified as 3.3 V. Although a CMOS input with a 2.5 V threshold may switch at 3.3 V, it will consume excessive current and switch slowly. In order to translate between 5 V and 3.3 V, HCT family parts powered from 5 V can be used, and are often the best solution. There is also the LVT family of parts that operate from 2.0 V to 3.3 V, but that have 5 V tolerant inputs and are available from many suppliers. True level-translating parts are available with separate 3.3 V and 5 V supply pins, but these parts are not usually needed, and have design traps involving power sequencing. Many charge pump chips that perform DC to DC voltage conversion at low cost have been introduced in recent years. These are convenient for systems with dual voltage requirements. 2.2.2 Serial Ports There are six serial ports designated ports A, B, C, D, E, and F. All six serial ports can operate in an asynchronous mode up to a baud rate equal to the system clock divided by 8. The asynchronous ports use 7-bit or 8-bit data formats, with or without parity. A 9th bit address scheme, where an additional bit is set or cleared to mark the first byte of a message, is also supported. The serial port software driver can tell when the last byte of a message has finished transmitting from the output shift register - correcting an important defect of the Z180. This is Users Manual 11 important for RS-485 communication because a half duplex line driver cannot have the direction of transmission reversed until the last data bit has been sent. In many UARTs, including those on the Z180, it is difficult to generate an interrupt after the last bit is sent. A so called address bit can be transmitted as either high or low after the last data bit. The address bit, if used, is followed by a high stop bit. This facility can be used to transmit 2 stop bits or a parity bit if desired. The ability to directly transmit a high voltage level address bit was not included in the original revision of the Rabbit 2000 processor. Serial ports A, B, C and D can be operated in the clocked serial mode. In this mode, a clock line synchronously clocks the data in or out. Either the Rabbit serial port or the remote device can supply the clock. When the Rabbit provides the clock, the baud rate can be up to 1/2 of the system clock frequency. When the clock is provided by another device the maximum data rate is system clock divided by 6 due to the need to synchronize the externally supplied clock with the internal clock. The clocked serial mode may be used to support SPI bus devices. Serial Port A has special features. It can be used to cold-boot the system after reset. Serial Port A is the normal port that is used for software development under Dynamic C. All the serial ports have a special timing mode that supports infrared data communications standards. 2.2.3 System Clock The main oscillator uses an external crystal with a frequency typically in the range from 1.8 MHz to 26 MHz. The processor clock is derived from the oscillator output by either doubling the frequency, using the frequency directly, or dividing the frequency by 2, 4, 6 or by 8. The processor clock can also be driven by the 32.768 kHz real-time clock oscillator for very low power operation, in which case the main oscillator can be shut down under software control. 2.2.4 32.768 kHz Oscillator Input The 32.768 kHz oscillator input is designed to accept a 32.768 kHz clock. A suggested lowpower clock circuit using tiny logic parts is documented and low in cost. The 32.768 kHz clock is used to drive a battery-backable (there is a separate power pin) internal 48-bit counter that serves as a real-time clock (RTC). The counter can be set and read by software and is intended for keeping the date and time. There are enough bits to keep the date for more than 100 years. The 32.768 kHz oscillator input is also used to drive the watchdog timer and to generate the baud clock for Serial Port A during the cold-boot sequence. 12 Rabbit 3000 Microprocessor 2.2.5 Parallel I/O There are 56 parallel input/output lines divided among seven 8-bit ports designated A through G. Most of the port lines have alternate functions, such as serial data or chip select strobes. Parallel Ports D, E, F, and G have the capability of timer-synchronized outputs. The output registers are cascaded as shown in Figure 2-1. Load Data Load Clock Timer Clock Output Port Figure 2-1. Cascaded Output Registers for Parallel Ports D and E Stores to the port are loaded in the first-level register. That register in turn is transferred to the output register on a selected timer clock. The clock can be selected to be the output of Timer A1, B1, B2 or the peripheral clock (divided by 2?). The timer signal can also cause an interrupt that can be used to set up the next bit to be output on the next timer pulse. This feature can be used to generate precisely controlled pulses whose edges are positioned with high accuracy in time. Applications include communications signaling, pulse width modulation and driving stepper motors. (A separate pulse width modulation facility is also included in the Rabbit 3000.) External Input D Q D Q Filtered Input peripheral clock Figure 2-2. Digital Filtering Input Pins Input pins to the parallel ports are filtered by cascaded D flip flops as shown in Figure 2-2. This prevents pulses shorter then the peripheral clock from being recognized, synchronizes external pulses to the internal clock, and avoids problems with meta stability (temporarily indeterminate logical conditions due to marginal set up time with respect to the clock). Users Manual 13 2.2.6 Slave Port The slave port is designed to allow the Rabbit to be a slave to another processor, which could be another Rabbit. The port is shared with Parallel Port A and is a bidirectional data port. The master can read any of three registers selected via two select lines that form the register address and a read strobe that causes the register contents to be output by the port. These same registers can be written as I/O registers by the Rabbit slave. Three additional registers transmit data in the opposite direction. They are written by the master by means of the two select lines and a write strobe. Figure 2-3 shows the data paths in the slave port. Rabbit 3000 Master Processor Input Register Output Registers CPU Control Slave Interface Registers Figure 2-3. Slave-Port Data Paths The slave Rabbit can read the same registers as I/O registers. When incoming data bits are written into one of the registers, status bits indicate which registers have been written, and an optional interrupt can be programmed to take place when the write occurs. When the slave writes to one of the registers carrying data bits outward, an attention line is enabled so that the master can detect the data change and be interrupted if desired. One line tells the master that the slave has read all the incoming data. Another line tells the master that new outgoing data bits are available and have not yet been read by the master. The slave port can be used to signal the master to perform tasks using a variety of communication protocols over the slave port. 14 Rabbit 3000 Microprocessor 2.2.7 Auxiliary I/O Bus The Rabbit 3000 instruction set supports memory access and I/O access. Memory access takes place in a 1 megabyte memory space. I/O access takes place in a 64K I/O space. In a traditional microprocessor design the same address and data lines are used for both memory and I/O spaces. Sharing address and data lines in this manner often forces compromises or makes design more complicated. Generally the memory bus has more critical timing and less tolerant of additional capacitive loading imposed by sharing it with an I/O bus. With the Rabbit 3000, the designer has the option of enabling completely separate buses for I/O and memory. The auxiliary I/O bus uses many of the same pins used by the slave port, so its operation is mutually exclusive from operation of the slave port. Parallel Port A is used to provide 8 bidirectional data lines. Parallel Port B bits 2:7 provide 6 address lines, the least significant 6 lines of the 16 lines that define the full I/O space. The auxiliary bus is only active on I/O bus cycles. The address lines remain in the same state assumed at the end of the previous I/O cycle until another I/O cycle takes place. I/O chip selects as well as read and write strobes are available at various other pins so that the 64 byte space defined by the 6 address lines may be easily expanded. I/O cycles also execute in parallel on the main (memory) bus when they take place on the auxiliary bus, so additional address lines can be buffered and provided if needed. By connecting I/O devices to the auxiliary bus, the fast memory bus is relieved of the capacitive load that would otherwise slow the memory. For core modules based on the Rabbit 3000, fewer pins are required to exit the core module since the slave port and the I/O bus can share the same pins and the memory bus no longer needs to exit the module to provide I/O capability. Because the I/O bus has less activity and is slower than the memory bus, it can be run further physically without EMI and ground bounce problems. 5 V signals can appear on the I/O bus since the Rabbit 3000 inputs are 5 V tolerant. 5 V signals could easily cause problems on the main bus if non 5 V tolerant 3.3 V memories are connected. 2.2.8 Timers The Rabbit has several timer systems. The periodic interrupt is driven by the 32.768 kHz oscillator divided by 16, giving an interrupt every 488 s if enabled. This is intended to be used as a general-purpose clock interrupt. Timer A consists of ten 8-bit countdown and reload registers that can be cascaded up to two levels deep. Each countdown register can be set to divide by any number between 1 and 256. The output of six of the timers is used to provide baud clocks for the serial ports. Any of these registers can also cause interrupts and clock the timer-synchronized parallel output ports. Timer B consists of a 10-bit counter that can be read but not written. There are two 10-bit match registers and comparators. If the match register matches the counter, a pulse is output. Thus the timer can be programmed to output a pulse at a predetermined count in the future. This pulse can be used to clock the timer-synchronized parallel-port output registers as well as cause an interrupt. Timer B is convenient for creating an event at a precise time in the future under program control. Figure 2-4 illustrates the Rabbit timers. Users Manual 15 perclk perclk A1 perclk/2 Timer A System A2 A3 Serial A A4 A8 A9 A10 Input Capture PWM Quadrature Decode Serial B A5 Serial C A6 Serial D A7 Serial E Serial F Timer A1 perclk/2 perclk/8 10-bit counter compare 10 bits match reg Timer B System match preload Timer_B2 match reg match preload Timer_B1 Control Timer Synchronized outputs Figure 2-4. Rabbit Timers A and B 2.2.9 Input Capture Channels The input capture channels are used to determine the time at which an event takes place. An event is signaled by a rising or falling edge (or optionally by either edge) on one of 16 input pins that can be selected as input for either of the two channels. A 16 bit counter is used to record the time at which the event takes place. The counter is driven by the output of Timer A8 and can be set to count at a rate ranging from full clock speed to 1/256 the clock speed. Two events are recognized: a start condition and a stop condition. The start condition may be used to start counting and the stop condition to stop counting. However the counter may also run continuously or run until a stop condition is encountered. The start and stop conditions may also be used to latch the current time at the instant the condition occurs rather than actually start or stop the counter. The same pin may be used to detect the start 16 Rabbit 3000 Microprocessor and stop condition, for example a rising edge could be the start condition and a falling edge the stop condition. However, optionally, the start and stop condition can be input from separate pins. The input capture channels can be used to measure the width of fast pulses. This is done by starting the counter on the first edge of the pulse and capturing the counter value on the second edge of the pulse. In this case the maximum error in the measurement is approximately 2 periods of the clock used to count the counter. If there is sufficient time between events for an interrupt to take place the unit can be set up to capture the counter value on either start or stop conditions or both and cause an interrupt each time the count is captured. In this case the start and stop conditions lose the connection with starting or stopping the counter and simply become capture conditions that may be specified for 2 independent edge detectors. The counter can also be cleared and started under software control and then have its value captured in response to an input. If desired the capture counter can synchronized with Timer B outputs used to synchronously load parallel port output registers. This makes it possible to generate an output signal precisely synchronized with an input signal. Usually it will be desired to synchronize one of the input capture counters with the Timer B counter. The count offset can be measured by outputting a pulse at a precise time using Timer B to set the output time and capturing the same pulse. Once the phase relationship is known between the counters it is then possible to output pulses a precise time delay after an input pulse is captured, provided that the time delay is great enough for the interrupt routine to processes the capture event and set up the output pulse synchronized by Timer B. The minimum time delay needed is probably less than 10 microseconds if the software is done carefully the clock speed is reasonably high. 2.2.10 Quadrature Encoder Inputs A quadrature encoder is a common electromechanical device used to track the rotation of a shaft, or in some cases to track the motion of a linear follower. These devices are usually implemented by the use of a disk or a strip with alternate opaque and transparent bands that excite dual optical detectors. The output signals are square waves 90 degrees out of phase also called being in quadrature with each other. By having quadrature signals, the direction of rotation can be detected by noting which signal leads the other signal. The Rabbit 3000 has 2 quadrature encoder units. Each unit has 2 inputs, one being the normal input and the other the 90 degree or quadrature input. An 8 bit up down counter counts encoder steps in the forward and backward direction. The count can be extended beyond 8 bits by an interrupt that takes place each time the count overflows or underflows. The external signals are synchronized with an internal clock provided by the output of Timer A10. 2.2.11 Pulse Width Modulation Outputs The pulse width modulated output generates a train of pulses periodic on a 1024 pulse frame with a duty cycle that varies from 1/1024 to 1024/1024. There are 4 independent PWM units. The units are driven by the output of Timer A9 which may be used to vary the Users Manual 17 length of the pulses. When the duty cycle is greater then 1/1024 the pulses are spread into groups distributed 256 counts apart in the 1024 frame. The pulse width modulation outputs can be passed through a filter and used as a 10-bit D/A converter. The outputs can also be used to directly drive devices that have intrinsic filtering such as motors or solenoids. 2.2.12 Spread Spectrum Clock The main system clock, which is generated by the crystal oscillator or input from an external oscillator, can be modified by a clock spectrum spreader internal to the Rabbit 3000 chip. When the spectrum spreader is engaged, the clock is alternately speeded up and slowed down, thus spreading the spectrum of the clock harmonics in the frequency domain. This reduces EMI and improves the results of official radiated-emissions tests typically by 1520 dB at critical frequencies. The spectrum spreader has 3 modes of operation: off, normal, and strong. Slightly faster memory access time is required when the spectrum spreader is used: 23 ns for the normal setting when the clock doubler is enabled, and 69 ns for the strong setting when the clock doubler is used. The spreader slightly influences baud rates and other timings because it introduces clock jitter, but the effect is usually small enough to be negligible. 2.2.13 Separate Core and I/O Power Pins The silicon die that constitutes the Rabbit 3000 processor is divided into the core logic and the I/O ring. The I/O ring located on the 4 edges of the die holds the bonding pads and the large transistors used to create the I/O buffers that drive signals to the external world. The core section, inside the I/O ring contains the main processor and peripheral logic. The clock and clock edges in the core are very fast with large transient currents that create a lot of noise that is communicated to the outside of the package via the power pins. The I/O buffers have slower switching times and mostly operate at much lower frequencies than the core logic. The Rabbit has separate power and ground pins for the core and I/O ring. This allows the designer to feed clean power to the I/O ring filtered to be free of the noise generated by the core switching. This minimizes high frequency noise that would otherwise appear on output pins driven by buffers in the I/O ring. The result is lower EMI. 2.3 Design Standards The same functionality can often be accomplished in more than one way with the Rabbit 3000. By publishing design standards, or standard ways to accomplish common objectives, software and hardware support become easier. Refer to the Rabbit 3000 Microprocessor Designers Handbook for additional information. 2.3.1 Programming Port Rabbit Semiconductor publishes a specification for a standard programming port (see Appendix A, The Rabbit Programming Port) and provides a converter cable that may be used to connect a PC serial port to the standard programming interface. The interface is implemented using a 10-pin connector with two rows of pins on 2 mm centers. The port is connected to Rabbit Serial Port A, to the startup mode pins on the Rabbit, to the Rabbit 18 Rabbit 3000 Microprocessor reset pin, and to a programmable output pin that is used to signal the PC that attention is needed. With proper precautions in design and software, it is possible to use Serial Port A as both a programming port and as a user-defined serial port, although this will not be necessary in most cases. Rabbit Semiconductor supports the use of the standard programming port and the standard programming cable as a diagnostic and setup port to diagnosis problems or set up systems in the field. 2.3.2 Standard BIOS Rabbit Semiconductor provides a standard BIOS for the Rabbit. The BIOS is a software program that manages startup and shutdown, and provides basic services for software running on the Rabbit. 2.4 Dynamic C Support for the Rabbit Dynamic C is Z-Worlds interactive C language development system. Dynamic C runs on a PC under Windows 32-bit operating systems. Dynamic C provides a combined compiler, editor, and debugger. The usual method for debugging a target system based on the Rabbit is to implement the 10-pin programming connector that connects to the PC serial port via a standard converter cable. Dynamic C libraries contain highly perfected software to control the Rabbit. These includes drivers, utility and math routines and the debugging BIOS for Dynamic C. In addition, the internationally known real-time operating system, uC/OS-II, has been ported to the Rabbit, and is available with Dynamic C on a license-free, royalty-free basis for use in Rabbit-based products.. Users Manual 19 20 Rabbit 3000 Microprocessor 3. DETAILS ON RABBIT MICROPROCESSOR FEATURES 3.1 Processor Registers The Rabbits registers are nearly identical to those of the Z180 or the Z80. The figure below shows the register layout. The XPC and IP registers are new. The EIR register is the same as the Z80 I register, and is used to point to a table of interrupt vectors for the externally generated interrupts. The IIR register occupies the same logical position in the instruction set as the Z80 R register, but its function is to point to an interrupt vector table for internally generated interrupts. A H D B F L E C 8/16-bit registers IX IY SP PC EIR XPC A' H' D' B' F' L' E' C' IP IIR Alternate Registers S Z x x x V x C F - flag register layout S-sign, Z-zero, V-overflow, C-carry Bits marked "x" are read/write. A- 8-bit accumulator F - flags register HL- 16-bit accumulator IX, IY - Index registers/alt accums SP - stack pointer PC- program counter XPC - extension of program counter IIR - internal interrupt register EIR-external interrupt register IP - interrupt priority register Figure 3-1. Rabbit Registers Users Manual 21 The Rabbit (and the Z80/Z180) processor has two accumulatorsthe A register serves as an 8-bit accumulator for 8-bit operations such as ADD or AND. The 16-bit register HL register serves as an accumulator for 16-bit operations such as ADD HL,DE, which adds the 16bit register DE to the 16-bit accumulator HL. For many operations IX or IY can substitute for HL as accumulators. The register marked F is the flags register or status register. It holds a number of flags that provide information about the last operation performed. The flag register cannot be accessed directly except by using the POP AF and PUSH AF instructions. Normally the flags are tested by conditional jump instructions. The flags are set to mark the results of arithmetic and logic operations according to rules that are specified for each instruction. There are four unused read/write bits in the flag register that are available to the user via the PUSH AF and POP AF instructions. These bits should be used with caution since newgeneration Rabbit processors could use these bits for new purposes. The registers IX, IY and HL can also serve as index registers. They point to memory addresses from which data bits are fetched or stored. Although the Rabbit can address a megabyte or more of memory, the index registers can only directly address 64K of memory (except for certain extended addressing LDP instructions). The addressing range is expanded by means of the memory mapping hardware (see Memory Mapping on page 23) and by special instructions. For most embedded applications, 64K of data memory (as opposed to code memory) is sufficient. The Rabbit can efficiently handle a megabyte of program space. The register SP points to the stack that is used for subroutine and interrupt linkage as well as general-purpose storage. A feature of the Rabbit (and the Z80/Z180) is the alternate register set. Two special instructions swap the alternate registers with the regular registers. The instruction EX AF,AF exchanges the contents of AF with AF'. The instruction EXX exchanges HL, DE, and BC with HL', DE', and BC'. Communication between the regular and alternate register set in the original Z80 architecture was difficult because the exchange instructions provided the only means of communication between the regular and alternate register sets. The Rabbit has new instructions that greatly improve communication between the regular and alternate register set. This effectively doubles the number of registers that are easily available for the programmers use. It is not intended that the alternate register set be used to provide a separate set of registers for an interrupt routine, and Dynamic C does not support this usage because it uses both registers sets freely. The IP register is the interrupt priority register. It contains four 2-bit fields that hold a history of the processors interrupt priority. The Rabbit supports four levels of processor priority, something that exists only in a very restricted form in the Z80 or Z180. 22 Rabbit 3000 Microprocessor 3.2 Memory Mapping Although the Rabbit memory mapping scheme is fairly complex, the user rarely needs to worry about it because the details are handled by the Dynamic C development system. Except for a handful of special instructions (see Section 19.5, 16-bit Load and Store 20bit Address.), the Rabbit instructions directly address a 64K data memory space. This means that the address fields in the instructions are 16 bits long and that the registers that may be used as pointers to memory addresses (index registers (IX, IY), program counter and stack pointer (SP)) are also 16 bits long. Because Rabbit instructions use 16-bit addresses, the instructions are shorter and can execute much faster than if, for example, 32-bit addresses were used. The executable code is very compact. The Rabbit memory-mapping unit is similar to, but more powerful than, the Z180 memory-mapping unit. Figure 3-2 illustrates the relationship among the major components related to addressing memory. Processor 16 bits Memory Mapping Unit Memory Interface 20 bits Memory Chips 20 bits plus control Figure 3-2. Addressing Memory Components The memory-mapping unit receives 16-bit addresses as input and outputs 20-bit addresses. The processor (except for certain LDP instructions) sees only a 16-bit address space. That is, it sees 65536 distinctly addressable bytes that its instructions can manipulate. Three segment registers are used to map this 16-bit space into a 1-megabyte space. The 16-bit space is divided into four separate zones. Each zone, except the first or root zone, has a segment register that is added to the 16-bit address within the zone to create a 20-bit address. The segment register has eight bits and those eight bits are added to the upper four bits of the 16-bit address, creating a 20-bit address. Thus, each separate zone in the 16-bit memory becomes a window to a segment of memory in the 20-bit address space. The relative size of the four segments in the 16-bit space is controlled by the SEGSIZE register. This is an 8-bit register that contains two 4-bit registers. This controls the boundary between the first and the second segment and the boundary between the second and the third segment. The location of the two movable segment boundaries is determined by a 4-bit value that specifies the upper four bits of the address where the boundary is located. These relationships are illustrated in Figure 3-3. Users Manual 23 10000 85 80 79 XPC register STACKSEG register DATASEG register 0E000 85 93000 0D000 80 8D000 10000 XPC segment E000 stack segment D000 data segment D SEGSIZE register 7000 7 07000 79 80000 root segment 07000 0000 16-bit address space 00000 20-bit address space Figure 3-3. Example of Memory Mapping Operation The names given to the segments in the figure are evocative of the common uses for each segment. The root segment is mapped to the base of flash memory and contains the startup code as well as other code that may happen to be stored there. The data segment usage varies depending on the overall strategy for setting up memory. It may be an extension of 24 Rabbit 3000 Microprocessor the root segment or it may contain data variables. The stack segment is normally 4K long and it holds the system stack. The XPC segment is normally used to execute code that is not stored in the root segment or the data segment. Special instructions support executing code that is visible in the XPC segment. The memory interface unit receives the 20-bit addresses generated by the memory-mapping unit. The memory interface unit conditionally modifies address lines A16, A18 and A19. The other address lines of the 20-bit address are passed unconditionally. The memory interface unit provides control signals for external memory chips. These interface signals are chip selects (/CS0, /CS1, /CS2), output enables (/OE0, /OE1), and write enables (/WE0, /WE1). These signals correspond to the normal control lines found on static memory chips (chip select or /CS, output enable or /OE, and write enable or /WE). In order to generate these memory control signals, the 20-bit address space is divided into four quadrants of 256K each. A bank control register for each quadrant determines which of the chip selects and which pair of output enables, and write enables (if any) is enabled when a memory read or write to that quadrant takes place. For example, if a 512K x 8 flash memory is to be accessed in the first 512K of the 20-bit address space, then /CS0, /WE0, /OE0 could be enabled in both quadrants. Figure 3-4 shows a memory interface unit. Axxinfrom processor Axxout from memory control unit Address lines not shown are passed directly. A19in A18in A19 A18 A18, A19 invertible by quadrant A19in A19in' A18in /CS0 /CS1 /CS2 memory control lines Optional A19 inversion memory control /OE0 /WE0 Read/Write Synchronization /OE1 /WE1 Figure 3-4. Memory Interface Unit Users Manual 25 3.2.1 Extended Code Space A crucial element of the Rabbit memory mapping scheme is the ability to execute programs containing up to a megabyte of code in an efficient manner. This ability is absent in a pure 16-bit address processor, and it is poorly supported by the Z180 through its memory mapping unit. On paged processors, such as the 8086, this capability is provided by paging the code space so that the code is stored in many separate pages. On the 8086 the page size is 64K, so all the code within a given page is accessible using 16-bit addressing for jumps, calls and returns. When paging is used, a separate register (CS on the 8086) is used to determine where the active page currently resides in the total memory space. Special instructions make it possible to jump, call or return from one page to another. These special instructions are called long calls, long jumps and long returns to distinguish them from the same operations that only operate on 16-bit variables. The Rabbit also uses a paging scheme to expand the code space beyond the reach of a 16bit address. The Rabbit paging scheme uses the concept of a sliding page, which is 8K long. This is the XPC segment. The 8-bit XPC register serves as a page register to specify the part of memory where the window points. When a program is executed in the XPC segment, normal 16-bit jumps, calls and returns are used for most jumps within the window. Normal 16-bit jumps, calls and returns may also be used to access code in the other three segments in the 16-bit address space. If a transfer of control to code outside the window is required, then a long jump, long call or long return is used. These instructions modify both the program counter (PC) and the XPC register, causing the XPC window to point to a different part of memory where the target of the long jump, call or return is located. The XPC segment is always 8K long. The granularity with which the XPC segment can be positioned in memory is 4K. Because the window can be slid by one-half of its size, it is possible to compile continuously without unused gaps in memory. As the compiler generates code resident in the XPC window, the window is slid down by 4K when the code goes beyond F000. This is accomplished by a long jump that repositions the window 4K lower. This is illustrated by Figure 3-5. The compiler is not presented with a sharp boundary at the end of the page because the window does not run out of space when code passes F000 unless 4K more of code is added before the window is slid down. All code compiled for the XPC window has a 24-bit address consisting of the 8-bit XPC and the 16-bit address. Short jumps and calls can be used, provided that the source and target instructions both have the same XPC address. Generally this means that each instruction belongs to a window that is approximately 4K long and has a 16-bit address between E000+n and F000+m, where n and m are on the order of a few dozen bytes, but can be up to 4096 bytes in length. Since the window is limited to no more than 8K, the compiler is unable to compile a single expression that requires more than 8K or so of code space. This is not a practical consideration since expressions longer than a few hundred bytes are in the nature of stunts rather than practical programs. Program code can reside in the root segment or the XPC segment. Program code may also be resident in the data segment. Code can be executed in the stack segment, but this is usually restricted to special situations. Code in the root, meaning any of the segments other 26 Rabbit 3000 Microprocessor than the XPC segment, can call other code in the root using short jumps and calls. Code in the XPC segment can also call code in the root using short jumps and calls. However, a long call must be used when code in the XPC segment is called. Functions located in the root have an efficiency advantage because a long call and a long return require 32 clocks to execute, but a short call and a short return require only 20 clocks to execute. The difference is small, but significant for short subroutines. Compiler notices that code has passed F000. 10000 XPC segment E000 D000 Stack segment short calls returns Compiler inserts long jump in code. F000 Data segment E000 XPC=N PC=F000+K Root segment XPC=N+1 PC=E000+K+4 Illustration of sliding XPC window Figure 3-5. Use of XPC Segment 3.2.2 Separate I and D Space - Extending Data Memory In the normal memory model, the data space must share a 64K space with root code, the stack, and the XPC window. Typically, this leaves a potential data space of 40K or less. The XPC requires 8K, the stack requires 4K, and most systems will require at least 12K of root code. This amount of data space is sufficient for many embedded applications. One approach to getting more data space is to place data in RAM or in flash memory that is not mapped into the 64K space, and then access this data using function calls or in assembly language using the LDP instructions that can access memory using a 20-bit address. This greatly expands the data space, but the instructions are less efficient than instructions that access the 64k space using 16 bit addresses. The Rabbit 3000 supports separate I and D or Instruction and Data spaces. When separate I and D space is enabled it applies only to addresses in the root segment or data segment. Separate I and D spaces mean that instruction execution makes a distinction between Users Manual 27 fetching an instruction from memory and fetching or storing data in memory. When enabled separate I and D space make available the combined root and data segment, typically 52k bytes for root code in the I space. In the D space, the root code segment part of the D space is typically used for constant data mapped to flash memory while the data segment part of the D space is used for variable data mapped to RAM. Separate I and D space increases the amount of both root code and root data because they no longer have to share the same memory, even though they share the same addresses. 20 Bit Memory Space RAM 64k 56k 52k xpc window stack 512k Flash D Space I space Data Segment 128k Variable D Space Root Code 64k Root Segment Constant D Space Figure 3-6. Separate I and D Space Normally separate I and D space is implemented as shown in Figure 3-6. In the I space the root segment and the data segment are combined into a single root code segment. In the D space the segments are separately mapped to flash and RAM to provide storage for constant data and variable data. The hardware method to achieve separate 20 bit addresses for the D space is to invert either A16 or A19 for data accesses. The inversion may be specified separately for the root segment and the data segment. Normally A16 is inverted for data accesses in the root segment. This causes data accesses to the root segment to be moved 64k higher to a section of flash starting at 20 bit address 64k that is reserved for constant data. A19 is normally inverted for data accesses to the data segment, causing the data accesses in the data segment to be moved to an address 512k higher in the 20 bit space, an address normally mapped to RAM. The stack segment and the XPC segment do 28 Rabbit 3000 Microprocessor not have split I and D space and memory accesses to these segments do not distinguish between I and D space. The advantage of having more root code space is that root code executes faster because short calls using a 16 bit address are used to call it. This compares to long calls that have a 20 bit address for extended code. Data located in the root can be more conveniently accessed due to the comparatively limited instructions available for accessing data in the full 20 bit space and the greater overhead involve in manipulating 20 bit addresses in a processor that has 8 and 16 bit registers. 3.2.3 Using the Stack Segment for Data Storage Another approach to extending data memory is to use the stack segment to access data, placing the stack in the data segment so as to free up the stack segment. This approach works well for a software system that uses data groupings that are self-contained and are accessed one at a time rather than randomly between all the groupings. An example would be the software structures associated with a TCP/IP communication protocol connection where the same code accesses the data structures associated with each connection in a pattern determined by the traffic on each connection. The advantage of this approach is that normal C data access techniques, such as 16-bit pointers, may be used. The stack segment register has to be modified to bring the data structure into view in the stack segment before operations are performed on a particular data structure. Since the stack has to be moved into the data area, it is important that the number of stacks required be kept to a minimum when using the stack segment to view data. Of course, tasks that dont need to see the data structures can have their stack located in the stack segment. Another possibility is to have a data structure and a stack located together in the stack segment, and to use a different stack segment for different tasks, each task having its own data area and stack bound to it. These approaches are shown in Figure 3-7 below. Users Manual 29 Stack Segment used as data window Data Segment used as data window Stacks in data segment Root Segment mapped to RAM has both root code and data. Stack Segment used for stack Data (RAM) Data (RAM) Root Code (flash) Root Code (RAM) Using Stack Segment for a Data Window Using Data Segment for a Data Window (Code must be copied to RAM on startup.) Figure 3-7. Schemes for Data Memory Windows A third approach is to place the data and root code in RAM in the root segment, freeing the data segment to be a window to extended memory. This requires copying the root code to RAM at startup time. Copying root code to RAM is not necessarily that burdensome since the amount of RAM required can be quite small, say 12K for example. The XPC segment at the top of the memory can also be used as a data segment by programs that are compiled into root memory. This is handy for small programs that need to access a lot of data. 3.2.4 Practical Memory Considerations The simplest Rabbit configurations have one flash memory chip interfaced using /CS0 and one RAM memory chip interfaced using /CS1. Typical Rabbit-based systems use 256K of flash and 128 K of RAM, but smaller or larger memories may be used. Although the Rabbit can support code size approaching a megabyte, it is anticipated that the majority of applications will use less than 250K of code, equivalent to approximately 10,00020,000 C statements. This reflects both the compact nature of Rabbit code and the typical size of embedded applications. Directly accessible C variables are limited to approximately 44K of memory, split between data stored in flash and RAM. This will be more than adequate for many embed30 Rabbit 3000 Microprocessor ded applications. Some applications may require large data arrays or tables that will require additional data memory. For this purpose Dynamic C supports a type of extended data memory that allows the use of additional data memory, even extending far beyond a megabyte. Requirements for stack memory depend on the type of application and particularly whether preemptive multitasking is used. If preemptive multitasking is used, then each task requires its own stack. Since the stack has its own segment in 16-bit address space, it is easy to use available RAM memory to support a large number of stacks. When a preemptive change of context takes place, the STACKSEG register can be changed to map the stack segment to the portion of RAM memory that contains the stack associated with the new task that is to be run. Normally the stack segment is 4K, which is typically large enough to provide space for several (typically four) stacks. It is possible to enlarge the stack segment if stacks larger than 4K are needed. If only one stack is needed, then it is possible to eliminate the stack segment entirely and place the single stack in the data segment. This option is attractive for systems with only 32K of RAM that dont need multiple stacks. Users Manual 31 3.3 Instruction Set Outline Load Immediate Data to a Register on page 33 Load or Store Data from or to a Constant Address on page 33 Load or Store Data Using an Index Register on page 34 Register-to-Register Move on page 35 Register Exchanges on page 35 Push and Pop Instructions on page 36 16-bit Arithmetic and Logical Ops on page 36 Input/Output Instructions on page 39these include a fix for a bug that manifests itself if an I/O instruction (prefix IOI or IOE) is followed by one of 12 single-byte op codes that use HL as an index register. In the discussion that follows, we give a few example instructions in each general category and contrast the Z80/ Z180 with the Rabbit. For a detailed description of every instruction, see Chapter 19, Rabbit Instructions The Rabbit executes instructions in fewer clocks then the Z80 or Z180. The Z180 usually requires a minimum of four clocks for 1-byte opcodes or three clocks for each byte for multi-byte op codes. In addition, three clocks are required for each data byte read or written. Many instructions in the Z180 require a substantial number of additional clocks. The Rabbit usually requires two clocks for each byte of the op code and for each data byte read. Three clocks are needed for each data byte written. One additional clock is required if a memory address needs to be computed or an index register is used for addressing. Only a few instructions dont follow this pattern. An example is mul, a 16 x 16 bit signed twos complement multiply. mul is a 1-byte op code, but requires 12 clocks to execute. Compared to the Z180, not only does the Rabbit require fewer clocks, but in a typical situation it has a higher clock speed and its instructions are more powerful. The most important instruction set improvements in the Rabbit over the Z180 are in the following areas. Fetching and storing data, especially 16-bit words, relative to the stack pointer or the index registers IX, IY, and HL. 16-bit arithmetic and logical operations, including 16-bit ands, ors, shifts and 16-bit multiply. Communication between the regular and alternate registers and between the index registers and the regular registers is greatly facilitated by new instructions. In the Z180 the alternate register set is difficult to use, while in the Rabbit it is well integrated with the regular register set. Long calls, long returns and long jumps facilitate the use of 1M of code space. This removes the need in the Z180 to utilize inefficient memory banking schemes for larger programs that exceed 64K of code. 32 Rabbit 3000 Microprocessor Input/output instructions are now accomplished by normal memory access instructions prefixed by an op code byte to indicate access to an I/O space. There are two I/O spaces, internal peripherals and external I/O devices. Some Z80 and Z180 instructions have been deleted and are not supported by the Rabbit (see Chapter 20, Differences Rabbit vs. Z80/Z180 Instructions). Most of the deleted instructions are obsolete or are little-used instructions that can be emulated by several Rabbit instructions. It was necessary to remove some instructions to free up 1-byte op codes needed to implement new instructions efficiently. The instructions were not reimplemented as 2-byte op codes so as not to waste on-chip resources on unimportant instructions. Except for the instruction EX (SP),HL, the original Z180 binary encoding of op codes is retained for all Z180 instructions that are retained. 3.3.1 Load Immediate Data to a Register A constant that follows the op code in the instruction stream can generally be loaded to any register, except PC, IP, and F. (Load to the PC is a jump instruction.) This includes the alternate registers on the Rabbit, but not on the Z180. Some example instructions appear below. LD LD LD LD LD LD A,3 HL,456 BC',3567 H',0x4A IX,1234 C,54 ; not possible on Z180 ; not possible on Z180 Byte loads require four clocks, word loads require six clocks. Loads to IX, IY or the alternate registers generally require two extra clocks because the op code has a 1-byte prefix. 3.3.2 Load or Store Data from or to a Constant Address LD LD LD LD LD LD A,(mn) A',(mn) (mn),A HL,(mn) HL',(mn) (mn),HL ; loads 8 bits from address mn ; not possible on Z180 ; load 16 bits from the address specified by mn ; to alternate register, not possible Z180 Similar 16-bit loads and stores exist for DE, BC, SP, IX and IY. It is possible to load data to the alternate registers, but it is not possible to store the data in the alternate register directly to memory. LD A,(mn) ; allowed ** LD (mn),D ; **** not a legal instruction! ** LD (mn),DE ; **** not a legal instruction! Users Manual 33 3.3.3 Load or Store Data Using an Index Register An index register is a 16-bit register, usually IX, IY, SP or HL, that is used for the address of a byte or word to be fetched from or stored to memory. Sometimes an 8-bit offset is added to the address either as a signed or unsigned number. The 8-bit offset is a byte in the instruction word. BC and DE can serve as index registers only for the special cases below. LD LD LD LD LD LD A,(BC) A,(BC) (BC),A A,(DE) A,(DE) (DE),A Other 8-bit loads and stores are the following. LD r,(HL) LD r,(HL) LD (HL),r ** LD LD LD LD ; r is any of 7 registers A, B, C, D, E, H, L ; same but alternate register destination ; r is any of the 7 registers above ;or an immediate data byte LD (HL),r ;**** not a legal instruction! r,(IX+d) ; r is any of 7 registers, d is -128 to +127 offset r,(IX+d) ; same but alternate destination (IX+d),r ; r is any of 7 registers or an immediate data byte (IY+d),r ; IX or IY can have offset d The following are 16-bit indexed loads and stores. None of these instructions exists on the Z180 or Z80. The only source for a store is HL. The only destination for a load is HL or HL'. LD HL,(SP+d) LD (SP+d),HL LD HL,(HL+d) ; ; ; ; ; ; d is an offset from 0 to 255. 16-bits are fetched to HL or HL corresponding store d is an offset from -128 to +127, uses original HL value for addressing l=(HL+d), h=(HL+d+1) LD HL,(HL+d) LD (HL+d),HL LD (IX+d),HL LD HL,(IX+d) LD HL,(IX+d) LD (IY+d),HL LD HL,(IY+d) LD HL,(IY+d) ; store HL at address pointed to ; by IX plus -128 to +127 offset ; store HL at address pointed to ; by IY plus -128 to +127 offset 34 Rabbit 3000 Microprocessor 3.3.4 Register-to-Register Move Any of the 8-bit registers, A, B, C, D, E, H, and L, can be moved to any other 8-bit register, for example: LD A,c LD d,b LD e,l The alternate 8-bit registers can be a destination, for example: LD a,c LD d,b These instructions are unique to the Rabbit and require 2 bytes and four clocks because of the required prefix byte. Instructions such as LD A,d or LD d,e are not allowed. Several 16-bit register-to-register move instructions are available. Except as noted, these instructions all require 2 bytes and four clocks. The instructions are listed below. LD LD LD LD LD LD LD LD LD dd,BC dd,DE IX,HL IY,HL HL,IY HL,IX SP,HL SP,IX SP,IY ; where dd is any of HL, DE, BC (2 bytes, 4 clocks) ; 1-byte, 2 clocks Other 16-bit register moves can be constructed by using 2-byte moves. 3.3.5 Register Exchanges Exchange instructions are very powerful because two (or more) moves are accomplished with one instruction. The following register exchange instructions are implemented. EX af,af EXX EX DE,HL ; exchange af with af ; exchange HL, DE, BC with HL, DE, BC ; exchange DE and HL The following instructions are unique to the Rabbit. EX DE,HL EX DE, HL EX DE, HL ; 1 byte, 2 clocks ; 2 bytes, 4 clocks ; 2 bytes, 4 clocks The following special instructions (Rabbit and Z180/Z80) exchange the 16-bit word on the top of the stack with the HL register. These three instructions are each 2 bytes and 15 clocks. EX (SP),HL EX (SP),IX EX (SP),IY Users Manual 35 3.3.6 Push and Pop Instructions There are instructions to push and pop the 16-bit registers AF, HL, DC, BC, IX, and IY. The registers AF', HL', DE', and BC' can be popped. Popping the alternate registers is exclusive to the Rabbit, and is not allowed on the Z80 / Z180. Examples POP HL PUSH BC PUSH IX PUSH af POP DE POP DE POP HL 3.3.7 16-bit Arithmetic and Logical Ops The HL register is the primary 16-bit accumulator. IX and IY can serve as alternate accumulators for many 16-bit operations. The Z180/Z80 has a weak set of 16-bit operations, and as a practical matter the programmer has to resort to combinations of 8-bit operations in order to perform many 16-bit operations. The Rabbit has many new op codes for 16-bit operations, removing some of this weakness. The basic Z80/Z180 16-bit arithmetic instructions are ADD ADC SBC INC HL,ww HL,ww HL,ww ww ; ; ; ; where ww is HL, DE, BC, SP ADD and ADD carry sub and sub carry increment the register (without affecting flags) In the above op codes, IX or IY can be substituted for HL. The ADD and ADC instructions can be used to left-shift HL with the carry. An alternate destination prefix (ALTD) may be used on the above instructions. This causes the result and its flags to be stored in the corresponding alternate register. If the ALTD flag is used when IX or IY is the destination register, then only the flags are stored in the alternate flag register. The following new instructions have been added for the Rabbit. ;Shifts RR HL ; ; ; ; ; ; ; rotate HL right with carry, 1 byte, 2 clocks note use ADC HL,HL for left rotate, or add HL,HL if no carry in is needed. 1 byte, 2 clocks rotate DE left with carry, 1-byte, 2 clocks rotate IX right with carry, 2 bytes, 4 clocks rotate IY right with carry RR RL RR RR DE DE IX IY ;Logical Operations AND HL,DE ; 1 byte, 2 clocks AND IX,DE ; 2 bytes, 4 clocks AND IY,DE OR HL,DE ; 1 byte, 2 clocks OR IX,DE ; 2 bytes, 4 clocks OR IY,DE 36 Rabbit 3000 Microprocessor The BOOL instruction is a special instruction designed to help test the HL register. BOOL sets HL to the value 1 if HL is non zero, otherwise, if HL is zero its value is not changed. The flags are set according to the result. BOOL can also operate on IX and IY. BOOL HL BOOL IX BOOL IY ALTD BOOL HL ALTD BOOL IY ; set HL to 1 if non- zero, set flags to match HL ; set HL an f according to HL ; modify IY and set f with flags of result The SBC instruction can be used in conjunction with the BOOL instruction for performing comparisions. The SBC instruction subtracts one register from another and also subtracts the carry bit. The carry out is inverted compared to the carry that would be expected if the number subtracted was negated and added. The following examples illustrate the use of the SBC and BOOL instructions. ; Test if HL>=DE - HL and DE unsigned numbers 0-65535 OR a ; clear carry SBC HL,DE ; if C==0 then HL>=DE else if C==1 then HL<DE ; ; SBC HL,HL ; BOOL HL ; ; ; SBC HL,HL ; INC HL ; ; convert the carry bit into a boolean variable in HL sets HL==0 if C==0, sets HL==0ffffh if C==1 HL==1 if C was set, otherwise HL==0 convert not carry bit into boolean variable in HL HL==0 if C==0 else HL==ffff if C=1 HL==1 if C==0 else HL==0 if C==1 note carry flag set, but zero / sign flags reversed In order to compare signed numbers using the SBC instruction, the programmer can map the numbers into an equivalent set of unsigned numbers by inverting the sign bit of each number before performing the comparison. This maps the most negative number 0x08000 to the smallest unsigned number 0x0000, and the most positive signed number 0x07FFF to the largest unsigned number 0x0FFFF. Once the numbers have been converted, the comparision can be done as for unsigned numbers. This procedure is faster than using a jump tree that requires testing the sign and overflow bits. ; example - test for HL>=DE where HL and DE are signed numbers ; invert sign bits on both ADD HL,HL ; shift left CCF ; invert carry RR HL ; rotate right RL DE CCF RR DE ; invert DE sign SBC HL,DE ; no carry if HL>=DE ; generate boolean variable true if HL>=DE SBC HL,HL ; zero if no carry else -1 INC HL ; 1 if no carry, else zero BOOL ; use this instruction to set flags if needed Users Manual 37 The SBC instruction can also be used to perform a sign extension. ; extend sign of l to HL LD A,l rla SBC A,a LD h,a ; sign to carry ; a is all 1s if sign negative ; sign extended The multiply instruction performs a signed multiply that generates a 32-bit signed result. MUL ; signed multiply of BC and DE, ; result in HL:BC - 1 byte, 12 clocks If a 16-bit by 16-bit multiply with a 16-bit result is performed, then only the low part of the 32-bit result (BC) is used. This (counter intuitively) is the correct answer whether the terms are signed or unsigned integers. The following method can be used to perform a 16 x 16 bit multiply of two unsigned integers and get an unsigned 32-bit result. This uses the fact that if a negative number is multiplied the sign causes the other multiplier to be subtracted from the product. The method shown below adds double the number subtracted so that the effect is reversed and the sign bit is treated as a positive bit that causes an addition. LD BC,n1 LD HL,BC LD DE,n2 LD A,b MUL OR a JR p,x1 ADD HL,DE x1: RL DE JR nc,x2 EX DE,HL ADD HL,DE x2: ; final unsigned 32 bit result in HL:BC ; save BC in HL ; ; ; ; ; save sign of BC form product in HL:BC test sign of BC multiplier if plus continue adjust for negative sign in BC ; test sign of DE ; if not negative ; subtract other multiplier from HL This method can be modified to multiply a signed number by an unsigned number. In that case only the unsigned number has to be tested to see if the sign is on, and in that case the signed number is added to the upper part of the product. The multiply instruction can also be used to perform left or right shifts. A left shift of n positions can be accomplished by multiplying by the unsigned number 2^^n. This works for n # 15, and it doesnt matter if the numbers are signed or unsigned. In order to do a right shift by n (0 < n < 16), the number should be multiplied by the unsigned number 2^^(16 n), and the upper part of the product taken. If the number is signed, then a signed by unsigned multiply must be performed. If the number is unsigned or is to be treated as unsigned for a logical right shift, then an unsigned by unsigned multiply must be performed. The problem can be simplified by excluding the case where the multiplier is 2^^15. 38 Rabbit 3000 Microprocessor 3.3.8 Input/Output Instructions The Rabbit uses an entirely different scheme for accessing input/output devices. Any memory access instruction may be prefixed by one of two prefixes, one for internal I/O space and one for external I/O space. When so prefixed, the memory instruction is turned into an I/O instruction that accesses that I/O space at the I/O address specified by the 16bit memory address used. For example IOI LD A,(0x85) LD IY,0x4000 IOE LD HL,(IY+5) ; loads A register with contents ; of internal I/O register at location 0x85. ; get word from external I/O location 0x4005 By using the prefix approach, all the 16-bit memory access instructions are available for reading and writing I/O locations. The memory mapping is bypassed when I/O operations are executed. I/O writes to the internal I/O registers require only two clocks, rather than the minimum of three clocks required for writes to memory or external I/O devices. Users Manual 39 3.4 How to Do It in Assembly LanguageTips and Tricks 3.4.1 Zero HL in 4 Clocks BOOL HL RR HL ; 2 clocks, clears carry, HL is 1 or 0 ; 2 clocks, 4 total - get rid of possible 1 This sequence requires four clocks compared to six clocks for LD HL,0. 3.4.2 Exchanges Not Directly Implemented HL<->HL' - eight clocks EX DE,HL EX DE,HL EX DE,HL ; 2 clocks ; 4 clocks ; 2 clocks, 8 total DE<->DE' - six clocks EX DE,HL EX DE,HL EX DE,HL ; 2 clocks ; 2 clocks ; 2 clocks, 6 total BC<->BC' - 12 clocks EX DE,HL EX DE,HL EX DE,HL EXX EX DE,HL ; ; ; ; ; 2 clocks 4 2 2 2 Move between IX, IY and DE, DE' IX/IY->DE / DE->IX/IY ;IX, IX --> DE EX DE,HL LD HL,IX/IY / LD IX/IY,HL EX DE,HL ; 8 clocks total ; DE --> IX/ IY EX DE,HL LD IX/IY,HL EX DE,HL ; 8 clocks total 3.4.3 Manipulation of Boolean Variables Logical operations involving HL when HL is a logical variable with a value of 1 or 0 this is important for the C language where the least bit of a 16-bit integer is used to represent a logical result Logical not operatorinvert bit 0 of HL in four clocks (also works for IX, IY in eight clocks) DEC HL BOOL HL ; 1 goes to zero, zero goes to -1 ; -1 to 1, zero to zero. 4 clocks total Logical xor operatorxor HL,DE when HL/DE are 1 or 0. ADD HL,DE RES 1,l ; 6 clocks total, clear bit 1 result of if 1+1=2 40 Rabbit 3000 Microprocessor 3.4.4 Comparisons of Integers Unsigned integers may be compared by testing the zero and carry flags after a subtract operation. The zero flag is set if the numbers are equal. With the SBC instruction the carry cleared is set if the number subtracted is less than or equal to the number it is subtracted from. 8-bit unsigned integers span the range 0255. 16-bit unsigned integers span the range 065535. OR a SBC HL,DE A>=B A<B A==B A>B A<=B ; clear carry ; HL=A and DE=B !C C Z !C & !Z C v Z If A is in HL and B is in DE, these operations can be performed as follows assuming that the object is to set HL to 1 or 0 depending on whether the compare is true or false. ; compute HL<DE ; unsigned integers ; EX DE,HL ; uncomment for DE<HL OR a ; clear carry SBC HL,DE ; C set if HL<DE SBC HL,HL ; HL-HL-C -- -1 if carry set BOOL HL ; set to 1 if carry, else zero ; else result == 0 ;unsigned integers ; compute HL>=DE or DE>=HL - check for !C ; EX DE,HL ; uncomment for DE<=HL OR a ; clear carry SBC HL,DE ; !C if HL>=DE SBC HL,HL ; HL-HL-C - zero if no carry, -1 if C INC HL ; 14 / 16 clocks total -if C after first SBC result 1, ; else 0 ; 0 if C , 1 if !C ; : compute HL==DE OR a ; clear carry SBC HL,DE ; zero is equal BOOL HL ; force to zero, 1 DEC HL ; invert logic BOOL HL ; 12 clocks total -logical not, 1 for inputs equal ; Users Manual 41 Some simplifications are possible if one of the unsigned numbers being compared is a constant. Note that the carry has a reverse sense from SBC. In the following examples, the pseudo-code in the form LD DE,(65535-B) does not indicate a load of DE with the address pointed to by 65535-B, but simply indicates the difference between 65535 and the 16-bit unsigned integer B. ;test for HL>B B is constant LD DE,(65535-B) ADD HL,DE ; carry set if HL>B SBC HL,HL ; HL-HL-C - result -1 if carry set, else zero BOOL HL ; 14 total clocks - true if HL>B ; HL>=B B is constant not zero LD DE,(65536-B) ADD HL,DE SBC HL,HL BOOL HL ; 14 clocks ; HL>=B LD HL,1 and B is zero ; 6 clocks ; HL<B B is a constant, not zero (if B==0 always false) LD DE,(65536-B) ADD HL,DE ; not carry if HL<B SBC HL,HL ; -1 if carry, else 0 INC HL ; 14 clocks --0 if carry, else 1 if no carry ; ; HL <= B B is constant not zero LD DE,(65535-B) ADD HL,DE ; ~C if HL<=B CCF ; C if true SBC HL,HL ; if C -1 else 0 INC HL ; 16 clocks -- 1 if true, else 0 ; ; HL <= B B is zero - true if HL==0 BOOL HL ; result in HL ; ; HL==B and B is a constant not zero LD DE,(65536-B) ADD HL,DE ; zero if equal BOOL HL INC HL RES 1,l ; 16 clocks ; HL==B and B==0 BOOL HL INC HL RES 1,l ; 8 clocks For signed integers the conventional method to look at the zero flag, the minus flag and the overflow flag. Signed 8-bit integers span the range 128 to +127 (0x80 to 0x7F). Signed 16-bit integers span the range 32768 to + 32767 (0x8000 to 0x7FFF). The sign and zero flag tell which is the larger number after the subtraction unless the overflow is set, in which case the sign flag needs to be inverted in the logic, that is, it is wrong. 42 Rabbit 3000 Microprocessor A>B A<B A==B A>=B A<=B (!S & !V & !Z) v (S & V) (S & !V) v (!S & V & !Z) Another method of doing signed compare is to first map the signed integers onto unsigned integers by inverting bit 15. This is shown in Figure 3-8. Once the mapping has been performed by inverting bit 15 on both numbers, the comparisions can be done as if the numbers were unsigned integers. This avoids having to construct a jump tree to test the overflow and sign flags. An example is shown below. ; test HL>5 for signed integers LD DE,65535-(5+0x08000) ; 5 mapped to unsigned integers LD BC,0x08000 ADD HL,BC ; invert high bit ADD HL,DE ; 16 clocks to here ; carry now set if HL>5 - opportunity to jump on carry SUBC HL,HL ; HL-HL-C ; if C on result is -1, else zero BOOL HL ; 22 clocks total - true if HL>5 else false 0111... 1111... 000... 111... 100... 100... 011... 000... Figure 3-8. Mapping Signed Integers to Unsigned Integers by Inverting Bit 15 3.4.5 Atomic Moves from Memory to I/O Space To avoid disabling interrupts while copying a shadow register to its target register, it is desirable to have an atomic move from memory to I/O space. This can be done using LDD or LDI instructions. LD HL,sh_PDDDR LD DE,PDDDR SET 5,(HL) IOI ldd ; ; ; ; ; point to shadow register set DE to point to I/O reg set bit 5 of shadow register use ldd instruction for atomic transfer (io DE)<-(HL) HL--, DE-- When the LDD instruction is prefixed with an I/O prefix, the destination becomes the I/O address specified by DE. The decrementing of HL and DE is a side effect. If the repeating instructions LDIR and LDDR are used, interrupts can take place between successive iterations. Word stores to I/O space can be used to set two I/O registers at adjacent addresses with a single noninterruptable instruction. Users Manual 43 3.5 Interrupt Structure When an interrupt occurs on the Rabbit, the return address is pushed on the stack, and control is transferred to the address of the interrupt service routine. The address of the interrupt service routine has two parts: the upper byte of the address comes from a special register and the lower byte is fixed by hardware for each interrupt, as shown in Table 6-1. There are separate registers for internal interrupts (IIR) and external interrupts (EIR) to specify the high byte of the interrupt service routine address. These registers are accessed by special instructions. LD LD LD LD A,IIR IIR,A A,EIR EIR,A Interrupts are initiated by hardware devices or by certain 1-byte instructions called reset instructions. RST RST RST RST RST 10 18 20 28 38 The RST instructions are similar to those on the Z80 and Z180, but certain ones have been removed from the instruction set (00, 08, 30). The RST interrupts are not inhibited regardless of the processor priority. The user is advised to exercise caution when using these instructions as they are mostly reserved for the use of Dynamic C for debugging. Unlike the Z80 or Z180, the IIR register contributes the upper byte of the service routine address for RST interrupts. Since interrupt routines do not affect the XPC, interrupt routines must be located in the root code space. However, they can jump to the extended code space after saving the XPC on the stack. 3.5.1 Interrupt Priority The Z80 and Z180 have two levels of interrupt priority: maskable and nonmaskable. The nonmaskable interrupt cannot be disabled and has a fixed interrupt service routine address of 0x66. The Rabbit, in contrast, has three levels of interrupt priority and four priority levels at which the processor can operate. If an interrupt is requested, and the priority of the interrupt is higher than that of the processor, the interrupt will take place after the execution of the current instruction is complete (except for privileged instructions) Multiple interrupt priorities have been established to make it feasible for the embedded systems programmer to have extremely fast interrupts available. Interrupt latency refers to the time required for an interrupt to take place after it has been requested. Generally, interrupts of the same priority are disabled when an interrupt service routine is entered. Sometimes interrupts must stay disabled until the interrupt service routine is completed, other times the interrupts can be re-enabled once the interrupt service routine has at least disabled its own cause of interrupt. In any case, if several interrupt routines are operating at 44 Rabbit 3000 Microprocessor the same priority, this introduces interrupt latency while the next routine is waiting for the previous routine to allow more interrupts to take place. If a number of devices have interrupt service routines, and all interrupts are of the same priority, then pending interrupts can not take place until at least the interrupt service routine in progress is finished, or at least until it changes the interrupt priority. As a rule of thumb, Z-World usually suggests that 100 s be allowed for interrupt latency on Z180- or Rabbit-based controllers. This can result if, for example, there are five active interrupt routines, and each turns off the interrupts for at most 20 s. The intention in the Rabbit is that most interrupting devices will use priority 1 level interrupts. Devices that need extremely fast response to interrupts will use priority level 2 or 3 interrupts. Since code that runs at priority level 0 or 1 never disables level 2 and level 3 interrupts, these interrupts will take place within about 20 clocks, the length of the longest instruction or longest sensible sequence of privileged instructions followed by an unprivileged instruction. It is important that the user be careful not to overdisable interrupts in critical code sections. The processor priority should not be raised above level 1 except in carefully considered situations. The effect of the processor priority on interrupts is shown in Table 3-1. The priority of the interrupt is usually established by bits in an I/O control register associated with the hardware that creates the interrupt. The 8-bit interrupt register (IP) holds the processor priority in the least significant 2 bits. When an interrupt takes place, the IP register is shifted left 2 positions and the lower 2 bits are set to equal the priority of the interrupt that just took place. This means that an interrupt service request (ISR) can only be interrupted by an interrupt of higher priority (unless the priority is explicitly set lower by the programmer). The IP register serves as a 4-word stack of 2-bit words to save and restore interrupt priorities. It can be shifted right, restoring the previous priority by a special instruction (IPRES). Since only the current processor priority and 3 previous priorities can be saved in the interrupt register, instructions are also provided to PUSH and POP IP using the regular stack. A new priority can be pushed into the IP register with special instructions (IPSET 0, IPSET 1, IPSET 2, IPSET 3). Table 3-1. Effect of Processor Priorities on Interrupts Processor Priority 0 1 2 3 Effect on Interrupts All interrupts, priority 1,2 and 3 take place after execution of current non privileged instruction. Only interrupts of priority 2 and 3 take place. Only interrupts of priority 3 take place. All interrupt are suppressed (except RST instruction). Users Manual 45 3.5.2 Multiple External Interrupting Devices The Rabbit 3000 has two distinct external interrupt request lines. If there are more than two external causes of interrupts, then these lines must be shared between multiple devices. The interrupt line is edge-sensitive, meaning that it requests an interrupt only when a rising or falling edge, whichever is specified in the setup registers, takes place. The state of the interrupt line(s) can always be read by reading Parallel Port E since they share pins with Parallel Port E. If several lines are to share interrupts with the same port, the individual interrupt requests would normally be ored together so that any device can cause an interrupt. If several devices are requesting an interrupt at the same time, only one interrupt results because there will be only one transition of the interrupt request line. To resolve the situation and make sure that the separate interrupt routines for the different devices are called, a good method is to have a interrupt dispatcher in software that is aided by providing separate attention request lines for each device. The attention request lines are basically the interrupt request lines for the separate devices before they are ored together. The interrupt dispatcher calls the interrupt routines for all devices requesting interrupts in priority order so that all interrupts are serviced. 3.5.3 Privileged Instructions, Critical Sections and Semaphores Normally an interrupt happens at the end of the instruction currently executing. However, if the instruction executing is privileged, the interrupt cannot take place at the end of the instruction and is deferred until a non privileged instruction is executed, usually the next instruction. Privileged instructions are provided as a handy way of making a certain operation atomic because there would be a software problem if an interrupt took place after the instruction. Turning off the interrupts explicitly may be too time consuming or not possible because the purpose of the privileged instruction is to manipulate the interrupt controls. For additional information on privileged instructions, see Section 19.19, Privileged Instructions. The privileged instructions to load the stack are listed below. LD SP,HL LD SP,IY LD SP,IX The following instructions to load SP are privileged because they are frequently followed by an instruction to change the stack segment register. If an interrupt occurs between these two instructions and the following instruction, the stack will be ill-defined. LD SP,HL IOI LD sseg,a 46 Rabbit 3000 Microprocessor The privileged instructions to manipulate the IP register are listed below. IPSET 0 IPSET 1 IPSET 2 IPSET 3 IPRES RETI POP IP ; shift IP left and set priority 00 in bits 1,0 ; rotate IP right 2 bits, restoring previous priority ; pops IP from stack and then pops return address ; pop IP register from stack 3.5.4 Critical Sections Certain library routines may need to disable interrupts during a critical section of code. Generally these routines are only legal to call if the processor priority is either 0 or 1. A priority higher than this implies custom hand-coded assembly routines that do not call general-purpose libraries. The following code can be used to disable priority 1 interrupts. IPSET 1 ; save previous priority and set priority to 1 ....critical section... IPRES ; restore previous priority This code is safe if it is known that the code in the critical section does not have an embedded critical section. If this code is nested, there is the danger of overflowing the IP register. A different version that can be nested is the following. PUSH IP IPSET 1 ; save previous priority and set priority to 1 ....critical section... POP IP ; restore previous priority The following instructions are also privileged. LD A,xpc LD xpc,a BIT B,(HL) 3.5.5 Semaphores Using Bit B,(HL) The bit B,(HL) instruction is privileged to allow the construction of a semaphore by the following code. BIT B,(HL) ; test a bit in the byte at (HL) SET B,(HL) ; make sure bit set, does not affect flag ; if zero flag set the semaphore belongs to us; ; otherwise someone else has it A semaphore is used to gain control of a resource that can only belong to one task or program at a time. This is done by testing a bit to see if it is on, in which case someone else is using the resource, otherwise setting the bit to indicate ownership of the resource. No interrupt can be allowed between the test of the bit and the setting of the bit as this might allow two different program to both think they own the resource. Users Manual 47 3.5.6 Computed Long Calls and Jumps The instruction to set the XPC is privileged to so that a computed long call or jump can be made. This would be done by the following sequence. LD xpc,a JP (HL) In this case, A has the new XPC, and HL has the new PC. This code should normally be executed in the root segment so as not to pull the memory out from under the JP (HL) instruction. A call to a computed address can be performed by the following code. ; A=xpc, IY=address ; LD A,newxpc LD IY,newaddress LCALL DOCALL ; call utility routine in the root ; ; The DOCALL routine DOCALL: LD xpc,a ; SET xpc JP (IY) ; go to the routine 48 Rabbit 3000 Microprocessor 4. RABBIT CAPABILITIES This chapter describes the various capabilities of the Rabbit that may not be obvious from the technical description. 4.1 Precisely Timed Output Pulses The Rabbit can output precise pulses under software control. The effect of interrupt latency is avoided because the interrupt always prepares a future pulse edge that is clocked into the output registers on the next clock. This is shown in Figure 4-1. Timer Output A B C Parallel Port Output Latency Parallel Port Output Interrupt routine sets Timer Output Setup Register Figure 4-1. Timed Output Pulses The timer output in Figure 4-1 is periodic. As long as the interrupt routine can be completed during one timer period, an arbitrary pattern of synchronous pulses can be output from the parallel port. The interrupt latency depends on the priority of the interrupt and the amount of time that other interrupt routines of the same or higher priority inhibit interrupts. The first instruction of the interrupt routine will start executing within 30 clocks of the interrupt request for the highest priority interrupt routine. This includes 19 clocks for the longest instruction to complete execution and 10 clocks for the interrupt to execute. Pushing registers requires 1012 clocks per 16-bit register. Popping registers requires 79 clocks. Return from interrupt requires 7 clocks. If three registers are saved and restored, and 20 instructions averaging 5 clocks are executed, an entire interrupt routine will require about 200 clocks, or 10 s with a 20 MHz clock. Given this timing, the following capabilities become possible. Users Manual 49 Pulse width modulated outputsThe minimum pulse width is 10 s. If the repetition rate is 10 ms, then a new pulse with 1000 different widths can be generated at the rate of 100 times per second. Asynchronous communications serial outputAsynchronous output data can be generated with a new pulse every 10 s. This corresponds to a baud rate of 100,000 bps. Asynchronous communications serial inputTo capture asynchronous serial input, the input must be polled faster than the baud rate, a minimum of three times faster, with five times being better. If five times polling is used, then asynchronous input at 20,000 bps could be received. Generating pulses with precise timing relationshipsThe relationship between two events can be controlled to within 10 s to 20 s. Using a timer to generate a periodic clock allows events to be controlled to a precision of approximately 10 s. However, if Timer B is used to control the output registers, a precision approximately 100 times better can be achieved. This is because Timer B has a match register that can be programmed to generate a pulse at a specified future time. The match register has two cascaded registers, the match register and the next match register. The match register is loaded with the contents of the next match register when a pulse is generated. This allows events to be very close together, one count of Timer B. Timer B can be clocked by sysclk/2 divided by a number in the range of 1256. Timer B can count as fast as 10 MHz with a 20 MHz system clock, allowing events to be separated by as little as 100 ns. Timer B and the match registers have 10 bits. Using Timer B, output pulses can be positioned to an accuracy of clk/2. Timer B can also be used to capture the time at which an external event takes place in conjunction with the external interrupt line. The interrupt line can be programmed to interrupt on either rising, falling or both edges. To capture the time of the edge, the interrupt routine can read the Timer B counter. The execution time of the interrupt routine up to the point where the timer is read can be subtracted from the timer value. If no other interrupt is of the same or higher priority, then the uncertainty in the position of the edge is reduced to the variable time of the interrupt latency, or about one-half the execution time of the longest instruction. This uncertainty is approximately 10 clocks, or 0.5 s for a 20 MHz clock. This enables pulse width measurements for pulses of any length, with a precision of about 1 s. If multiple pulses need to be measured simultaneously, then the precision will be reduced, but this reduction can be minimized by careful programming. 4.1.1 Pulse Width Modulation to Reduce Relay Power Typically relays need far less current to hold them closed than is needed to initially close them. For example, if the driver is switched to a 75% duty cycle using pulse width modulation after the initial period when the relay armature is picked, the holding current will be approximately 75% of the full duty-cycle current and the power consumption will be about 56% as great. 50 Rabbit 2000 Microprocessor 4.2 Open-Drain Outputs Used for Key Scan The Parallel Port D outputs can be individually programmed to be open drain. This is useful for scanning a switch matrix, as shown in Figure 4-2. A row is driven low, then the columns are scanned for a low input line, which indicates a key is closed. This is repeated for each row. The advantage of using open-drain outputs is that if two keys in the same column are depressed, there will not be a fight between a driver driving the line high and another driver driving it low. + o.d. + o.d. + + + + + Figure 4-2. Using Open-Drain Outputs for Key Scan Users Manual 51 4.3 Cold Boot Most microprocessors start executing at a fixed address, often address zero, after a reset or power-on condition. The Rabbit has two mode pins (SMODE0, SMODE1see Figure 51). The logic state of these two pins determines the startup procedure after a reset. If both pins are grounded, then the Rabbit starts executing instructions at address zero. On reset, address zero is defined to be the start of the memory connected to the memory control lines /CS0, and /OE0. However, three other startup modes are available. These alternate methods all involve accepting a data stream via a communications port that is used to store a boot program in a RAM memory, which in turn can be used to start any further secondary boot process, such as downloading a program over the same communications port. (For a detailed description, see Section 7.11, Bootstrap Operation.) Three communication channels may be used for the bootstrap, either Serial Port A in asynchronous mode at 2400 bps, Serial Port A in synchronous mode with an external clock, or the (parallel) slave port. The cold-boot protocol accepts groups of three bytes that define an address and a data byte. Each triplet causes a write of the data byte to either memory or to internal I/O space. The high bit of the address is set to specify the I/O space, and thus writes are limited to the first 32K of either space. The cold boot is terminated by a store to an address in I/O space, which causes execution to begin at address zero. Since any memory chip can be remapped to address zero by storing in the I/O space, RAM can be temporarily be mapped to zero to avoid having to deal with the more complicated write protocol of flash memory, which is the usual default memory located at address zero. The following are the advantages of the cold-boot capability. Flash memory can be soldered to the microprocessor board and programmed via a serial port or a parallel port. This avoids having to socket the part or program it with a BIOS or boot program before soldering. Complete reprogramming of the flash memory can be accomplished in the field. This is particularly useful during software development when the development platform can perform a complete reload of software regardless of the state of the existing software in the processor. The standard programming cable for Dynamic C allows the development platform to reset and cold boot the target, a Rabbit-based microprocessor board. If the Rabbit is used as a slave processor, the master processor can cold boot it over via the slave port. This means the slave can operate without any nonvolatile memory. Only RAM is required. 52 Rabbit 2000 Microprocessor 4.4 The Slave Port The slave port allows a Rabbit to act as a slave to another processor, which can also be a Rabbit. The slave has to have only a processor chip, a RAM chip, and clock and reset signals that can be supplied by the master. The master can cold boot and download a program to the slave. The master does not have to be a Rabbit processor, but can be any type of processor capable of reading and writing standard registers. For a detailed description, see Chapter 13, Rabbit Slave Port. The slave processors slave port is connected to the master processors data bus. Communication between the master and the slave takes place via three registers, implemented in the Rabbit, for each direction of communication, for a total of six data registers. In addition, there is a slave port status register that can be read by either the master or the slave (see Figure 13-1). Two slave address lines are used by the master to select the register to be read or written. The registers that carry data from the master to the slave appear as write registers to the master and as read registers to the slave. The registers that operate in the opposite direction appear as read registers to the master and as write registers to the slave. These registers appear as read-write registers on both sides, but are not true read-write registers since different data may be read from what is written. The master provides the clock or strobe to store data in the three write registers under its control. The master also can do a write to the status register, which is used as a signaling device and does not actually write to the status register. The three registers that the master can write appear as read registers to the slave Rabbit. The master provides an enable strobe to read the three read data registers and the status register. These registers are write registers to the Rabbit. The first register or the three pairs of registers is special in that writing can interrupt the other processor in the master-slave communications link. An output line from the slave is asserted when the slave writes to slave register zero. This line can be used to interrupt the master. Internal circuits in the slave can be setup up to interrupt the slave when the master writes to slave register zero. The status register that is available to both sides keeps score on all the registers and reports if a potential interrupt is requested by either side. The status register keeps track of the "full-empty" status of each register. A register is considered full when one side of the link writes to it. It becomes empty if the other side reads it. In this way either side can test if the other side has modified a register or whether either side has even stored the same information to a register. The master-slave communication link makes possible "set and forget" communication protocols. Either side can issue a command or request by storing data in some register and then go about its business while the other side takes care of the request according to its own time schedule. The other side can be alerted by an interrupt that takes place when a store is made to register zero, or it can alert itself by a periodic poll of the status register. Users Manual 53 Of the three registers seen by each side for each direction of communication, the first register, slave register zero, has a special function because an interrupt can only be generated by a write to this register, which then causes an interrupt to take place on the other side of the link if the interrupt is enabled. One type of protocol is to store data first in registers 1 and 2, and then as the last step store to register 0. Then 24 bits of data will be available to the interrupt routine on the other side of the link. Bulk data transfers across the link can take place by an interrupt for each byte transferred, similar to a typical serial port or UART. In this case, a full-duplex transfer can take place, similar to what can be done with a UART. The overhead for such an interrupt-driven transfer will be on the order of 100 clocks per byte transferred, assuming a 20-instruction interrupt routine. (To keep the interrupt routine to 20 instructions, the interrupt routine needs to be very focused as opposed to general purpose.) Several methods are available to cater to a faster transfer with less computing overhead. There are enough registers to transfer two bytes on each interrupt, thus nearly halving the overhead. If a rendezvous is arranged between the processors, data can be transferred at approximately 25 clocks per byte. Each side polls the status register waiting for the other side to read/write a data register, which is then written/read again by the other side. 4.4.1 Slave Rabbit As A Protocol UART A prime application for the Rabbit used as a slave is to create a 4-port UART that can also handle the details of a communication protocol. The master sends and receives messages over the slave port. Error correction, retransmission, etc., can be handled by the slave. 54 Rabbit 2000 Microprocessor 5. PIN ASSIGNMENTS AND FUNCTIONS Users Manual 55 56 A2 A3 VDDCORE VSSCORE INT0B, I4, PE4 I3, PE3 I2, PE2 VDDIO CLK /CS2 STATUS /OE0 A10 /CS0 VDDCORE VSSCORE D7 D6 D5 D4 D3 D2 VSSIO VDDIO D1 D0 A0 A1 9 8 7 6 5 4 3 2 1 11 31 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 /SCS, I7, PE7 I6, PE6 INT1B, I5, PE5 5.1.1 Pinout 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 5.1 LQFP Package VSSIO 32 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 Rabbit 3000 (AT56C55-IL1T, IL2T) 128-pin Low-Profile Quad Flat Pack (LQFP) 14 14 Body, 0.4 mm pitch VDDIO, INT1A, I1, PE1 INT0A, I0, PE0 RXE, PG7 TXE, PG6 RCLKE, PG5 TCLKE, PG4 /IOWR /IORD /BUFEN /WDIOUT SMODE1 SMODE0 /RESET /CS1 VSSIO CLK32K RESOUT VBAT VSSIO PF7, AQD2A, PWM3 PF6, AQD2B, PWM2 PF5, AQD1A, PWM1 PF4, AQD1B, PWM0 PB7, IA5, /SLAVEATTN PB6, IA4 PB5, IA3, SA1 PB4, IA2, SA0 PB3, IA1, /SRD PB2, IA0, /SWR PB1, CLKA PB0, CLKB VDDIO XTALA2 XTALA1 VSSIO PA7, ID7, SD7 PA6, ID6, SD6 PA5, ID5, SD5 PA4, ID4, SD4 PA3, ID3, SD3 PA2, ID2, SD2 PA1, ID1, SD1 PA0, ID0, SD0 PF3, QD2A PF2, QD2B PF1, QD1A, CLKC PF0, QD1B, CLKD /WE1 A19 VDDIO Figure 5-1. Package Outline and Pin Assignments 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 ARXA, PD7 ATXA, PD6 ARXB, PD5 ATXB, PD4 PD3 PD2 PD1 PD0 RXF, PG3 TXF, PG2 RCLKF, PG1 TCLKF, PG0 VSSIO PC7, RXA VDDIO PC4, TXB PC5, RXB PC6, TXA PC0, TXD PC1, RXD VSSCORE VDDCORE PC2, TXC PC3, RXC VSSIO /OE1 A11 A9 A8 A13 A14 VSSCORE VDDCORE A17 /WE0 A18 A16 A15 A12 VDDIO VSSIO A7 A6 A5 A4 Rabbit 3000 Microprocessor 5.1.2 Mechanical Dimensions and Land Pattern Figure 5-2 shows the mechanical dimensions of the Rabbit 3000 LQFP package. 16.00 0.25 mm 14.00 0.10 mm 128 97 1 96 14.00 0.10 mm 32 65 33 64 0.18 0.05 mm 0.40 mm 1.40 0.05 mm 16.00 0.25 mm 0.10 0.05 mm 0.60 + 0.10 mm 0.15 mm The same pin dimensions apply along the x axis and the y axis. 1.00 mm Figure 5-2. Mechanical Dimensions Rabbit LQFP Package Users Manual 57 Figure 5-3 shows the PC board land pattern for the Rabbit 3000 chip in a 128-pin LQFP package. This land pattern is based on the IPC-SM-782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pattern Standard, IPC, Northbrook, IL, 1999. 16.85 mm (max.) 13.75 mm (min.) 0.40 mm 0.28 mm (max.) 1.55 mm 12.4 mm 15.3 mm TOLERANCE AND SOLDER JOINT ANALYSIS JT: 0.290.55 mm Lmin JH: 0.290.604 mm T Smax JS: -0.010.077 mm Wmin Zmax: 16.85 mm Gmin: 13.75 mm X: 0.28 mm (max.) Toe Fillet J: L: S: T: W: Heel Fillet Side Fillet Solder fillet min/max (toe, heel, and side respectively) Toe-to-toe distance across chip Heel-to-heel distance across chip Toe-to-heel distance on pin Width of pin Figure 5-3. PC Board Land Pattern for Rabbit 3000 128-pin LQFP 58 Rabbit 3000 Microprocessor 16.85 mm (max.) 13.75 mm (min.) 15.3 mm 12.4 mm 5.2 Ball Grid Array Package 5.2.1 Pinout Rabbit 3000 (AT56C55-IZ1T, IZ2T) 128-pin Thin Map Ball Grid Array (TFBGA) 10 10 Body, 0.8 mm pitch 1 A B C D E F G H J K L M VDDIO 2 VSSIO 3 PF7 4 PF5 5 PB6 6 PB2 7 XTALA2 8 PA6 9 PA2 10 11 12 PF3 PF1 PF0 CLK /CS2 PF6 PF4 PB5 PB1 XTALA1 PA5 PA1 PF2 /WE1 A19 STATUS /OE0 A10 PB7 PB4 PB0 VSSIO PA4 PA0 VDDIO VSSIO /OE1 /CS0 VDDCORE VSSCORE D7 PB3 VDDIO PA7 PA3 A11 A9 A8 A13 D6 D5 D4 D3 A14 VSSCORE VDDCORE A17 D2 VSSIO VDDIO D1 /WE0 A18 A16 A15 D0 A0 A1 A2 A12 VDDIO VSSIO A7 A3 VDDCORE VSSCORE PE7 A6 A5 A4 PC0 PE6 PE5 PE4 PE3 /WDTOUT /CS1 VBAT PD4 PD0 PC1 VSSCORE VDDCORE PE2 VSSIO VDDIO /IOWR SMODE1 VSSIO PD7 PD3 PG3 PG0 PC2 PC3 PE1 PE0 PG5 /IORD SMODE0 CLK32K PD6 PD2 PG2 VSSIO PC7 PC4 PG7 PG6 PG4 /BUFEN /RESET RESOUT PD5 PD1 PG1 VDDIO PC6 PC5 Figure 5-4. Ball Grid Array Pinout Looking Through the Top of Package Users Manual 59 5.2.2 Mechanical Dimensions and Land Pattern Table 5-2. Ball and Land Size Dimensions Nominal Ball Diameter (mm) 0.3 Tolerance Variation (mm) 0.350.25 Ball Pitch (mm) 0.8 Nominal Land Diameter (mm) 0.25 Land Variation (mm) 0.250.20 The design considerations in Table 5-3 are based on 5 mil design rules and assume a single conductor between solder lands. Table 5-3. Design Considerations (all dimensions in mm) Key A B C D E F G Feature Solder Land Diameter NSMD Defined Land Diameter Land to Mask Clearance (min.) Conductor Width (max.) Conductor Spacing (typ.) Via Capture Pad (max.) Via Drill Size (max.) Recommendation 0.254 (0.010) 0.406 (0.016) 0.050 (0.002) 0.127 (0.005) 0.127 (0.005) 0.406 (0.016) 0.254 (0.010) D A B C G E F Land and Trace Via 60 Rabbit 3000 Microprocessor TOP VIEW 1 A 0.80 BOTTOM VIEW 9 10 11 12 12 11 10 9 8 7 6 5 4 3 2 1 A B C D 10.00 0.05 2 3 4 5 6 7 8 B C D E F G H J K L M E F G H J K L M 0.80 10.00 0.05 Ball Pitch: 0.80 mm Ball Diameter: 0.3 mm (0.25~0.35) Figure 5-5. BGA Package Outline Users Manual 0.20~0.30 1.20 (max.) 61 5.3 Rabbit Pin Descriptions Table 5-1 lists all the pins on the device, along with their direction, function, and pin number on the package. Table 5-1. Rabbit Pin Descriptions Pin Group Hardware Pin Name CLK CLK32K /RESET RESOUT Direction Output Input Input Output Function Internal Clock 32 kHz Oscillator In Master Reset Reset Output Pin Numbers LQFP 2 49 46 50 Pin Numbers TFBGA B1 L6 M5 M6 XTALA1 Input Main Oscillator Inif an external clock is used, this pin should be driven by 113 the external clock; see Technical Note TN235 for more information on external oscillator circuits Main Oscillator Out Address Bus Data Bus WDT Time-Out Instruction Fetch First Byte Bootstrap Mode Select Memory Chip Select 0 Memory Chip Select 1 Memory Chip Select 2 114 various B7 XTALA2 CPU Buses ADDR[19:0] DATA[7:0] Status/Control /WDTOUT STATUS SMODE[1:0] /CS0 Memory Chip /CS1 Selects /CS2 Memory Output Enables /OE0 /OE1 Output Output Bidirectional Output Output Input Output Output Output Output Output Output Output Output Output Output A7 1015, 18 D4, E1E4, 19 F1, F4, G0 43 4 44, 45 7 47 3 J5 C1 K5, L5 D1 J6 B2 C2 C12 F9 B11 M4 L4 K4 Memory Output Enable 0 5 Memory Output Enable 1 95 Memory Write Enable 0 Memory Write Enable 1 I/O Buffer Enable I/O Read Enable I/O Write Enable 86 99 42 41 40 /WE0 Memory Write Enables /WE1 I/O Control /BUFEN /IORD /IOWR 62 Rabbit 3000 Microprocessor Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction Function Pin Numbers LQFP 111104 Pin Numbers TFBGA D7, A8, B8, C8, D8, A9, B9, C9 C4, A5, B5, C5, D5, A6, B6, C6 L11, M11, M12, L12, K12, K11, J10, H12 K7, L7, M7, J8, K8, L8, M8, J9 H4, J1J4, K1, L1L2 A3, B3, A4, B4, A10, B10, A11, A12 I/O ports I/O ports (continued) PA[7:0] Input / Output I/O Port A PB[7:0] Input / Output I/O Port B 123116 PC[7:0] 4 In / 4 Out I/O Port C 6671, 74, 75 PD[7:0] Input / Output I/O Port D 5259 2631, 34, 35 127124, 103100 PE[7:0] Input / Output I/O Port E PF[7:0] Input / Output I/O Port F PG[7:0] Power, VDDCORE processor core Power Processor I/O Ring VDDIO Input / Output I/O Port G M1, M2, L3, 3638, 60 M3, K9, L9, 63 M9, K10 8, 24, 72, 88 1, 17, 33, 65, 81, 97, 115 51 9, 25, 73, 89 16, 32, 48, 64, 80, 96, 112, 128 D2, E11, H2, J12 A1, C10, D6, F3, G10, K3, M10 J7 D3, E10, H3, J11 A2, C7, C11, F2, G11, K2, K6, L10 +3.3 V +3.3 V Power Battery VBAT Backup Ground Processor Core Ground Processor I/O Ring VSSCORE +3.3 V or battery Ground VSSIO Ground Users Manual 63 5.4 Bus Timing The external bus has essentially the same timing for memory cycles or I/O cycles. A memory cycle begins with the chip select and the address lines. One clock later, the output enable is asserted for a read. The output data and the write enable are asserted for a write. T1 Tw T2 Address (20 for memory, 16 for I/O) /IOCSn or /CSn /OEn or /IORD and /BUFEN (/BUFEN rd or wr) Data for read valid Data for write 3-s drive starts at end of T1 /WEn or /IOWR Notes: Read may have no wait states. Write cycles and I/O read cycles have at least 1 wait state. Clock may be asymmetric if clock doubler used. I/O chip select available on port E as option. Figure 5-6. Bus Timing Read and Write In some cases, the timing shown in Figure 5-6 may be prefixed by a false memory access during the first clock, which is followed by the access sequence shown in Figure 5-6. In this case, the address and often the chip select will change values after one clock and assume the final values for the memory to be actually accessed. Output enable and write enable are always delayed by one clock from the time the final, stable address and chip select are enabled. Normally the false memory access attempts to start another instruction access cycle, which is aborted after one clock when the processor realizes that a read data or write data bus cycle is needed. The user should not attempt a design that uses the chip select or a memory address as a clock or state changing signal without taking this into consideration. 64 Rabbit 3000 Microprocessor 5.5 Description of Pins with Alternate Functions Table 5-2. Pins With Alternate Functions Pin Name PA[7:0] PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Users Manual Output Function SLAVE D[7:0], ID[7:0] SLAVEATTN, IA5 IA4 IA3 IA2 IA1 IA0 CLKA CLKB n/a TXA n/a TXB n/a TXC n/a TXD APWM3* ATXA APWM2* ATXB Input Function SLAVE D[7:0], ID[7:0] Input Capture Option /ASCS* SD1 SD0 /SRD /SWR CLKA CLKB RXA n/a RXB n/a RXC n/a RXD n/a ARXA yes yes yes yes yes ARXB yes yes yes I7 I6 I5 I4 I3 I2 I1 I0 /SCS (slave chip select) INT1B INT0B INT1A INT0A 65 Table 5-2. Pins With Alternate Functions (continued) Pin Name PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 CLKC CLKD APWM1* TXE RCLKE TCLKE APWM0* TXF RCLKF TCLKF RCLKF, ARXF* TCLKF, ARCLKF* RCLKE, ARXE* TCLKE, ARCLKE* RXF yes Output Function PWM3 PWM2 PWM1 PWM0 Input Function AQD2A AQD2B AQD1A AQD1B QD2A QD2B QD1A, CLKC QD1B, CLKD RXE yes yes yes yes Input Capture Option yes * Introduced with Rabbit 3000A chip 66 Rabbit 3000 Microprocessor The alternate output functions identified in Table 5-2 are configured by setting the appropriate bits in the Paralle Port x Function Register. Table 5-3. Parallel Port x Alternate Functions Parallel Port x Function Register (PCFR) (PDFR) (PEFR) (PFFR) (PGFR) Description The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output. See Table 5-4 below. Only the bits that have alternate functions listed in Table 5-4 actually have a control bit in these registers. That is, there are four in Port C, four in Port D, eight in Port E, four in Port F, and eight in Port G. (Address = 0x0055) (Address = 0x0065) (Address = 0x0075) (Address = 0x003D) (Address = 0x004D) Bit(s) Value 0 7:0 1 Table 5-4. Parallel Port x Alternate Functions Control Bits Alternate Output Function Bit 7 6 5 4 3 2 1 0 Port B /SLAVEATTN, IA5 IA4 IA3 IA2 IA1 IA0 CLKA CLKB TXD TXC TXB TXA Port C Port D APWM3 ATXA APWM2 ATXB Port E I7 I6 I5 I4 I3 I2 I1 I0 CLKC CLKD Port F PWM3 PWM2 PWM1 PWM0 Port G APWM1 TXE RCLKE TCLKE APWM0 TXF RCLKF TCLKF Users Manual 67 5.6 DC Characteristics Table 5-5. Rabbit 3000 Absolute Maximum Ratings Symbol TA TS Parameter Operating Temperature Storage Temperature Maximum Input Voltage: Maximum Rating -55 to +85C -65 to +150C Oscillator Buffer Input 5-V-tolerant I/O VDD Maximum Operating Voltage VDD + 0.5 V 5.5 V 3.6 V Stresses beyond those listed in Table 5-5 may cause permanent damage. The ratings are stress ratings only, and functional operation of the Rabbit 3000 chip at these or any other conditions beyond those indicated in this section is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect the reliability of the Rabbit 3000 chip. Table 5-6 outlines the DC characteristics for the Rabbit 3000 at 3.3 V over the recommended operating temperature range from TA = 55C to +85C, VDD = 3.0 V to 3.6 V. Table 5-6. 3.3 Volt DC Characteristics Symbol VDD VIH VIL VOH VOL IIH IIL Parameter Supply Voltage High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage IOH = 6.8 mA, VDD = VDD (min) IOL = 6.8 mA, VDD = VDD (min) 0.7 VDD 0.4 Test Conditions Min 3.0 2.0 0.8 Typ 3.3 Max 3.6 Units V V V V Low-Level Output Voltage High-Level Input Current V VIN = VDD, (absolute worst case, all buffers) VDD = VDD (max) VIN = VSS, (absolute worst case, all buffers) VDD = VDD (max) Low-Level Input Current High-Impedance State Output Current (absolute worst case, all buffers) 10 A -10 A IOZ VIN = VDD or VSS, VDD = VDD (max), no pull-up -10 10 A 68 Rabbit 3000 Microprocessor 5.7 I/O Buffer Sourcing and Sinking Limit Unless otherwise specified, the Rabbit I/O buffers are capable of sourcing and sinking 6.8 mA of current per pin at full AC switching speeds. The limits are related to the maximum sustained current permitted by the metallization on the die. Users Manual 69 70 Rabbit 3000 Microprocessor 6. RABBIT INTERNAL I/O REGISTERS Users Manual 71 Table 6-1. Rabbit 3000 Peripherals and Interrupt Service Vectors On-Chip Peripheral System Management Memory Management Slave Port Parallel Port A Parallel Port F Parallel Port B Parallel Port G Parallel Port C Input Capture Parallel Port D Parallel Port E External I/O Control Pulse Width Modulator Quadrature Decoder External Interrupts Timer A Timer B Serial Port A (async/cks) Serial Port E (async/hdlc) Serial Port B (async/cks) Serial Port F (async/hdlc) Serial Port C (async/cks) Serial Port D (async/cks) RST 10 instruction RST 18 instruction RST 20 instruction RST 28 instruction RST 38 instruction ISR Starting Address {IIR[7:1], 0, 0x00} No interrupts {IIR[7:1], 0, 0x80} No interrupts No interrupts No interrupts No interrupts No interrupts {IIR[7:1], 1, 0xA0} No interrupts No interrupts No interrupts No interrupts {IIR[7:1], 1, 0x90} INT0 {EIR, 0x00} INT1 {EIR, 0x10} {IIR[7:1], 0, 0xA0} {IIR[7:1], 0, 0xB0} {IIR[7:1], 0, 0xC0} {IIR[7:1], 1, 0xC0} {IIR[7:1], 0, 0xD0} {IIR[7:1], 1, 0xD0} {IIR[7:1], 0, 0xE0} {IIR[7:1], 0, 0xF0} {IIR[7:1], 0, 0x20} {IIR[7:1], 0, 0x30} {IIR[7:1], 0, 0x40} {IIR[7:1], 0, 0x50} {IIR[7:1], 0, 0x70} 72 Rabbit 3000 Microprocessor 6.1 Default Values for all the Peripheral Control Registers The default values for all of the peripheral control registers are shown in Table 6-2. The registers within the CPU affected by reset are the Stack Pointer (SP), the Program Counter (PC), the IIR register, the EIR register, and the IP register. The IP register is set to all ones (disabling all interrupts), while all of the other listed CPU registers are reset to all zeros. Table 6-2. Rabbit Internal I/O Registers Register Name Global Control/Status Register Global Clock Modulator 0 Register Global Clock Modulator 1 Register Global Power Save Control Register Global Output Control Register Global Clock Double Register MMU Instruction/Data Register MMU Common Base Register MMU Bank Base Register MMU Common Bank Area Register Memory Bank 0 Control Register Memory Bank 1 Control Register Memory Bank 2 Control Register Memory Bank 3 Control Register MMU Expanded Code Register Memory Timing Control Register Breakpoint/Debug Control Register Slave Port Data 0 Register Slave Port Data 1 Register Slave Port Data 2 Register Slave Port Status Register Slave Port Control Register Global ROM Configuration Register Global RAM Configuration Register Global CPU Configuration Register Mnemonic GCSR GCM0R GCM1R GPSCR GOCR GCDR MMIDR STACKSEG DATASEG SEGSIZE MB0CR MB1CR MB2CR MB3CR MECR MTCR BDCR SPD0R SPD1R SPD2R SPSR SPCR GROM GRAM GCPU I/O Address 0x00 0x0A 0x0B 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1C 0x20 0x21 0x22 0x23 0x24 0x2C 0x2D 0x2E R/W R/W W W W W W R/W R/W R/W R/W W W W W R/W W W R/W R/W R/W R R/W R R R Reset 11000000 00000000 00000000 0000x000 00000000 00000000 00000000 00000000 00000000 11111111 00001000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxx000 xxxx0000 0xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 0xx00000 0xx00000 0xx00000 0xx00001 Users Manual 73 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Global Revision Register Port A Data Register Port B Data Register Port B Data Direction Register Port C Data Register Port C Function Register Port D Data Register Port D Control Register Port D Function Register Port D Drive Control Register Port D Data Direction Register Port D Bit 0 Register Port D Bit 1 Register Port D Bit 2 Register Port D Bit 3 Register Port D Bit 4 Register Port D Bit 5 Register Port D Bit 6 Register Port D Bit 7 Register Port E Data Register Port E Control Register Port E Function Register Port E Data Direction Register Port E Bit 0 Register Port E Bit 1 Register Port E Bit 2 Register Port E Bit 3 Register Port E Bit 4 Register Port E Bit 5 Register Port E Bit 6 Register Mnemonic GREV PADR PBDR PBDDR PCDR PCFR PDDR PDCR PDFR PDDCR PDDDR PDB0R PDB1R PDB2R PDB3R PDB4R PDB5R PDB6R PDB7R PEDR PECR PEFR PEDDR PEB0R PEB1R PEB2R PEB3R PEB4R PEB5R PEB6R I/O Address 0x2F 0x30 0x40 0x47 0x50 0x55 0x60 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x74 0x75 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E R/W R R/W R/W W R/W W R/W W W W W W W W W W W W W R/W W W W W W W W W W W Reset 0xx00000 xxxxxxxx 00xxxxxx 11000000 x0x1x1x1 x0x0x0x0 xxxxxxxx xx00xx00 xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx00xx00 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 74 Rabbit 3000 Microprocessor Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Port E Bit 7 Register Port F Data Register Port F Control Register Port F Function Register Port F Drive Control Register Port F Data Direction Register Port G Data Register Port G Control Register Port G Function Register Port G Drive Control Register Port G Data Direction Register Input Capture Ctrl/Status Register Input Capture Control Register Input Capture Trigger 1 Register Input Capture Source 1 Register Input Capture LSB 1 Register Input Capture MSB 1 Register Input Capture Trigger 2 Register Input Capture Source 2 Register Input Capture LSB 2 Register Input Capture MSB 2 Register I/O Bank 0 Control Register I/O Bank 1 Control Register I/O Bank 2 Control Register I/O Bank 3 Control Register I/O Bank 4 Control Register I/O Bank 5 Control Register I/O Bank 6 Control Register I/O Bank 7 Control Register PWM LSB 0 Register Mnemonic PEB7R PFDR PFCR PFFR PFDCR PFDDR PGDR PGCR PGFR PGDCR PGDDR ICCSR ICCR ICT1R ICS1R ICL1R ICM1R ICT2R ICS2R ICL2R ICM2R IB0CR IB1CR IB2CR IB3CR IB4CR IB5CR IB6CR IB7CR PWL0R I/O Address 0x7F 0x38 0x3C 0x3D 0x3E 0x3F 0x48 0x4C 0x4D 0x4E 0x4F 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 R/W W R/W W W W W R/W W W W W R/W W W W R R W W R R W W W W W W W W W Reset xxxxxxxx xxxxxxxx xx00xx00 xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xx00xx00 xxxxxxxx xxxxxxxx 00000000 00000000 xxxxxx00 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 000000xx 000000xx 000000xx 000000xx 000000xx 000000xx 000000xx 000000xx xxxxxxxx Users Manual 75 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name PWM MSB 0 Register PWM LSB 1 Register PWM MSB 1 Register PWM LSB 2 Register PWM MSB 2 Register PWM LSB 3 Register PWM MSB 3 Register Quad Decode Ctrl/Status Register Quad Decode Control Register Quad Decode Count 1 Register Quad Decode Count 2 Register Interrupt 0 Control Register Interrupt 1 Control Register Real Time Clock Control Register Real Time Clock Byte 0 Register Real Time Clock Byte 1 Register Real Time Clock Byte 2 Register Real Time Clock Byte 3 Register Real Time Clock Byte 4 Register Real Time Clock Byte 5 Register Timer A Control/Status Register Timer A Prescale Register Timer A Time Constant 1 Register Timer A Control Register Timer A Time Constant 2 Register Timer A Time Constant 8 Register Timer A Time Constant 3 Register Timer A Time Constant 9 Register Timer A Time Constant 4 Register Timer A Time Constant 10 Register Mnemonic PWM0R PWL1R PWM1R PWL2R PWM2R PWL3R PWM3R QDCSR QDCR QDC1R QDC2R I0CR I1CR RTCCR RTC0R RTC1R RTC2R RTC3R RTC4R RTC5R TACSR TAPR TAT1R TACR TAT2R TAT8R TAT3R TAT9R TAT4R TAT10R I/O Address 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x94 0x96 0x98 0x99 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0xA0 0xA1 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA R/W W W W W W W W R/W W R R W W W R/W R R R R R R/W W W W W W W W W W Reset xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00xx0000 xxxxxxxx xxxxxxxx xx000000 xx000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 xxxxxxx1 xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 76 Rabbit 3000 Microprocessor Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Timer A Time Constant 5 Register Timer A Time Constant 6 Register Timer A Time Constant 7 Register Timer B Control/Status Register Timer B Control Register Timer B MSB 1 Register Timer B LSB 1 Register Timer B MSB 2 Register Timer B LSB 2 Register Timer B Count MSB Register Timer B Count LSB Register Serial Port A Data Register Serial Port A Address Register Serial Port A Long Stop Register Serial Port A Status Register Serial Port A Control Register Serial Port A Extended Register Serial Port B Data Register Serial Port B Address Register Serial Port B Long Stop Register Serial Port B Status Register Serial Port B Control Register Serial Port B Extended Register Serial Port C Data Register Serial Port C Address Register Serial Port C Long Stop Register Serial Port C Status Register Serial Port C Control Register Serial Port C Extended Register Serial Port D Data Register Mnemonic TAT5R TAT6R TAT7R TBCSR TBCR TBM1R TBL1R TBM2R TBL2R TBCMR TBCLR SADR SAAR SALR SASR SACR SAER SBDR SBAR SBLR SBSR SBCR SBER SCDR SCAR SCLR SCSR SCCR SCER SDDR I/O Address 0xAB 0xAD 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xF0 R/W W W W R/W W W W W W R R R/W R/W R/W R W W R/W R/W R/W R W W R/W R/W R/W R W W R/W Reset xxxxxxxx xxxxxxxx xxxxxxxx xxxxx000 xxxx0000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx Users Manual 77 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Serial Port D Address Register Serial Port D Long Stop Register Serial Port D Status Register Serial Port D Control Register Serial Port D Extended Register Serial Port E Data Register Serial Port E Address Register Serial Port E Long Stop Register Serial Port E Status Register Serial Port E Control Register Serial Port E Extended Register Serial Port F Data Register Serial Port F Address Register Serial Port F Long Stop Register Serial Port F Status Register Serial Port F Control Register Serial Port F Extended Register Watchdog Timer Control Register Watchdog Timer Test Register Mnemonic SDAR SDLR SDSR SDCR SDER SEDR SEAR SELR SESR SECR SEER SFDR SFAR SFLR SFSR SFCR SFER WDTCR WDTTR I/O Address 0xF1 0xF2 0xF3 0xF4 0xF5 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0x08 0x09 R/W R/W R/W R W W R/W R/W R/W R W W R/W R/W R/W R W W W W Reset xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 00000000 00000000 78 Rabbit 3000 Microprocessor 7. MISCELLANEOUS FUNCTIONS 7.1 Processor Identification Four read-only registers are provided to allow software to identify the Rabbit microprocessor and recognize the features and capabilities of the chip. Five bits in each of these registers are unique to each version of the chip. One register is reserved for the on-chip flash memory configuration (GROM), one register is reserved for the on-chip RAM memory configuration (GRAM), one register identifies the CPU (GCPU), and the final register is reserved for revision identification (GREV). The Rabbit 3000 does not contain on-chip SRAM or flash memories. Table 7-1. Global ROM Configuration Register Global ROM Configuration Register Bit(s) 7 (read only) 6:5 4:0 Value 0 1 read 00000 (GROM) Description Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. These bits report the state of the SMODE pins. ROM identifier for this version of the chip. (Address = 0x2C) Table 7-2. Global RAM Configuration Register Global RAM Configuration Register Bit(s) 7 (read only) 6:5 4:0 Value 0 1 read 00000 (GRAM) Description Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. These bits report the state of the SMODE pins. RAM identifier for this version of the chip. (Address = 0x2D) Users Manual 79 Table 7-3. Global CPU Register Global CPU Register Bit(s) 7 (read only) 6:5 4:0 Value 0 1 read 00001 (GCPU) Description Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. These bits report the state of the SMODE pins. CPU identifier for this version of the chip. (Address = 0x2E) Table 7-4. Global Revision Register Global Revision Register Bit(s) 7 (read only) 6:5 4:0 Value 0 1 read 00000 (GREV) Description Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. These bits report the state of the SMODE pins. Revision identifier for this version of the chip. (Address = 0x2F) 7.2 Rabbit Oscillators and Clocks The Rabbit 3000 usually requires two separate clocks. The main clock normally drives the processor core and most of the peripheral devices, and the 32.768 kHz clock drives the battery-backable time-date clock and other circuitry. Main Clock An oscillator buffer is built into the Rabbit 3000 that may be used to implement the main processor oscillator (Figure 7-1). For lowest power an external oscillator may be substituted for the built-in oscillator circuit. An oscillator implemented using the built in buffer accepts crystals up to a frequency of 27 MHz (first overtone crystals only). This frequency may be then doubled by the clock doubler. The component values shown in the figure for the oscillator circuits are subject to adjustment depending on the crystal used and the operating frequency. The Rabbit 3000 has a spectrum spreader unit that modifies the clock by shortening and lengthening clock cycles. The effect of this is to spread the spectral energy of the clock harmonics over a fairly wide range of frequencies. This limits the peak energy of the harmonics and reduces EMI that may interfere with other devices as well as reducing the readings in government mandated EMI tests. The spectrum spreader has two operating modes, normal spreading and strong spreading. The spreader can also be turned off. 80 Rabbit 3000 Microprocessor 32.768 kHz Clock The 32.768 kHz clock is primarily used to clock the on-chip real-time clock. In addition, it is also used to support remote cold boot via Serial Port A, driving the 2400 baud communications used to initiate the cold boot. Another function of the 32.768 kHz oscillator is to drive the low power sleepy mode with the main oscillator shut down to reduce power. The 32.768 kHz clock can be left out of a system provided that its functions are not required. Rabbit 3000 CLK clock out 2 f/2 f/1 XTALB1 113 Processor clock enb 1 MW 2.5 kW XTALB2 114 enb enb enb Spectrum Spreader R1 and R2 control the power consumed by the unbuffered inverter. VBAT R1 SN74AHC1GU04 Clock Doubler f/(8,6,4,2) Divider f/(1,2,4,8,16) 49 Cin U1A R2 NC7SP14 U2A Rp 22 MW CL = 7 pF 32.768 kHz C1 C2 Rs 330 kW Peripheral clock Watchdog Timer Real-Time Clock Note: Peripherals cannot be clocked slower than processor Reference design for 32.768 kHz oscillator Figure 7-1. Clock Distribution TN235, External 32.768 kHz Oscillator Circuits, provides further information on oscillator circuits and selecting the values of components to use in the oscillator circuit. Users Manual 81 Table 7-5. Global Control/Status Register Global Control/Status Register Bit(s) Value 00 7:6 (rd-only) 01 10 11 0 5 1 4:2 xxx 00 01 1:0 10 11 Periodic interrupts use Interrupt Priority 2. Periodic interrupts use Interrupt Priority 3. Force a Periodic interrupt to be pending. See table below for decode of this field. Periodic interrupts are disabled. Periodic interrupts use Interrupt Priority 1. (GCSR) Description No Reset or Watchdog Timer time-out since the last read. The Watchdog Timer timed out. These bits are cleared by a read of this register. This bit combination is not possible. Reset occurred. These bits are cleared by a read of this register. No effect on the Periodic interrupt. This bit will always be read as zero. (Address = 0x00) Table 7-6. Clock Select Field of GCSR Clock Select Bits 4:2 GCSR 000 001 010 011 100 101 110 111 CPU Clock osc/8 osc/8 osc osc/2 32 kHz or fraction 32 kHz or fraction osc/4 osc/6 Peripheral Clock osc/8 osc osc osc/2 32 kHz or fraction 32 kHz or fraction osc/4 osc/6 Main Oscillator on on on on on off on on Power-Save CS if Enabled by GPSCR short CS option short CS option none none self-timed option self-timed option short CS option short CS option 82 Rabbit 3000 Microprocessor 7.3 Clock Doubler The clock doubler is provided to allow a lower frequency crystal to be used for the main oscillator and to provide an added range of clock frequency adjustability. The clock doubler is controlled via the Global Clock Double Register as shown in Table 7-7. Table 7-7. Global Clock Double Register Global Clock Double Register Bit(s) 7:4 Value xxxx 0000 0001 0010 0011 0100 0101 0110 0111 3:0 1000 1001 1010 1011 1100 1101 1110 1111 13 ns nominal low time 14 ns nominal low time 15 ns nominal low time 16 ns nominal low time 17 ns nominal low time 18 ns nominal low time 19 ns nominal low time. 20 ns nominal low time Reserved The clock doubler circuit is disabled. 6 ns nominal low time 7 ns nominal low time 8 ns nominal low time 9 ns nominal low time 10 ns nominal low time 11 ns nominal low time 12 ns nominal low time (GCDR) Description (Address = 0x0F) The clock doubler uses an on-chip delay circuit that must be programmed by the user at startup if there is a need to double the clock. Table 7-8 lists the recommended delays for the Global Clock Double Register for various oscillator frequencies. Table 7-8. Recommended Delays Set In GCDR for Clock Doubler Recommended GCDR Value 15 13 9 6 3 0 Users Manual Frequency Range 7.3728 MHz 7.372811.0592 MHz 11.059216.5888 MHz 16.588820.2752 MHz 20.275252.8384 MHz >52.8384 MHz 83 When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as shown in Figure 7-2. P Oscillator Oscillator delayed and inverted Doubled clock Delay time 0.48P 0.52P 0.48P 0.52P 48% 52% Example Write Cycle Address / CS Data out write pulse early write pulse option Address / CS Example Read Cycle data out from mem output enb early output enb option Figure 7-2. Effect of Clock Doubler The doubled-clock low time is subject to wide (50%) variation since it depends on process parameters, temperature, and voltage. The times given above are for a supply voltage of 3.3 V and a temperature of 25C. The doubled-clock low time increases by 20% when the voltage is reduced to 2.5 V, and increases by about 40% when the voltage is reduced further to 2.0 V. The values increase or decrease by 1% for each 5C increase or decrease in temperature. The doubled clock is created by xoring the delayed and inverted clock with itself. If the original clock does not have a 50-50 duty cycle, then alternate clocks will have a slightly different length. Since the duty cycle of the built-in oscillator can be as asymmetric as 52-48, the clock generated by the clock doubler will exhibit up to a 4% 84 Rabbit 3000 Microprocessor variation in period on alternate clocks. This does not affect the no-wait states memory access time since two adjacent clocks are always used. However, the maximum allowed clock speed must be slightly reduced if the clock is supplied via the clock doubler. The only signals clocked on the falling edge of the clock are the memory and I/O write pulses and the early option memory output enable. See Chapter 8 for more information on the early output enable and write enable options. The spectrum spreader either stretches or shrinks the low plateau of the clock by a maximum of 3 ns for the normal spreading and 4.5 ns for the strong spreading. If the clock doubler is used this will cause an additional asymmetry between alternate clock cycles. The power consumption is proportional to the clock frequency, and for this reason power can be reduced by slowing the clock when less computing activity is taking place. The clock doubler provides a convenient method of temporarily speeding up or slowing down the clock as part of a power management scheme. Users Manual 85 7.4 Clock Spectrum Spreader When enabled the spectrum spreader stretches and compresses the clocks in a complex pattern that results in spreading the energy in the clock harmonics over a wide range of frequencies. The spectrum spreader has a normal and a strong setting. With either setting the peak spectral strength of the clock harmonics is reduced by approximately 15 dB for frequencies above 100 MHz. For lower frequencies the strong spreading has a greater effect in reducing the peak spectral strength as shown in the figure below. 15dB Strong Spreading 10 Normal Spreading 5 50 100 150 200 MHz 250 300 350 Figure 7-3. Reduction in Peak Spectral Strength from Spectrum Spreader In the normal spectrum spreading mode, the maximum shortening of the clock cycle is 3 nanoseconds at 3.3 V and 25C. In the strong spreading mode the maximum shortening of a clock cycle under the same conditions is 4.5 ns. The reduction in peak spectral strength is roughly independent of the clock frequency. Special precautions must be followed in setting the GCM0R and GCM1R registers (see Section 15.2, Using the Clock Spectrum Spreader). 86 Rabbit 3000 Microprocessor 7.5 Chip Select Options for Low Power Some types of flash memory and RAM consume power whenever the chip select is enabled even if no signals are changing. The chip select behavior of the Rabbit 3000 can be modified to reduce unnecessary power consumption when the Rabbit 3000 is running at a reduced clock speed. The short chip select option can be enabled when the processor clock is divided (by 4, 6, or 8) so as to run at a lower speed. The short chip select option is exercised with clock select bits 4:2 of the GCSR register as shown in Table 7-6. Whether the chip select is normal or short is then determined by whether bit 4 in the GPSCR register is 0 or 1. When the short chip select option is enabled, the chip select delays turning on until the end of the of the memory cycle when it turns on for the last 2 undivided clocks. If the clock is divided by 6, the memory read cycle with no wait states would normally be 12 undivided clocks long. With the short chip select, the chip select is on for only 2/12 clocks for a memory duty cycle of 1/6. If wait states are added, the duty cycle is reduced even more. For example, if there is one wait state and the clock is divided by 6, the memory bus cycle will be 18 undivided clocks long and the duty cycle will be 2/18 = 1/9 with the short chip select option enabled. When the short chip select option is enabled, the interrupt sequence will attempt to write the return address to the stack if an interrupt takes place immediately after an internal or an external I/O instruction. The chip select will be suppressed during the write cycle, and the correct return address will not be stored on the stack. This happens only when an interrupt takes place immediately after an I/O instruction when the short chip select option is enabled. Therefore, when using the short chip select option, ensure that interrupts are disabled during I/O instructions (or do not use short chip select). Interrupts can be disabled for a single I/O instruction as shown in the following example. PUSH IP IPSET 3 IOE LD a,(hl) POP IP ; ; ; ; save interrupt state interrupts off typical I/O instruction reenable interrupts When the 32.768 kHz clock is used as the main processor clock (sleepy mode) the memory duty cycle can be reduced by enabling a self-timed chip select mode. When the 32.768 kHz clock is used, the clock period is approximately 32 s, and a normal memory read cycle without wait states will be approximately 64 s. No more than a few hundred nanoseconds are needed to read the memory. The main oscillator is normally shut down when operating at 32 kHz, and no faster clock is available to time out a short chip select cycle. To provide for a low-memory-duty cycle, a chip select and memory read can take place under control of a delay timer that is on the chip. The cycle starts at the start of the final 64 s clock of the memory cycle and can be set to enable chip select for a period in the range of 70 to 200 ns. The data are clocked in early at the end of the delay-driven cycle. The chip select duty cycle is very small, about 0.2/128 = 1/600. Users Manual 87 When operating in the 32 kHz mode, it is also possible to further divide the clock to a frequency as low as 2 kHz, further reducing execution speed and current consumption. Global Power Save Control Register Bit(s) Value 000 001 01x 7:5 100 101 110 111 4 3 0 1 x 000 001 01x 2:0 100 101 110 111 (GPSCR) Description Self-timed chip selects are disabled. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. 296 ns self-timed chip selects (192 ns best case, 457 ns worst case). 234 ns self-timed chip selects (151 ns best case, 360 ns worst case). 171 ns self-timed chip selects (111 ns best case, 264 ns worst case). 109 ns self-timed chip selects (71 ns best case, 168 ns worst case). Normal Chip Select operation. Short Chip Select timing when dividing main oscillator by 4, 6, or 8. This bit is reserved and should not be used. The 32 kHz clock divider is disabled. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. 32 kHz oscillator divided by two (16.384 kHz). 32 kHz oscillator divided by four (8.192 kHz). 32 kHz oscillator divided by eight (4.096 kHz). 32 kHz oscillator divided by sixteen (2.048 kHz). (Address = 0x0D) It is anticipated that these measures would reduce operating current consumption to as low as 20 A plus some additional leakage that would be significant at high operating temperatures. 88 Rabbit 3000 Microprocessor T1 T2 clock ADDR Valid DATA MEMCSxB MEMOExB Figure 7-4. Short Chip Select Memory Read T1 T2 32 kHz ADDR Valid DATA Valid MEMCSxB MEMOExB ~100 ns Figure 7-5. Self-Timed Chip Select Memory Read Cycle Users Manual 89 7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN Certain output pins can have alternate assignments as specified in Table 7-9. Table 7-9. Global Output Control Register (GOCR = 0x0E) Bit(s) Value 00 01 7:6 10 11 00 01 5:4 10 11 1 3 0 2 x 00 01 1:0 10 11 /BUFEN pin is low. /BUFEN pin is high. WDTOUTB pin follows watchdog function. This bit is ignored. /BUFEN pin is active (low) during external I/O cycles. /BUFEN pin is active (low) during data memory accesses. STATUS pin is low. STATUS pin is high. WDTOUTB pin is low (1 cycle minimum, 2 cycles maximum, of 32 kHz). CLK pin is low. CLK pin is high. STATUS pin is active (low) during a first opcode byte fetch. STATUS pin is active (low) during an interrupt acknowledge. Description CLK pin is driven with peripheral clock. CLK pin is driven with peripheral clock divided by 2. 90 Rabbit 3000 Microprocessor 7.7 Time/Date Clock (Real-Time Clock) The time/date clock (RTC) is a 48-bit (ripple) counter that is driven by the 32.768 kHz oscillator. The RTC is a modified ripple counter composed of six separate 8-bit counters. The carries are fed into all six 8-bit counters at the same time and then ripple for 8 bits. The time for this ripple to take place is a few nanoseconds per bit, and certainly should not should not exceed 200 ns for all 8 bits, even when operating at low voltage. The 48 bits are enough to count up 272 years at the 32 kHz clock frequency. By convention, 12 AM on January 1, 1980, is taken as time zero. Z-World software ignores the highest order bit, giving the counter a capacity of 136 years from January 1, 1980. To read the counter value, the value is first transferred to a 6-byte holding register. Then the individual bytes may be read from the holding registers. To perform the transfer, any data bits are written to RTC0R, the first holding register. The counter may then be read as six 8-bit bytes at RTC0R through RTC5R. The counter and the 32 kHz oscillator are powered from a separate power pin that can be provided with power while the remainder of the chip is powered down. This design makes battery backup possible. Since the processor operates on a different clock than the RTC, there is the possibility of performing a transfer to the holding registers while a carry is taking place, resulting in incorrect information. In order to prevent this, the processor should do the clock read twice and make sure that the value is the same in both reads. If the processor is itself operating at 32 kHz, the read-clock procedure must be modified since a number of clock counts would take place in the time needed by the slow-clocked processor to read the clock. An appropriate modification would be to ignore the lower bytes and only read the upper 5 bytes, which are counted once every 256 clocks or every 1/128th of a second. If the read cannot be performed in this time, further low-order bits can be ignored. The RTC registers cannot be set by a write operation, but they can be cleared and counted individually, or by subset. In this manner, any register or the entire 48-bit counter can be set to any value with no more than 256 steps. If the 32 kHz crystal is not installed and the input pin is grounded, no counting will take place and the six registers can be used as a small battery-backed memory. Normally this would not be very productive since the circuitry needed to provide the power switchover could also be used to battery-back a regular low-power static RAM. Users Manual 91 Table 7-10. Real-Time Clock RTCxR Data Registers Real-Time Clock x Holding Register (RTC0R) R/W (RTC1R) (RTC2R) (RTC3R) (RTC4R) (RTC5R) Description The current value of the 48-bit RTC holding register is returned. Writing to the RTC0R transfers the current count of the RTC to six holding registers while the RTC continues counting. (Address = 0x02) (Address = 0x03) (Address = 0x04) (Address = 0x05) (Address = 0x06) (Address = 0x07) Bit(s) 7:0 Value Read Write Table 7-11. Real-Time Clock Control Register (RTCCR adr = 0x01) Bit(s) Value Description Writing a 0x00 to the RTCCR has no effect on the RTC counter. However, depending on what the previous command was, writing a 0x00 may either 1. disable the byte increment function or 2. cancel the RTC reset command If the 0xC0 command is followed by a 0x00 command, only the byte increment function will be disabled. The RTC reset will still take place. Arm RTC for a reset with code 0x80 or reset and byte increment function with code 0x0C0. Resets all six bytes of the RTC counter to 0x00 if proceeded by arm command 0x40. Resets all six bytes of the RTC counter to 0x00 and enters byte increment modeprecede this command with 0x40 arm command. This bit combination must be used with every byte increment write to increment clock(s) register corresponding to bit(s) set to "1". Example: 01001101 increments registers: 0, 2,3. The byte increment mode must be enabled. Storing 0x00 cancels the byte increment mode. No effect on the RTC counter. Increment the corresponding byte of the RTC counter. 0x00 7:0 0x40 0x80 0xC0 7:6 01 0 5:0 1 92 Rabbit 3000 Microprocessor 7.8 Watchdog Timer The watchdog timer is a 17-bit counter. In normal operation it is driven by the 32.768 kHz clock. When the watchdog timer reaches any of several values corresponding to a delay of from 0.25 to 2 seconds, it times out. When it times out, it emits a 1-clock pulse from the watchdog output pin and it resets the processor via an internal circuit. To prevent this timeout, the program must hit the watchdog timer before it times out. The hit is accomplished by storing a code in WDTCR. Note that although a watchdog timeout resets the processor, it does not reset the timeout period stored in the WDTCR. This was done intentionally because an application may require the initialization of the processor resulting from the watchdog timeout to be based on a specific timeout period that is different from that of the reset initialization. Table 7-12. Watchdog Timer Control Register (WDTCR adr = 0x08) Bit(s) 7:0 Value 0x5A 0x57 0x59 0x53 0x5F other Description Restart (hit) the watchdog timer, with a 2-second timeout period. Restart (hit) the watchdog timer, with a 1-second timeout period. Restart (hit) the watchdog timer, with a 500 ms timeout period. Restart (hit) the watchdog timer, with a 250 ms timeout period. Restart the secondary watchdog timer (starting with Rabbit 3000A chip). No effect on watchdog timer. The watchdog timer may be disabled by storing a special code in the WDTTR register. Normally this should not be done unless an external watchdog device is used. The purpose of the watchdog is to unhang the processor from an endless loop caused by a software crash or a hardware upset. It is important to use extreme care in writing software to hit the watchdog timer (or to turn off the watchdog timer). The programmer should not sprinkle instructions to hit the watchdog timer throughout his program because such instructions can become part of an endless loop if the program crashes and thus disable the recovery ability given by having a watchdog. The following is a suggested method for hitting the watchdog. An array of bytes is set up in RAM. Each of these bytes is a virtual watchdog. To hit a virtual watchdog, a number is stored in a byte. Every virtual watchdog is counted down by an interrupt routine driven by a periodic interrupt. This can happen every 10 ms. If none of the virtual watchdogs has counted down to zero, the interrupt routine hits the hardware watchdog. If any have counted down to zero, the interrupt routine disables interrupts, and then enters an endless loop waiting for the reset. Hits of the virtual watchdogs are placed in the users program at must exercise locations. Users Manual 93 Table 7-13. Watchdog Timer Test Register (WDTTR adr = 0x09) Bit(s) Value 0x51 0x52 0x53 7:0 0x54 Description Clock the least significant byte of the watchdog timer from the peripheral clock. (Intended for chip test and code 0x54 below only.) Clock the most significant byte of the watchdog timer from the peripheral clock. (Intended for chip test and code 0x54 below only.) Clock both bytes of the watchdog timer, in parallel, from the peripheral clock. (Intended for chip test and code 0x54 below only.) Disable the watchdog timer. This value, by itself, does not disable the watchdog timer. Only a sequence of two writes, where the first write is 0x51, 0x52, or 0x53, followed by a write of 0x54, actually disables the watchdog timer. The watchdog timer will be re-enabled by any other write to this register. Normal clocking (32 kHz oscillator) for the watchdog timer. This is the condition after reset. other The code to do this may also hit the watchdog with a 0.25-second period to speed up the reset. Such watchdog code must be written so that it is highly unlikely that a crash will incorporate the code and continue to hit the watchdog in an endless loop. The following suggestions will help. 1. Place a jump to self before the entry point of the watchdog hitting routines. This prevents entry other than by a direct call or jump to the routine. 2. Before calling the routine, set a data byte to a special value and then check it in the routine to make sure the call came from the right caller. If not, go into an endless loop with interrupts disabled. 3. Maintain data corruption flags and/or checksums. If these go wrong, go into an endless loop with interrupts off. 94 Rabbit 3000 Microprocessor 7.9 System Reset The Rabbit 3000 contains a master reset input (pin 46), which initializes everything in the device except for the Real-Time Clock (RTC). This reset is delayed until the completion of any write cycles in progress to prevent potential corruption of memory. If no write cycles are in progress the reset takes effect immediately. The reset sequence requires a minimum of 128 cycles of the fast oscillator to complete, even if no write cycles were in progress at the start of the reset. Reset forces both the processor clock and the peripheral clock in the divide-by-eight mode. Note that if the processor is being clocked from the 32 kHz clock, the 128 cycles of the fast oscillator will probably not be sufficient to allow any writes in progress to be completed before the reset sequence completes and the clocks switch to divide-by-eight mode. During reset /CS1 is high impedance and all of the other memory and I/O control signals are held inactive (High). After the /RESET signal becomes inactive (High) the processor begins fetching instructions and the memory control signals begin normal operation. Note that the default values in the Memory Bank Control Registers select four wait states per access, so the initial program fetch memory reads are 48 clock cycles long (8 x (2 + 4)). Software can immediately adjust the processor timing to whatever the system requires. /CS1 is high-impedance during reset (and during power-down, when only VBAT is powered) to allow an external RAM connected to /CS1 to be powered by VBAT. This is possible because the /CS1 pin is powered by VBAT. In this case an external pull-up resistor (to VBAT) is required on /CS1 to keep the RAM deselected during power-down. If the external RAM connected to /CS1 is not powered by VBAT, so that any information held within it is lost during power-down, no pull-up resistor on /CS1 is appropriate, as this would add leakage (through the protection diode) to drain VBAT. The RESOUT signal, which is High during reset and power-down, can be used to control an external power switch to disconnect VDD from supplying VBAT. The default selection for the memory control signals consists of /CS0 and /OE0, and writes are disabled. This selection can also be immediately programmed to match the hardware configuration. A typical sequence would be to speed up the clock to full speed, followed by selection of the appropriate number of wait states and the chip select signals, output enable signals and write enable signals. At this point software would usually check the system status to determine what type of reset just occurred and begin normal operation. The default values for all of the peripheral control registers are shown with the following register listing. The registers within the CPU affected by reset are the Stack Pointer (SP), the Program Counter (PC), the IIR register, the EIR register, and the IP register. The IP register is set to all ones (disabling all interrupts), while all of the other listed CPU registers are reset to all zeros. Table 7-14 describes the state of the I/O pins after an external reset is recognized by the Rabbit CPU. Note that the /RESET signal must be held low for three clocks for the processor to begin the reset sequence. There is no facility to tri-state output lines such as the address lines and the memory and I/O control lines. Users Manual 95 Table 7-14. Rabbit 3000 Reset Sequence and State of I/O Pins Pin Name /RESET CLK CLK32K RESOUT XTALA1 XTALA2 A[19:0] D[7:0] /WDTOUT STATUS SMODE[1:0] /CS0 /CS1 /CS2 /OE0 /OE1 /WE0 /WE1 /BUFEN /IORD /IOWR PA[7:0] PB[7:0] PC[7:0] PD[7:0] PE[7:0] PF[7:0] PG[7:0] Direction Input Output Input Output Input Output Output Bidirectional Output Output Input Output Output Output Output Output Output Output Output Output Output Input/Output Input/Output 4 In/4 Out Input/Output Input/Output Input/Output Input/Output /RESET Low* Recognized by CPU Low or High High Not Affected High Not Affected Not Affected Last Value High Z High High Not Affected High High Z High High High High High High High High Post-Reset High Operational Not Affected Low Not Affected Not Affected 0x00000 High Z High Operational (as /IFTCH1) Not Affected Operational High High Operational High High High High High High zzzzzzzz 00zzzzzz z0z1z1z1 zzzzzzzz zzzzzzzz zzzzzzzz zzzzzzzz zzzzzzzz 00zzzzzz z0z1z1z1 zzzzzzzz zzzzzzzz zzzzzzzz zzzzzzzz * A low is recognized internally by the processor after a reset The default state of the I/O ports after the completion of the reset and initialization sequences 96 Rabbit 3000 Microprocessor 7.10 Rabbit Interrupt Structure An interrupt causes a call to be executed, pushing the PC on the stack and starting to execute code at the interrupt vector address. The interrupt vector addresses have a fixed lower byte value for all interrupts. The upper byte is adjustable by setting the registers EIR and IIR for external and internal interrupts respectively. There are only two external interrupts generated by transitions on certain pins in Parallel Port E. The interrupt vectors are shown in Table 6-2. The interrupts differ from most Z80 or Z180 interrupts in that the 256-byte tables pointed to EIR and IIR contain the actual instructions beginning the interrupt routines rather than a 16-bit pointer to the routine. The interrupt vectors are spaced 16 bytes apart so that the entire code will fit in the table for very small interrupt routines. Interrupts have priority 1, 2 or 3. The processor operates at priority 0, 1, 2 or 3. If an interrupt is being requested, and its priority is higher than the priority of the processor, the interrupt will take place after then next instruction. The interrupt automatically raises the processors priority to its own priority. The old processor priority is pushed into the 4position stack of priorities contained in the IP register. Multiple devices can be requesting interrupts at the same time. In each case there is a latch set in the device that requests the interrupt. If that latch is cleared before the interrupt is latched by the central interrupt logic, then the interrupt request is lost and no interrupt takes place. This is shown in Table 7-15. The priorities shown in this table apply only for interrupts of the same priority level and are only meaningful if two interrupts are requested at the same time. Most of the devices can be programmed to interrupt at priority level 1, 2 or 3. Users Manual 97 Table 7-15. InterruptsPriority and Action to Clear Requests Priority Highest Interrupt Source External 1 External 0 Periodic (2 kHz) Quadrature Decoder Timer B Timer A Input Capture Slave Port Action Required to Clear the Interrupt Automatically cleared by the interrupt acknowledge. Automatically cleared by the interrupt acknowledge. Read the status from the GCSR. Read the status from the QDCSR. Read the status from the TBSR. Read the status from the TASR. Read the status from the ICCSR. Rd: Read the data from the SPD0R, SPD1R or SPD2R. Wr: Write data to the SPD0R, SPD1R, SPD2R or write a dummy byte to the SPSR. Rx: Read the data from the SEDR or SEAR. Tx: Write data to the SEDR, SEAR, SELR or write a dummy byte to the SESR. Rx: Read the data from the SFDR or SFAR. Tx: Write data to the SFDR, SFAR, SFLR or write a dummy byte to the SFSR. Rx: Read the data from the SADR or SAAR. Tx: Write data to the SADR, SAAR, SALR or write a dummy byte to the SASR. Rx: Read the data from the SBDR or SBAR. Tx: Write data to the SBDR, SBAR, SBLR or write a dummy byte to the SBSR. Rx: Read the data from the SCDR or SCAR. Tx: Write data to the SCDR, SCAR, SCLR or write a dummy byte to the SCSR. Rx: Read the data from the SDDR or SDAR Tx: Write date to the SDDR, SDAR, SDLR or write a dummy byte to the SDSR Serial Port E Serial Port F Serial Port A Serial Port B Serial Port C Lowest Serial Port D In the case of the external interrupts the only action that will clear the interrupt request is for the interrupt to take place, which automatically clears the request. A special action must be taken in the interrupt service routine for the other interrupts. 98 Rabbit 3000 Microprocessor 7.10.1 External Interrupts There are two external interrupts. Each interrupt has 2 input pins that can be used to trigger the interrupt. The inputs have a pulse catcher that can detect rising, falling or either rising or falling edges. INT1A [PE1] pulse catcher INT1B [PE5] pulse catcher #1 interrupt acknowledge INT0A [PE0] pulse catcher INT0B [PE4] pulse catcher #0 interrupt acknowledge Figure 7-6. External Interrupt Line Logic The external interrupts take place on a transition of the input, which is programmable for rising, falling or both edges. The pulse catchers are programmable separately to detect a rising, falling, or either edge in the input. Each of the interrupt pins has its own catcher device to catch the edge transition and request the interrupt. When the interrupt takes place, both pulse catchers associated with that interrupt are automatically reset. If both edges are detected before the corresponding interrupt takes place, because the triggering edges occur nearly simultaneously or because the interrupts are inhibited by the processor priority, then there will be only one interrupt for the two edges detected. The interrupt service routine can read the interrupt pins via Parallel Port E and determine which lines experienced a transition, provided that the transitions are not too fast. Interrupts can also be generated by setting up the matching port E bit as an output and toggling the bit. External interrupts are cleared automatically during the processor Interrupt Acknowledge cycle. The Interrupt Acknowledge cycle will always immediately follow an Instruction Fetch 1 cycle. This instruction byte is ignored, and will be the first byte fetched upon returning from the interrupt. Interrupt Acknowledge cycles are always followed by two memory writes to push the contents of the PC onto the stack. Execution then begins at the appropriate interrupt vector location. Users Manual 99 Table 7-16. Control Registers for External Interrupts Reg Name I0CR I1CR Reg Address 10011000 10011001 xx xx Bits 7,6 Bits 5,4 INT0B PE4 INT1B PE5 edge triggered 00-disabled 10-rising 01-falling 11-both Bits 3,2 INT0A PE0 INT1A PE1 edge triggered 00-disabled 10-rising 01-falling 11-both Bits 1,0 Enb INT0 Enb INT1 interrupt 00-disable 01-pri 1 10-pri 2 11-pri 3 7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 When it is desired to expand the number of interrupts for additional peripheral devices, the user should use the interrupt routine to dispatch interrupts to other virtual interrupt routines. Each additional interrupting device will have to signal the processor that it is requesting an interrupt. A separate signal line is needed for each device so that the processor can determine which devices are requesting an interrupt. The following code shows how the interrupt service routines can be written. ; External interrupt Routine #0 (programmed priority could be 3) int2: PUSH IP ; save interrupt priority IPSET 1 ; set to priority really desired (1, 2, etc.) ; insert body of interrupt routine here ; OPP IP ; get back entry priority IPRES ; restore interrupted routines priority RET ; return from interrupt 100 Rabbit 3000 Microprocessor 7.11 Bootstrap Operation The device provides the option of bootstrap from any of three sources: from the Slave Port, from Serial Port A in clocked serial mode, or from Serial Port A in asynchronous mode. This is controlled by the state of the SMODE pins after reset. Bootstrap operation is disabled if (SMODE1, SMODE0) = (0, 0). Bootstrap operation inhibits the normal fetch of code from memory, and instead substitutes the output of a small internal boot ROM for program fetches. This bootstrap program reads groups of three bytes from the selected peripheral device. The first byte is the most significant byte of a 16-bit address, followed by the least-significant byte of a 16-bit address, followed by a byte of data. The bootstrap program then writes the byte of data to the downloaded address and jumps back to the start of the bootstrap program. The most significant bit of the address is used to determine the destination for the byte of data. If this bit is zero, the byte is written to the memory location addressed by the downloaded address. If this bit is one, the byte is written to the internal peripheral addressed by the downloaded address. Note that all of the memory control signals continue to operate normally during bootstrap. Execution of the bootstrap program automatically waits for data to become available from the selected peripheral, and each byte transferred automatically resets the watchdog timer. However, the watchdog timer still operates, and bytes must be transferred often enough to prevent the watchdog timer from timing out. Bootstrap operation is terminated when the SMODE pins are set to zero. The SMODE pins are sampled just prior to fetching the first instruction of the bootstrap program. If the SMODE pins are zero, instructions are fetched from normal memory starting at address 0x0000. The Slave Port Control register allows the bootstrap operation to be terminated remotely. Writing a one to bit 7 of this register causes the bootstrap operation to terminate immediately. So the sequence 0x80, 0x24, and 0x80 will terminate bootstrap operation. Bootstrap operation is not restricted to the time immediately after reset because the boot ROM is addressed by only the four least significant bits of the address. So any time that the address ends in four zeros, if the SMODE pins are non-zero and bit 7 of the SPCR is zero, the bootstrap program will begin execution. This allows in-line downloading from the selected bootstrap port. Upon completion of the bootstrap operation, either by returning the SMODE pins to zero or setting the bit in the SPCR, execution will continue from where it was interrupted for the bootstrap operation. The Slave Port is selected for bootstrap operation when (SMODE1, SMODE0) = (0, 1). In this case the pins of Parallel Port A are used for a byte-wide data bus, and selected pins of Parallel Ports B and E are used for the Slave Port control signals. Only Slave Port Data Register 0 is used for bootstrap operation, and any writes to the other data registers will be ignored by the processor, and can actually interfere with the bootstrap operation by masking the Write Empty signal. Users Manual 101 Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE = 10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B is used for the serial clock. Note that the serial clock must be externally supplied for bootstrap operation. This precludes the use of a serial EEPROM for bootstrap operation. Serial Port A is selected for bootstrap operation as an asynchronous serial port when SMODE = 11. In this case bit 7 of Parallel Port C is used for the serial data, and the 32 kHz oscillator is used to provide the serial clock. A dedicated divide circuit allows the use of the 32 kHz signal to provide the timing reference for the 2400 bps asynchronous transfer. Only 2400 bps is supported for bootstrap operation, and the serial data must be eight bits for proper operation. In the case of asynchronous bootstrap, Serial Port A accepts either regular NRZ data or IrDA-encoded data (RZI coding with 3/16ths bit cell) automatically. The hardware contians a monostable multivibrator triggered by the falling edge of serial data into the data path. The one shot stretches any IrDA-encoded pulses enough to look like NRZ data, but not so much as to interfere with real NRZ data. When a bootstrap is performed using Serial Port A, the TXA signal is not needed since the bootstrap is a one-way communication. After the reset ends and the bootstrap mode begins, TXA will be low, reflecting its function as a parallel port output bit that is cleared by the reset. This may be interpreted as a break signal by some serial communication devices. TXA can be forced high by sending the triplet 0x80, 0x50, 0x40, which stores 0x40 in Parallel Port C. An alternate approach is to send the triplet 0x80, 0x55, 0x40, which will enable the TXA output from bit 6 of Parallel Port C by writing to the Parallel Port C function register (0x55). The transfer rate in any bootstrap operation must not be too fast for the processor to execute the instruction stream. The Write Empty signal acts as an interlock when using the Slave Port for bootstrap operation, because the next byte should not be written to the Slave Port until the Write Empty signal is active. No such interlock exists for the clocked serial and asynchronous bootstrap operation. In these cases, remember that the processor clock starts out in divide-by-eight mode with four wait states, and limit the transfer rate accordingly. In asynchronous mode at 2400 bps it takes about 4 ms to send each character, so no problem is likely unless the system clock is extremely slow. 102 Rabbit 3000 Microprocessor 7.12 Pulse Width Modulator The Pulse Width Modulator consists of a ten-bit free running counter, and four width registers. Each PWM output is High for "n + 1" counts out of the 1024-clock count cycle, where "n" is the value held in the width register. The PWM output High time can optionally be spread throughout the cycle to reduce ripple on the externally filtered PWM output. The PWM is clocked by the output of Timer A9. Register Name PWM LSB 0 Register PWM MSB 0 Register PWM LSB 1 Register PWM MSB 1 Register PWM LSB 2 Register PWM MSB 2 Register PWM LSB 3 Register PWM MSB 3 Register Mnemonic PWL0R PWM0R PWL1R PWM1R PWL2R PWM2R PWL3R PWM3R I/O Address 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F W W W W W W W W R/W Reset xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx The spreading function is implemented by dividing each 1024-clock cycle into four quadrants of 256 clocks each. Within each quadrant, the Pulse Width Modulator uses the eight MSBs of each pulse-width register to select the base width in each of the quadrants. This is the equivalent to dividing the contents of the pulse-width register by four and using this value in each quadrant. To get the exact High time, the Pulse Width Modulator uses the two LSBs of the pulse-width register to modify the High time in each quadrant according to the table below. The "n/4" term is the base count, formed from the eight MSBs of the pulse-width register. Pulse Width LSBs 00 01 10 11 1st n/4 + 1 n/4 + 1 n/4 + 1 n/4 + 1 n/4 n/4 n/4 + 1 n/4 + 1 2nd n/4 n/4 + 1 n/4 + 1 n/4 + 1 3rd n/4 n/4 n/4 n/4 + 1 4th The diagram below shows a PWM output for several different width values, for both modes of operation. Operation in the spread mode reduces the filtering requirements on the PWM output in most cases. Users Manual 103 n=255, normal (256 counts) n=255, spread (64 counts) (64 counts) (64 counts) (64 counts) n=256, spread (65 counts) (64 counts) (64 counts) (64 counts) n=257, spread (65 counts) (64 counts) (65 counts) (64 counts) n=258, spread (65 counts) (65 counts) (65 counts) (64 counts) n=259, spread (65 counts) (65 counts) (65 counts) (65 counts) n=259, normal (260 counts) Table 7-17. PWM LSB x Register PWM LSB x Register (PWL0R) (PWL1R) (PWL2R) (PWL3R) Description The least significant two bits for the Pulse Width Modulator count are stored. These bits are ignored. 0 1 PWM output High for single block. Spread PWM output throughout the cycle. (Address = 0x88) (Address = 0x8A) (Address = 0x8C) (Address = 0x8E) Bit(s) 7:6 5:1 0 Value write Table 7-18. PWM MSB x Register PWM MSB x Register (PWM0R) (PWM1R) (PWM2R) (PWM3R) Description The most significant eight bits for the Pulse Width Modulator count are stored. With a count of "n", the PWM output will be High for "n + 1" clocks out of the 1024 clocks of the PWM counter. (Address = 0x89) (Address = 0x8B) (Address = 0x8D) (Address = 0x8F) Bit(s) 7:0 Value write 104 Rabbit 3000 Microprocessor 7.13 Input Capture The two-channel Input Capture can be used to time input signals from various port pins. Each Input Capture channel consists of a sixteen-bit counter that is clocked by the output of Timer A8, and can be connected to one or two out of sixteen parallel port pins. The Input Capture channel captures the state of its counter upon either of two programmed conditions and can then generate an interrupt. The programmed conditions can also be used to start and stop the counter. Register Name Input Capture Ctrl/Status Register Input Capture Control Register Input Capture Trigger 1 Register Input Capture Source 1 Register Input Capture LSB 1 Register Input Capture MSB 1 Register Input Capture Trigger 2 Register Input Capture Source 2 Register Input Capture LSB 2 Register Input Capture MSB 2 Register Mnemonic ICCSR ICCR ICT1R ICS1R ICL1R ICM1R ICT2R ICS2R ICL2R ICM2R I/O Address 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F R/W R/W W W W R R W W R R Reset 00000000 xxxxxx00 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx Because the Input Capture channels synchronize their inputs to the peripheral clock (further divided by Timer A8), there is some delay between the input transition and when an interrupt is requested, as shown below. The status bits in the ICSxR are set coincident with the interrupt request and are reset when read from the ICSxR. Peri Clock Timer A8 CPT input Interrupt Each Input Capture channel has two inputs, called the Start condition and the Stop condition. Each of these two inputs can be programmed to come from one of four bits (bits 1, 3, 5 or 7) in Parallel Port C, D, F or G. The two inputs can come from the same or different pins, and are edge-sensitive. Each input can be disabled, rising-edge-sensitive, fallingedge-sensitive or responsive to either edge polarity. Either or both inputs can generate an Input Capture interrupt, and either or both inputs can cause the current count to be latched. Users Manual 105 Each Input Capture counter operates in one of three modes, or can be disabled. The counter is never automatically reset, but must be reset by a software command. Although it does not generate an interrupt, there is a status bit which is set when the counter overflows (counts from 0xFFFF to 0x0000) so that software can recognize this condition. To prevent potential stale-data problems, whenever the LSB of the latched count is read from the ICLxR, the corresponding MSB of the latched count is transferred to a holding register until read from the ICMxR. In the first mode the counter starts counting at the Start condition and stops counting at the Stop condition. This mode is useful for pulse width measurement if the Start condition and Stop condition are assigned to the same pin. The Input Capture inputs were chosen to take maximum advantage of this mode, to allow baud-rate detection for the serial ports and rotational speed measurement for the Quadrature Decoder channels. Using this mode with different inputs for the Start and Stop condition allows time-delay measurements between two signals. This is the mode to use for high-speed pulse measurement, because only one count latch is available, and it may be overwritten if the processor is not able to read the latched value quickly enough. When the counter starts from a known count only the stop count is necessary to determine the pulse width. In the second mode the counter runs continuously and the Start and Stop conditions merely latch the current count. This mode is useful for time-stamping the input conditions against the time reference of the counter. If the time-stamp feature is not needed, this mode gives the Rabbit 3000 up to four more external interrupt inputs. This mode works well for slower-speed pulse measurement, where the processor has enough time to read the count latched by the Start condition before the Stop condition occurs and latches a new count. In the third mode the counter runs continuously until the Stop condition occurs. This mode measures the time from the software-defined counter start until the Stop condition occurs on an input. Note that once the counter stops because of the Stop condition, it will not resume counting until re-enabled by software. 106 Rabbit 3000 Microprocessor Table 7-19. Input Capture Control/Status Register Input Capture Control/Status Register Bit(s) 7:2 (read) 7 (read) 7 (write) 6 (read) 6 (write) 5 (read) 5 (write) 4 (read) 4 (write) 3 (read) 3 (write) 2 (read) 2 (write) 1:0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0x x0 11 Value (ICCSR) Description These status bits (but not the interrupt enable bits) are cleared by the read of this register, as is the Input Capture Interrupt. The Input Capture 2 Start condition has not occurred. The Input Capture 2 Start condition has occurred. The corresponding Input Capture 2 Start interrupt is disabled. The corresponding Input Capture 2 Start interrupt is enabled. The Input Capture 2 Stop condition has not occurred. The Input Capture 2 Stop condition has occurred. The corresponding Input Capture 2 Stop interrupt is disabled. The corresponding Input Capture 2 Stop interrupt is enabled. The Input Capture 1 Start condition has not occurred. The Input Capture 1 Start condition has occurred. The corresponding Input Capture 1 Start interrupt is disabled. The corresponding Input Capture 1 Start interrupt is enabled. The Input Capture 1 Stop condition has not occurred. The Input Capture 1 Stop condition has occurred. The corresponding Input Capture 1 Stop interrupt is disabled. The corresponding Input Capture 1 Stop interrupt is enabled. The Input Capture 2 counter has not rolled over to all zeros. The Input Capture 2 counter has rolled over to all zeros. No effect on Input Capture 2 counter. This bit always reads as zero. Reset Input Capture 2 counter to all zeros and clears the rollover latch. The Input Capture 1 counter has not rolled over to all zeros. The Input Capture 1 counter has rolled over to all zeros. No effect on Input Capture 1 counter. This bit always reads as zero. Reset Input Capture 1 counter to all zeros and clears the rollover latch. Normal Input Capture operation. Normal Input Capture operation. Reserved for test. The Input Capture counter increments at both bit 0 and bit 8. There is no carry from lower byte to higher byte. (Address = 0x56) Users Manual 107 Table 7-20. Input Capture Control Register Input Capture Control Register Bit(s) 7:2 1:0 00 01 10 11 Value These bits are ignored. Input Capture interrupts are disabled. Input Capture interrupt use Interrupt Priority 1. Input Capture interrupt use Interrupt Priority 2. Input Capture interrupt use Interrupt Priority 3. (ICCR) Description (Address = 0x57) Table 7-21. Input Capture Trigger x Register Input Capture Trigger x Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11 Disable the counter. The counter runs from the Start condition until the Stop condition. The counter runs continuously. The counter runs continuously, until the Stop condition. Disable the count latching function. Latch the count on the Stop condition only. Latch the count on the Start condition only. Latch the count on either the Start or Stop condition. Ignore the starting input. The Start condition is the rising edge of the starting input. The Start condition is the falling edge of the starting input. The Start condition is either edge of the starting input. Ignore the ending input. The Stop condition is the rising edge of the ending input. The Stop condition is the falling edge of the ending input. The Stop condition is either edge of the ending input. (ICT1R) (ICT2R) Description (Address = 0x58) (Address = 0x5C) 108 Rabbit 3000 Microprocessor Table 7-22. Input Capture Source x Register Input Capture Source x Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11 (ICS1R) (ICS2R) Description Parallel Port C used for Start condition input. Parallel Port D used for Start condition input. Parallel Port F used for Start condition input. Parallel Port G used for Start condition input. Use port bit 1 for Start condition input. Use port bit 3 for Start condition input. Use port bit 5 for Start condition input. Use port bit 7 for Start condition input. Parallel Port C used for Stop condition input. Parallel Port D used for Stop condition input. Parallel Port F used for Stop condition input. Parallel Port G used for Stop condition input. Use port bit 1 for Stop condition input. Use port bit 3 for Stop condition input. Use port bit 5 for Stop condition input. Use port bit 7 for Stop condition input. (Address = 0x59) (Address = 0x5D) Table 7-23. Input Capture LSB x Register Input Capture LSB x Register Bit(s) 7:0 Value read (ICL1R) (ICL2R) Description The least significant eight bits of the latched Input Capture count are returned. Reading the lsb of the count latches the msb of the count to avoid reading stale data. Reading the msb of the count opens the latches. (Address = 0x5A) (Address = 0x5E) Table 7-24. Input Capture MSB x Register Input Capture MSB x Register (ICM1R) (ICM2R) Description The most significant eight bits of the latched Input capture count are returned. 109 (Address = 0x5B) (Address = 0x5F) Bit(s) 7:0 Users Manual Value read 7.14 Quadrature Decoder The two-channel Quadrature Decoder accepts inputs, via Port F, from two external optical incremental encoder modules. Each channel of the Quadrature Decoder accepts an inphase (I) and a quadrature-phase (Q) signal and provides 8-bit counters to track shaft rotation and provide interrupts when the count goes from 0x00 to 0xFF or from 0xFF to 0x00. The Quadrature Decoder contains digital filters on the inputs to prevent false counts. The Quadrature Decoder is clocked by the output of Timer A10. Register Name Quad Decode Ctrl/Status Register Quad Decode Control Register Quad Decode Count 1 Register Quad Decode Count 2 Register Mnemonic QDCSR QDCR QDC1R QDC2R I/O Address 0x90 0x91 0x94 0x96 R/W R/W W R R Reset xxxxxxxx 00xx0000 xxxxxxxx xxxxxxxx Each Quadrature Decoder channel accepts inputs from either the upper nibble or lower nibble of Port F. The I signal is input on an odd-numbered port bit, while the Q signal is input on an even-numbered port bit. There is also a disable selection, which is guaranteed not to generate a count increment or decrement on either entering or exiting the disable state. The operation of the counter as a function of the I and Q inputs is shown below. I input Q input Counter 00 01 02 03 04 05 06 07 08 07 06 05 04 03 02 01 00 FF Interrupt The Quadrature decoders are clocked by the output of Timer A10, giving a maximum clock rate of one-half of the peripheral clock rate. The time constant of Timer A10 must be fast enough to sample the inputs properly. Both the I and Q inputs go through a digital filter that rejects pulses shorter than two clock period wide. In addition, the clock rate must be High enough that transitions on the I and Q inputs are sampled in different clock cycles. The Input Capture may be used to measure the pulse width on the I inputs because they come from the odd-numbered port bits. The operation of the digital filter is shown below. 110 Rabbit 3000 Microprocessor Peri Clock Timer A10 Rejected Accepted The Quadrature Decoder generates an interrupt when the counter increments from 0xFF to 0x00 or when the counter decrements from 0x00 to 0xFF. The timing for the interrupt is shown below. Note that the status bits in the QDCSR are set coincident with the interrupt, and the interrupt (and status bits) are cleared by reading the QDCSR. Users Manual 111 Table 7-25. Quadrature Decoder Control/Status Register Quad Decode Control/Status Register Bit(s) 7 (read-only) 6 (read-only) 5 4 (write-only) 3 (read-only) 2 (read-only) 1 0 (write-only) 0 1 0 1 0 1 0 1 Value 0 1 0 1 (QDCSR) Description Quadrature Decoder 2 did not increment from 0xFF. Quadrature Decoder 2 incremented from 0xFF to 0x00. This bit is cleared by a read of his register. Quadrature Decoder 2 did not decrement from 0x00. Quadrature Decoder 2 decremented from 0x00 to 0xFF. This bit is cleared by a read of this register. This bit always reads as zero. No effect on the Quadrature Decoder 2. Reset Quadrature Decoder 2 to 0x00 without causing an interrupt. Quadrature Decoder 1 did not increment from 0xFF. Quadrature Decoder 1 incremented from 0xFF to 0x00. This bit is cleared by a read of this register. Quadrature Decoder 1 did not decrement from 0x00. Quadrature Decoder 1 decremented from 0x00 to 0xFF. This bit is cleared by a read of this register. This bit always reads as zero. No effect on the Quadrature Decoder 1. Reset Quadrature Decoder 1 to 0x00 without causing an interrupt. (Address = 0x90) 112 Rabbit 3000 Microprocessor Table 7-26. Quadrature Decoder Control Register Quad Decode Control Register Bit(s) Value 00 7:6 01 10 11 5:4 00 3:2 01 10 11 00 01 1:0 10 11 Quadrature Decoder interrupt use Interrupt Priority 2. Quadrature Decoder interrupt use Interrupt Priority 3. (QDCR) Description Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. This bit combination is reserved and should not be used. Quadrature Decoder 2 inputs from Port F bits 3 and 2. Quadrature Decoder 2 inputs from Port F bits 7 and 6. These bits are ignored. Disable Quadrature Decoder 1 inputs. Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement. This bit combination is reserved and should not be used. Quadrature Decoder 1 inputs from Port F bits 1 and 0. Quadrature Decoder 1 inputs from Port F bits 5 and 4. Quadrature Decoder interrupts are disabled. Quadrature Decoder interrupt use Interrupt Priority 1. (Address = 0x91) Table 7-27. Quadrature Decoder Count Register Quad Decode Count Register Bit(s) 7:0 Value read (QDC1R) (QDC2R) Description The current value of the Quadrature Decoder counter is reported. (Address = 0x94) (Address = 0x96) Users Manual 113 114 Rabbit 3000 Microprocessor 8. MEMORY INTERFACE AND MAPPING 8.1 Interface for Static Memory Chips Static memory chips generally have address lines, data line, a chip select line, an output enable line and a write enable. The Rabbit 3000 has these same lines that can connect directly to a number of static memory chips. The chip selects are not completely interchangeable because certain chip selects have special functions. When the processor starts up, not in cold boot mode, execution starts at address zero in the memory attached to /CS0. A static RAM should be connected to /CS1 because Dynamic C development tools assume a static RAM connected to /CS1. In addition /CS1 has special features that support battery backing of static RAM. When the processor power is removed but battery power is supplied to the battery power pin (VBAT) /CS1 is held in a high impedance state. This allows a pull up resistor to the battery backup power to hold /CS1 high and thus hold the static memory chip in standby mode. The RESOUT pin is also held high while the processor is powered down and battery power is supplied to VBAT. This allows the RESOUT pin to be used to control power to the processor and the static RAM chip via a transistor. It is also possible to force /CS1 to be enabled at all times. This is convenient if an external battery backup device is used that might slow down the transition of /CS1 during the memory cycle. Most users will not use this feature. 3.3 V FDV302P Main Power (p channel) 5 kW 3V 100 kW Rabbit 3000 /CS /CS Rabbit 3000 VBAT SRAM VDD Rabbit 3000 RESOUT Figure 8-1. Battery-Backup Circuit Users Manual 115 DATA LINES (8) Rabbit 3000 ADDRESS LINES (20) STATIC MEMORY FLASH /CS /CS0 /CS1 /CS2 /OE0 /OE1 /WE0 /WE1 /OE /WE STATIC MEMORY RAM /CS /OE /WE Figure 8-2. Typical Memory Chip Connection 116 Rabbit 3000 Microprocessor 8.2 Memory Mapping Overview See Section 3.2, Memory Mapping, for a discussion of Rabbit memory mapping. Figure 8-3 shows an overview of the Rabbit memory mapping. The task of the memory mapping unit is to accept 16-bit addresses and translate them to 20-bit addresses. The memory interface unit accepts the 20-bit addresses and generates control signals applied directly to the memory chips. Processor Memory Mapping Unit Memory Interface Unit Memory Chips Figure 8-3. Overview of Rabbit Memory Mapping 8.3 Memory-Mapping Unit The 64K 16-bit address space accessed by processor instructions is divided into segments. Each segment has a length that is a multiple of 4K. Except for the extended code segment, the segments have adjustable sizes and some segments can be reduced to zero size and thus vanish from the memory map. The four segments are shown in the example in Figure 8-4. The segment size register (SEGSIZE) determines the boundaries marked in the diagram. The extended code segment always occupies the addresses 0x0E0000x0FFFF. The stack segment stretches from the address specified by the upper 4 bits of the SEGSIZE register to 0x0DFFF. For example, if the upper 4 bits of SEGSIZE are 0x0D, then the stack segment will occupy 0x0D0000x0DFFF, or 4K. If the upper 4 bits of SEGSIZE are greater than or equal to 0x0E, the stack segment vanishes. If these bits are set to zero, the two segments below the stack segment will vanish. The lower 4 bits of SEGSIZE determine the lower boundary shown in the figure. If this boundary is equal to the upper boundary or greater than 0x0E, the data segment will vanish. If this segment is placed at zero the code segment will vanish. Users Manual 117 64K Extended code XPC segment (8K) Stack segment (4K typ) Data segment Boundary SEGSIZE[4..7] Boundary SEGSIZE[0..3] XPC STACKSEG DATASEG 00 + 16-bit address 20-bit address Figure 8-4. Memory Segments Root segment 0K The memory management unit accepts a 16-bit address from the processor and translates it into a 20-bit address. The procedure to do this works as follows. 1. It is determined which segment the 16-bit address belongs to by inspecting the upper 4 bits of the address. Every address must belong to one of the possible 4 segments. 2. Each segment has an 8-bit segment register. The 8-bit segment register is added to the upper 4 bits of the 16-bit address to create a 20-bit address. Wraparound occurs if the addition would result in an address that does not fit in 20 bits. Table 8-1. Segment Registers Segment Register XPC STACKSEG = 0x11 DATASEG = 0x12 Function Locates extended code segment in physical memory. Read and written by processor instructions: ld a,xpc, ld xpc,a, lcall, lret, ljp Locates stack segment in physical memory. Locates data segment in physical memory. Table 8-2. Segment Size Register Bits 7..4 SEGSIZE = 0x13 Boundary address stack segment. Bits 3..0 Boundary address data segment. 118 Rabbit 3000 Microprocessor 8.4 Memory Interface Unit The 20-bit memory addresses generated by the memory-mapping unit feed into the memory interface unit. The memory interface unit has a separate write-only control register for each 256K quadrant of the 1M physical memory. This control register specifies how memory access requests to that quadrant are to be dispatched to the memory chips connected to the Rabbit. There are three separate chip select output lines (/CS0, /CS1, and /CS2) that can be used to select one of three different memory chips. A field in the control register determines which chip select is selected for memory accesses to the quadrant. The same chip select line may be accessed in more than one quadrant. For example, if a 512K RAM is installed and is selected by /CS1, it would be appropriate to use /CS1 for accesses to the 3rd and 4th quadrants, thus mapping the RAM chip to addresses 0x80000 to 0x0FFFFF. Users Manual 119 8.5 Memory Bank Control Registers Table 8-3 describes the operation of the four memory bank control registers. The registers are write-only. Each register controls one quadrant in the 1M address space. Table 8-3. Memory Bank Control Register x (MBxCR = 0x014 + x) Memory Bank x Control Register (MB0CR) (MB1CR) (MB2CR) (MB3CR) Description Four wait states for accesses in this bank. Two wait states for accesses in this bank. One wait states for accesses in this bank. Zero wait states for accesses in this bank. Pass A[19] for accesses in this bank. Invert A[19] for accesses in this bank. Pass A[18] for accesses in this bank. Invert A[18] for accesses in this bank. /OE0 and /WE0 are active for accesses in this bank /OE1 and /WE1 are active for accesses in this bank /OE0 only is active for accesses in this bank (i.e. read-only). Transactions are normal in every other way. /OE1 only is active for accesses in this bank (i.e. read-only). Transactions are normal in every other way. /CS0 is active for accesses in this bank. /CS1 is active for accesses in this bank. /CS2 is active for accesses in this bank. (Address = 0x014) (Address = 0x015) (Address = 0x016) (Address = 0x017) Bit(s) Value 00 01 7:6 10 11 0 5 1 0 4 1 00 01 3:2 10 11 00 1:0 01 1x Bits 7,6The number of wait states used in access to this quadrant. Without wait states, read requires 2 clocks and write requires 3 clocks. The wait state adds to these numbers. Wait states should only be used for memory data accesses (RAM or data flash), not for memory from which instructions are executed (code memory). Bits 5, 4These bits allow the upper address lines to be inverted. This inversion occurs after the logic that selects the bank register, so setting these lines has no effect on which bank register is used. The inversion may be used to install a 1M memory chip in the space normally allocated to a 256K chip. The larger memory can then be accessed as 4 pages of 256K each. There is no effect outside the quadrant that the memory bank control register is controlling. 120 Rabbit 3000 Microprocessor Bit 3Inhibits the write pulse to memory accessed in this quadrant. Useful for protecting flash memory from an inadvertent write pulse, which will not actually write to the flash because it is protected by lock codes, but will temporarily disable the flash memory and crash the system if the memory is used for code. Bit 2Selects which set of the two lines /OEx and /WEx will be driven for memory accesses in this quadrant. Bits 1,0Determines which of the three chip select lines will be driven for memory accesses to this quadrant. All bits of the control register are initialized to zero on reset. 8.5.1 Optional A16, A19 Inversions by Segment (/CS1 Enable) The inversion of A19 or A16 controlled by the read/write MMIDR register is used to redirect mapping of the root segment and the data segment by inverting certain bits when these segments are accessed. The optional enable of /CS1 is valuable for systems that are pushing the access time of battery-backed RAM. By enabling /CS1, the delay time of the switch that forces /CS1 high when power is off can be bypassed. This feature increases power consumption since the RAM is always enabled and its access is controlled normally by /OE1. Table 8-4. MMU Instruction/Data Register (MMIDR = 0x010) * MMU Instruction/Data Register Bit(s) 7:6 Value 00 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 1 For root access, invert A16 * See Table B-20 for information on bit 7 for Rabbit 3000A and later versions. For root access, invert A19 before MBxCR (bank select) decision. Normal operation. For a DATASEG access: invert A16 Normal operation. For a DATASEG access, invert A19 before MBxCR (bank select) decision. Normal operation. (MMIDR) Description These bits are ignored and always return zeros when read. Enable A16 and A19 inversion independent of instruction/data. Enable A16 and A19 inversion (controlled by bits 03) for data accesses only. This enables the instruction/data split. This is separate I and D space. Normal /CS1 operation. Force /CS1 always active. This will not cause any conflicts as long as the memory using /CS1 does not also share an Output Enable or Write Enable with another memory. Normal operation. (Address = 0x010) Users Manual 121 Table 8-5. MMU Expanded Code Register (MECR = 0x018) MMU Expanded Code Register Bit(s) 7:3 0xx 100 2:0 101 110 111 Value (MECR) Description These bits are ignored for write, and return zeros when read. Normal operation. For an XPC access, use MB0CR independent of A19-A18. For an XPC access, use MB1CR independent of A19-A18. For an XPC access, use MB2CR independent of A19-A18. For an XPC access, use MB3CR independent of A19-A18. (Address = 0x018) The Memory Timing Control Register (MTCR) enables the extended timing for the memory output enables and write enables. See Figure 7-2 for details on how the timing of the memory read and write strobes is affected when using the early output enable and write enable options. Figure 16-3 shows extended output enable and write enable timing diagrams. Table 8-6. Memory Timing Control Register (MTCR, adr = 0x019) Memory Timing Control Register Bit(s) 7:4 3 Value xxxx 0 1 2 0 1 1 0 1 0 0 1 (MTCR) Description These bits are reserved and should not be used. Normal timing for /OE1B (rising edge to rising edge, one clock minimum). Extended timing for /OE1B (one-half clock earlier than normal). Normal timing for /OE0B (rising edge to rising edge, one clock minimum). Extended timing for /OE0B (one-half clock earlier than normal). Normal timing for /WE1B (rising edge to falling edge, one and one-half clocks minimum). Extended timing for /WE1B (falling edge to falling edge, two clocks minimum). Normal timing for /WE0B (rising edge to falling edge, one and one-half clocks minimum). Extended timing for /WE0B (falling edge to falling edge, two clocks minimum). (Address = 0x019) 122 Rabbit 3000 Microprocessor The Breakpoint/Debug controller allows the RST 28 instruction to be used as a software breakpoint. Normally the RST 28 instruction causes a call to a particular location in memory, but the operation of this instruction is modified when the breakpoint/debug feature is enabled. The RST 28 instruction is treated as a NOP in the breakpoint/debug mode. Table 8-7. Breakpoint/Debug Control Register (BDCR, adr = 0x01C ) Breakpoint/Debug Control Register Bit(s) 7 Value 0 1 6:0 Normal RST 28 operation. RST 28 is NOP. These bits are reserved and should not be used. (BDCR) Description (Address = 0x01C) 8.6 Allocation of Extended Code and Data The Dynamic C compiler compiles code to root code space or to extended code space. Root code starts in low memory and compiles upward. Allocation of extended code starts above the root code and data. Allocation normally continues to the end of the flash memory. Data variables are allocated to RAM working backwards in memory. Allocation normally starts at 52K in the 64K D space and continues. The 52K space must be shared with the root code and data, and is allocated upward from zero. Dynamic C also supports extended data constants. These are mixed in with the extended code in flash. Users Manual 123 8.7 Instruction and Data Space Support Instruction and Data space (I and D space) support is accomplished by optionally inverting address lines A16 and/or A19 when the processor accesses D space, but not inverting those lines when the processor accesses I space. The MMIDR register (see Table 8-8) is used to control this inversion. It is important to understand that the bit inversion of A16 and A19 associated with I and D space occurs before the upper 2 bits of the 20-bit address are used to determine the quadrant and thus the bank register that is going to control memory access. This contrasts with the optional address bit inversion of A19 and A18 controlled by the 4 memory bank control registers (see Table 8-3) that takes place after the quadrant has been computed. Table 8-8. Use of MMIDR Register to Control Inversion of Address Lines A16 and A19 Bits 7:5 000 Bit 4 1force /CS1 always enabled Bit 3 Bit 2 Bit 1 Bit 0 1Invert A16 for 1Invert A19 for data accesses in data data accesses in data segment segment before quadrant selection 1Invert A16 for 1Invert A19 for data accesses in root data accesses in root segment. segment before quadrant selection To make this clear, lets look at an example. Suppose a 1 megabyte flash memory is controlled by /CS0, /WE0, and /OE0. Suppose this memory is accessed as part of the first quadrant and MB0CR is set up to enable /CS0 and /WE0 or /OE0 on accesses to this bank. Then if A18 and A19 are zero, the first 256K of the flash memory will be visible in the first 256K of the physical memory. If access is made to the second quadrant, the memory will not be selected unless MB1CR is mapped to the flash memory. However, if A18 is inverted by setting bit 4 in MB0CR to a 1, then the second 256K of the flash will be mapped into the first quadrant. A18 will have been inverted, but he quadrant does not change because this inversion occurs after the quadrant has been selected. The inversion of A19 or A16 controlled by the MMIDR register on D space accesses is used to separate I and D space to different memory locations. The separation of I and D space can only occur for the first two memory zones in the64K space. For each zone, the root code segment and the data segment either or both of A19 and A16 can be inverted. The reasoning behind these choices is that a normal memory map places flash memory in the lower 512K of the physical memory space. RAM memory begins at 512K. By inverting A19 on D space accesses, memory mapped to the lower 512K and held in flash will be switched to RAM for D accesses. By inverting A16, D accesses will be switched to an adjacent 64K page, which would normally still be in the lower 512K memory or flash. To see how this works consider that data are of two different typesconstants stored in flash memory and variables, which must be stored in RAM. Because there are two types of data, it is desirable to divide the D space into two zones, one for constants and one for variables, as shown in Figure 8-5. In a combined I and D space model the root code segment holds both code and data constants in flash memory. The data segment holds data variables in RAM. In the separate I and D space model, the root code segment and the data segment 124 Rabbit 3000 Microprocessor are mapped into contiguous regions of memory to create a continuous root code segment starting at the bottom of physical memory in flash. In the I space the division between the root segment and the data segment is irrelevant because the DATASEG register contains zero and the division between the segments defined by the lower 4 bits of the SEGSIZE register does not mark a division in physical memory for code space. However, if for D space accesses A16 is inverted for the root segment and A19 is inverted for the data segment, then root segment data is mapped to the next 64k of flash and data segment data is mapped to a place in memory 512K higher in the RAM. This divides the data space into two separate segments for constants and variables. If the stack segment (which is still combined I and D space) and the extended code segment (also combined I and D space) occupy 12K at the top of the 64K space, then the remaining 52K is doubled into a 52K code space in flash and a 52K data space, which may be split into two parts, one for constants and one for variables. The relative size of the two parts depends on the lower 4 bits of the SEGSIZE register, which define the 4K page boundary between the root segment and the data segment. Combined I & D 64k 52k RAM Root Code & Data (flash) Extended Code Stack Root Code I-Space D-Space Var (RAM) D-Space Const (flash) Separate I & D Allocate vars Allocate consts (4*n)k Figure 8-5. Combined versus Separate I & D Space The use of physical memory that goes with this map is shown in Figure 8-6, Use of Physical Memory Separate I & D Space Model, on page 126. In this figure "n" is the number of 4k pages devoted to D space constants. In the figure it is assumed that the lower 512k of memory is entirely composed of flash memory and the upper 512K is entirely RAM. This does not have to be the case. For example, if a low-cost 32K x 8 RAM is used and mapped to the 3rd quadrant using /CS1, the RAM memory will begin at 512K and will be repeated 8 times in the 3rd quadrant from addresses 512K to 768K. Since the memory repeats, it can be considered to start at any address and continue for 32K. At least 4K of RAM is needed for the stack segment, so if a 32K RAM is used, a maximum of 28K would be available for storing data variables. If more stack segments are needed, the amount of data variable space would be corresponding reduced. Users Manual 125 64k 0k Root I Space 52k 64k+4*n alloc xcode 512k+4*n xconsts 512k 512k+52k 1024k alloc xdata vars alloc consts Constant D Space Flash memory available for extended code, constant data. Variable D Space allocate vars Ram memory available. Figure 8-6. Use of Physical Memory Separate I & D Space Model In Figure 8-6 arrows indicate the direction in which variables and constants are allocated as the compile or assemble proceeds. Each of these arrows starts at a constant location in physical memory. This is important because the Dynamic C debugging monitor needs to keep a small number of constants and variable in data space and it needs to be able to access these regardless of the state of the user program. The Dynamic C debugger variables are kept at the top of the data segment starting at 52k and working down in memory. The user-program variables are allocated by the compiler starting just below the Dynamic C debugger data. The Dynamic C constants start at address zero. User constants are allocated stating at a low address just above the Dynamic C constants. 126 Rabbit 3000 Microprocessor 8.8 How the Compiler Compiles to Memory The compiler actually generates code for root code and constants and extended code and extended constants. It allocates space for data variables, but does not generate data bits to be stored in memory. In any but the smallest programs, most of the code is compiled to extended memory. This code executes in the 8K window from E000 to FFFF. This 8K window uses paged access. Instructions that use 16-bit addressing can jump within the page and also outside of the page to the remainder of the 64K space. Special instructions, particularly long call, long jump and long return, are used to access code outside of the 8K window. When one of these transfer of control instructions is executed, both the address and the view through the 8K window or page are changed. This allows transfer to any instruction in the 1M memory space. The 8-bit XPC register controls which of the 256 4K pages the 8K window aligns with. The 16-bit PC controls the address of the instruction, usually in the region E000 to FFFF. The advantage of paged access is that most instructions continue to use 16-bit addressing. Only when an out-of-range transfer of control is made does a 20-bit transfer of control need to be made. The beauty of having a 4K minimum step in page alignment while the size of the page is 8K is that code can be compiled continuously without gaps caused by change of page. When the page is moved by 4K, the previous end of code is still visible in the window, provided that the midpoint of the page was crossed before moving the page alignment. As the compiler compiles code in the extended code window, it checks at opportune times to see if the code has passed the midpoint of the window or F000. When the code passes F000, the compiler slides the window down by 4K so that the code at F000+x becomes resident at E000+x. This results in the code being divided into segments that are typically 4K long, but which can very short or as long as 8K. Transfer of control can be accomplished within each segment by 16-bit addressing; 20-bit addressing is required between segments. Users Manual 127 128 Rabbit 3000 Microprocessor 9. PARALLEL PORTS The Rabbit has seven 8-bit parallel ports designated A, B, C, D, E, F, and G. The pins used for the parallel ports are also shared with numerous other functions as shown in Table 5-2. The important properties of the ports are summarized below. Port AShared with the slave port data interface and auxiliary I/O data bus. Port BShared with control lines for slave port, auxiliary I/O address bus, and clock I/O for clocked serial mode option for Serial Ports A and B. Port CShared with serial port data I/O. Port D4 bits shared with alternate I/O pins for Serial Ports A and B. 4 bits not shared. Port D can be configured as open drain outputs. Port D also contains output preload registers that can be clocked into the output registers under timer control for pulse generation. Port EAll bits of Port E can be configured as I/O strobes. 4 bits of port E can be used as external interrupt inputs. One bit of port E is shared with the slave port chip select. Port E has output preload registers that can be clocked into the output registers under timer control for pulse generation. Port F As outputs, Port F can be configured as open drain outputs. Alternatively, Parallel Port F outputs can carry the four Pulse-Width Modulator outputs. As inputs, Parallel Port F inputs can carry the inputs to the two channels of the quadrature decoders. Port F pins can also be configured to be used as clock pins for clocked Serial Ports C and D. Port GAs outputs, Port G can be configured as open drain outputs. Port G inputs and outputs are also used for access to other serial peripherals on the chip such as those used for asynchronous or SDLC/HDLC communication. Parallel Ports DG behave in the same manner when used as digital I/O. NOTE: There may be a conflict in using Parallel Port A and Parallel Port F. Either Parallel Port A can be used as inputs, in which case Parallel Port F has full function, or if Parallel Port A cannot be used as inputs, use any pins on Parallel Port F not used for PWM or serial clock outputs as inputs and take the precaution of setting up Parallel Port F before the conflicting functionality of Parallel Port A is enabled. Refer to Section 9.6.1, Using Parallel Port A and Parallel Port F, for more information. Users Manual 129 9.1 Parallel Port A Parallel Port A has a single read/write register: Table 9-1. Parallel Port A Registers Register Name Port A Data Register Slave Port Control Register Mnemonic PADR SPCR I/O address 0x30 0x24 R/W R/W R/W Reset xxxxxxxx 0xx00000 Table 9-2. Parallel Port A Data Register Bit Functions Bit 7 PADR (R/W) adr = 0x030 PA7 Bit 6 PA6 Bit 5 PA5 Bit 4 PA4 Bit 3 PA3 Bit 2 PA2 Bit 1 PA1 Bit 0 PA0 This register should not be used if the slave port or auxiliary I/O bus is enabled. The slave port control register is used to control whether Parallel Port A is configured as slave databus, auxiliary I/O data bus, parallel Input or parallel output. To make the port an input, store 0x080 in the SPCR (slave port control register). To make the port an output, store 0x084 in SPCR. Parallel Port A is set up as an input port on reset. When the port is read, the value read reflects the voltages on the pins, "1" for high and "0" for low. This could be different than the value stored in the output register if the pin is forced to a different state by an external voltage. NOTE: Refer to Section 9.6.1, Using Parallel Port A and Parallel Port F, for more information. 130 Rabbit 3000 Microprocessor 9.2 Parallel Port B Parallel Port B, has eight pins that can programmed individually to be inputs and outputs. After reset, Parallel Port B comes up as six inputs (PB[5:0]) and two outputs (PB7 and PB6). The output value on pins PB6 and PB7 (package pins 99, 100) will be low. Table 9-3. Parallel Port B Registers Register Name Port B Data Register Port B Data Direction Register Mnemonic PBDR PBDDR I/O address 0x40 0x47 R/W R/W W Reset 00xxxxxx 11000000 Table 9-4. Parallel Port B Register Bit Functions Bit 7 PBDR (R/W) PB7 adr = 0x040 PBDDR dir = (W) adr = 0x047 out Bit 6 PB6 Bit 5 PB5 Bit 4 PB4 Bit 3 PB3 Bit 2 PB2 Bit 1 PB1 Bit 0 PB0 dir = out dir = out dir = out dir = out dir = out dir = out dir = out When the auxiliary I/O bus is enabled, Parallel Port B bits 2:7 provide 6 address lines, the least significant 6 lines of the 16 lines that define the full I/O space. When the slave port is enabled, parallel port lines PB2PB7 are assigned to various slave port functions. However, it is still possible to read PB0PB5 using the Port B data register even when lines PB2PB7 are used for the slave port. It is also possible to read the signal driving PB6 and PB7 (this signal is on the signaling lines from the slave port logic). Regardless of whether the slave port is enabled, PB0 reflects the input of the pin unless Serial Port B has its internal clock enabled, which causes this line to be driven by the serial port clock. PB1 reflects the input of the pin unless Serial Port A has its internal clock enabled. PBDRParallel Port B data register. Read/Write. PBDDRParallel Port B data direction register. A "1" makes the corresponding pin an output. This register is write only. Users Manual 131 9.3 Parallel Port C Parallel Port C, shown in Table 9-6, has four inputs and four outputs. The even-numbered ports, PC0, PC2, PC4, and PC6, are outputs. The odd-numbered ports, PC1, PC3, PC5, and PC7, are inputs. When the data register is read, bits 1,3,5,7 return the value of the voltage on the pin. Bits 0,2,4,6 return the value of the signal driving the output buffers. The signal driving the output buffers and the value of the output pin are normally the same. Either the Port C data register is driving these pins or one of the serial port transmit lines is driving the pin. The bits set in the PCFR Parallel Port C Function Register identify whether the data register or the serial port transmit lines were driving the pins. Table 9-5. Parallel Port C Registers Register Name Port C Data Register Port C Function Register Mnemonic PCDR PCFR I/O address 0x50 0x55 R/W R/W W Reset x0x1x1x1 x0x0x0x0 Table 9-6. Parallel Port C Register Bit Functions Bit 7 PCDR (r) adr = 0x050 PCDR (w) adr = 0x050 PCFR (w) adr = 0x055 PC7 in Bit 6 Echo drive PC6 Drive TXA Bit 5 PC5 in Bit 4 Echo drive PC4 Drive TXB Bit 3 PC3 in Bit 2 Echo drive PC2 Drive TXC Bit 1 PC1 in Bit 0 Echo drive PC0 Drive TXD x x x x x x x x Parallel Port C shares its pins with serial ports A-D. The parallel port inputs can be configured as serial port inputs while the dedicated outputs as serial port outputs. When serving as serial inputs, the data lines can still be read from the Parallel Port C data register. The parallel port outputs can be selected to be serial port outputs by setting the corresponding bit positions in the Port C Function register (PCFR). When a parallel port output pin is selected to be a serial port output, the value stored in the data register is ignored. On reset the active (even-numbered) function register bits are zeroed resulting in Port C to behave as an I/O port. Bit 6 of the Port C data register is zeroed while the remaining even numbered bits are set to 1. 132 Rabbit 3000 Microprocessor 9.4 Parallel Port D Parallel Port D, shown in Figure 9-1, has eight pins that can be programmed individually to be inputs or outputs. When programmed as outputs, the pins can be individually selected to be open-drain outputs or standard outputs. Port D pins can be addressed by bit if desired. The output registers are cascaded and timer-controlled, making it possible to generate precise timing pulses. Port D bits 4 and 5 can be used as alternate bits for Serial Port B, and bits 6 and 7 can be used as alternate bits for Serial Port A. Alternate serial port bit assignments make it possible for the same serial port to connect to different communications lines that are not operating at the same time. On reset, the data direction register is zeroed, making all pins inputs. In addition certain bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers when loaded. All other registers associated with port D are not initialized on reset. Table 9-7. Parallel Port D Registers Register Name Port D Data Register Port D Control Register Port D Function Register Port D Drive Control Register Port D Data Direction Register Port D Bit 0 Register Port D Bit 1 Register Port D Bit 2 Register Port D Bit 3 Register Port D Bit 4 Register Port D Bit 5 Register Port D Bit 6 Register Port D Bit 7 Register Mnemonic PDDR PDCR PDFR PDDCR PDDDR PDB0R PDB1R PDB2R PDB3R PDB4R PDB5R PDB6R PDB7R I/O address 0x60 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F R/W R/W W W W W W W W W W W W W Reset xxxxxxxx xx00xx00 xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Users Manual 133 ARXA PD7 PD6 ATXA ARXB PD5 PD4 ATXB inputs I/O Data perclk/2 Timer A1 Timer B1 Timer B2 Driveroptional open drain PD3 PD0 perclk/2 Timer A1 Timer B1 Timer B2 Figure 9-1. Parallel Port D Block Diagram 134 Rabbit 3000 Microprocessor Table 9-8. Parallel Port D Register functions Bit 7 PDDR (R/W) adr = 0x060 PDDCR (W) adr = 0x066 PDFR (W) adr = 0x065 PDDDR (W) adr = 0x067 PDB0R (W) adr = 0x068 PDB1R (W) adr = 0x069 PDB2R (W) adr =0x 06A PDB3R (W) adr = 0x06B PDB4R (W) adr = 0x06C PDB5R (W) adr = 0x06D PDB6R (W) adr = 0x06E PDB7R (W) adr = 0x06F PD7 out = open drain x dir = out x Bit 6 PD6 out = open drain alt TXA dir = out x Bit 5 PD5 out = open drain x dir = out x Bit 4 PD4 out = open drain alt TXB dir = out x Bit 3 PD3 out = open drain x dir = out x Bit 2 PD2 out = open drain x dir = out x Bit 1 PD1 out = open drain x dir = out x Bit 0 PD0 out = open drain x dir = out PD0 x x x x x x PD1 x x x x x x PD2 x x x x x x PD3 x x x x x x PD4 x x x x x x PD5 x x x x x x PD6 x x x x x x PD7 x x x x x x x Table 9-9. Parallel Port D Control Register (adr = 0x064) Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0 00clock lower nibble on pclk/2 01clock on timer A1 10clock on timer B1 11clock on timer B2 x,x 00clock upper nibble on pclk/2 01clock on timer A1 x,x 10clock on timer B1 11clock on timer B2 Users Manual 135 The following registers are described in Table 9-8 and in Table 9-9. PDDRParallel Port D data register. Read/Write. PDDDRParallel Port D data direction register. A "1" makes the corresponding pin an output. Write only. PDDCRParallel Port D drive control register. A "0" makes the corresponding pin a regular output. A "1" makes the corresponding pin an open-drain output. Write only. PDFRParallel Port D function control register. This port may be used to make port positions 4 and 6 be serial port outputs. Write only. PDBxRThese eight registers may be used to set outputs on individual port positions. PDCRParallel Port D control register. This register is used to control the clocking of the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4, and 5 are reset to zero. 136 Rabbit 3000 Microprocessor 9.5 Parallel Port E Parallel Port E, shown in Figure 9-2, has eight I/O pins that can be individually programmed as inputs or outputs. PE7 is used as the slave port chip select when the slave port is enabled. Each of the port E outputs can be configured as an I/O strobe. In addition, four of the port E lines can be used as interrupt request inputs. The output registers are cascaded and timer-controlled, making it possible to generate precise timing pulses. /scs PE7 I7 I6 INT1 I5 PE4 I4 INT0 Inputs I/O Data perclk/2 Timer A1 Timer B1 Timer B2 PE3 I3 I2 INT1 I1 PE0 I0 INT0 perclk/2 Timer A1 Timer B1 Timer B2 Figure 9-2. Parallel Port E Block Diagram Users Manual 137 Table 9-10. Parallel Port E Registers Register Name Port E Data Register Port E Control Register Port E Function Register Port E Data Direction Register Port E Bit 0 Register Port E Bit 1 Register Port E Bit 2 Register Port E Bit 3 Register Port E Bit 4 Register Port E Bit 5 Register Port E Bit 6 Register Port E Bit 7 Register Mnemonic PEDR PECR PEFR PEDDR PEB0R PEB1R PEB2R PEB3R PEB4R PEB5R PEB6R PEB7R I/O address 0x70 0x74 0x75 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F R/W R/W W W W W W W W W W W W Reset xxxxxxxx xx00xx00 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx The following registers are described in Table 9-11 and in Table 9-12. PEDRPort E data register. Reads value at pins. Writes to port E preload register. PEDDRPort E data direction register. Set to "1" to make corresponding pin an output. This register is zeroed on reset. PEFRPort E function register. Set bit to "1" to make corresponding output an I/O strobe. The nature of the I/O strobe is controlled by the I/O bank control registers (IBxCR). The data direction must be set to output for the I/O strobe to work. PEBxRThese are individual registers to set individual output bits on or off. PECRParallel Port E control register. This register is used to control the clocking of the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4, and 5 are reset to zero. On reset, the data direction register and function register are zeroed, making all pins inputs, and disabling the alternate output functions. In addition certain bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers when loaded. All other registers associated with Port E are not initialized on reset. 138 Rabbit 3000 Microprocessor Table 9-11. Parallel Port E Register functions Bit 7 PEDR (R/W) adr = 0x070 PEFR (W) adr = 0x075 PEDDR (W) adr = 0x077 PEB0R (W) adr = 0x078 PEB1R (W) adr = 0x079 PEB2R (W) adr = 0x07A PEB3R (W) adr = 0x07B PEB4R (W) adr = 0x07C PEB5R (W) adr = 0x07D PEB6R (W) adr = 0x07E PEB7R (W) adr = 0x07F PE7 Bit 6 PE6 Bit 5 PE5 Bit 4 PE4 Bit 3 PE3 Bit 2 PE2 Bit 1 PE1 Bit 0 PE0 alt /I7 dir = out x alt /I6 dir = out x alt /I5 dir = out x alt /I4 dir = out x alt /I3 dir = out x alt /I2 dir = out x alt /I1 dir = out x alt /I0 dir = out PE0 x x x x x x PE1 x x x x x x PE2 x x x x x x PE3 x x x x x x PE4 x x x x x x PE5 x x x x x x PE6 x x x x x x PE7 x x x x x x x Table 9-12. Parallel Port E Control Register (adr = 0x074) Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0 00clock lower nibble on pclk/2 01clock on timer A1 10clock on timer B1 11clock on timer B2 x,x 00clock upper nibble on pclk/2 01clock on timer A1 x,x 10clock on timer B1 11clock on timer B2 Users Manual 139 9.6 Parallel Port F Parallel Port F is a byte-wide port with each bit programmable for data direction and drive. These are simple inputs and outputs controlled and reported in the Port F Data Register. As outputs, the bits of the port are buffered, with the data written to the Port F Data Register transferred to the output pins on a selected timing edge. The outputs of Timer A1, Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a separate select field to control this timing. These inputs and outputs are also used for access to other peripherals on the chip. As outputs, the Parallel Port F outputs can carry the four Pulse-Width Modulator outputs. As inputs, Parallel Port F inputs can carry the inputs to the quadrature decoders. When Serial Port C or Serial Port D is used in the clocked serial mode, two pins of Parallel Port F are used to carry the serial clock signals. When the internal clock is selected in these serial ports, the corresponding bit of Parallel Port F is set as an output. The Parallel Port F registers and their functions are described in Table 9-14 and in Table 9-15. Table 9-13. Parallel Port F Registers Register Name Port F Data Register Port F Control Register Port F Function Register Port F Drive Control Register Port F Data Direction Register Mnemonic PFDR PFCR PFFR PFDCR PFDDR I/O address 0x38 0x3C 0x3D 0x3E 0x3F R/W R/W W W W W Reset xxxxxxxx xx00xx00 xxxxxxxx xxxxxxxx 00000000 Table 9-14. Parallel Port F Register Functions Bit 7 PFDR (R/W) adr = 0x038 PFFR (W) adr = 0x03D PFDCR (W) adr = 0x03E PFDDR (W) adr = 0x03F PF7 pwm[3] out = open drain dir = out Bit 6 PF6 pwm[2] out = open drain dir = out Bit 5 PF5 pwm[1] out = open drain dir = out Bit 4 PF4 pwm[0] out = open drain dir = out Bit 3 PF3 x out = open drain dir = out Bit 2 PF2 x out = open drain dir = out Bit 1 PF1 sclk_c out = open drain dir = out Bit 0 PF0 sclk_d out = open drain dir = out 140 Rabbit 3000 Microprocessor Table 9-15. Parallel Port F Control Register (adr = 0x03C) Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0 00clock lower nibble on pclk/2 01clock on timer A1 10clock on timer B1 11clock on timer B2 x,x 00clock upper nibble on pclk/2 01clock on timer A1 x,x 10clock on timer B1 11clock on timer B2 The following registers are described in Table 9-14 and in Table 9-15. PFDRPort F data register. Reads value at pins. Writes to port F preload register. PFCRParallel Port F control register. This register is used to control the clocking of the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4, and 5 are reset to zero. PFFRPort F function register. Set bit to "1" to enable alternate output function. Bits 7-4 enable the PWM outputs and bits 1-0 enable synchronous serial ports C and D clock outputs for when the serial port is configured for internal clock generation. PFDCRParallel Port F drive control register. A "0" makes the corresponding pin a regular output. A "1" makes the corresponding pin an open-drain output. Write only. PFDDRPort F data direction register. Set to "1" to make corresponding pin an output. This register is zeroed on reset. On reset, the data direction register is zeroed, making all pins inputs. In addition certain bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers when loaded. All other registers associated with port F are not initialized on reset. 9.6.1 Using Parallel Port A and Parallel Port F A bug has been discovered in the Rabbit 3000 that results in a conflict between Parallel Port F and Parallel Port A under certain conditions. This bug has been corrected in versions of the Rabbit chip designated 3000A and later. See Appendix B for further details. The bug is rooted in an incomplete address decode for the data output register for Parallel Port A. This register responds to any of 16 addresses 30 to 3F (hex). When Parallel Port F was added, the addresses 38 to 3F were used, and the decode for Parallel Port A was not updated. There are five registers in Parallel Port F at addresses in the range of 38 to 3F. Writing to any of these registers will also cause a write to the Parallel Port A output register, which is identical to the slave port number zero output register. If Parallel Port A is used as in input register or if the auxiliary I/O bus (which uses the pins of Parallel Port A as a data bus) is enabled, then the spurious write has no effect on operation because the Parallel Port A output register is not used. However if Parallel Port A is used as an output or is used as the bidirectional bus of the slave port, then writing to any of the Parallel Port F registers will cause a spurious write to the Parallel Port A register, which will have a spurious effect on the operation of the Rabbit 3000 chip. Users Manual 141 The functionality of the Parallel Port F pins is not affected for pulse width modulation outputs and serial clock outputs, except that the Parallel Port F function and direction registers should be set up before a conflicting function on Parallel Port A is in use, since writing to these registers also writes to the Parallel Port A output register. 9.6.1.1 Summary Parallel Port A Parallel Port F Parallel Inputs Parallel Outputs Slave Port Auxiliary I/O Bus Full Functionality Parallel Inputs, PWM, Serial Port Clocks Parallel Inputs, PWM, Serial Port Clocks Full Functionality If you enable the auxiliary I/O bus, which uses Parallel Port A, then the bug does not manifest itself and you can use the full functionality of Parallel Port F. If you use Parallel Port A as inputs, then the bug does not manifest itself and the full functionality of Parallel Port F is available. If you use Parallel Port A as outputs, then you cannot use Parallel Port F pins as outputs too, except that you can use the PWM and clock outputs provided that you are aware that writing to the control registers of Parallel Port F will also write to the data output register of Parallel Port A. A simple way to resolve this is to leave Parallel Port A as an input until you complete the setup of Parallel Port F and then switch Parallel Port A to be an output. You can always use pins on Parallel Port F as inputs. If you enable the slave port, then you cannot use Parallel Port F as parallel outputs, but you can still use the other output functions of Parallel Port F following the precautions regarding setup described above. The easiest approach to avoid any problem when there is a conflict is to assign inputs and outputs in such a manner as to avoid the bug. Either Parallel Port A can be used as inputs, in which case Parallel Port F has full function, or if Parallel Port A cannot be used as inputs, use any pins on Parallel Port F not used for PWM or serial clock outputs as inputs and take the precaution of setting up Parallel Port F before the conflicting functionality of Parallel Port A is enabled. 142 Rabbit 3000 Microprocessor 9.7 Parallel Port G Parallel Port G is a byte-wide port with each bit programmable for data direction and drive. These are simple inputs and outputs controlled and reported in the Port G Data Register. As outputs, the bits of the port are buffered, with the data written to the Port G Data Register transferred to the output pins on a selected timing edge. The outputs of Timer A1, Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a separate select field to control this timing. These inputs and outputs are also used for access to other peripherals on the chip. As outputs, Port G can carry the data and clock outputs from Serial Ports E and F. As inputs, Port G can carry the data and clock inputs for these two serial ports. The following registers are described in Table 9-17 and in Table 9-18. Table 9-16. Parallel Port G Registers Register Name Port G Data Register Port G Control Register Port G Function Register Port G Drive Control Register Port G Data Direction Register Mnemonic PGDR PGCR PGFR PGDCR PGDDR I/O address 0x48 0x4C 0x4D 0x4E 0x4F R/W R/W W W W W Reset xxxxxxxx xx00xx00 xxxxxxxx xxxxxxxx 00000000 Table 9-17. Parallel Port G Data Register Functions Bit 7 PGDR (R/W) adr = 0x048 PGFR (W) adr = 0x04D PGDCR (W) adr = 0x04E PGDDR (W) adr = 0x04F PG7 x out = open drain dir = out Bit 6 PG6 SOUT_E Bit 5 PG5 RCLK_E Bit 4 PG4 TCLK_E Bit 3 PG3 x Bit 2 PG2 SOUT_F Bit 1 PG1 RCLK_F Bit 0 PG0 TCLK_F out = open drain dir = out out = open drain dir = out out = open drain dir = out out = open drain dir = out out = open drain dir = out out = open drain dir = out out = open drain dir = out Users Manual 143 Table 9-18. Parallel Port G Control Register (adr= 0x04C) Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0 00clock lower nibble on pclk/2 01clock on timer A1 10clock on timer B1 11clock on timer B2 x,x 00clock upper nibble on pclk/2 01clock on timer A1 x,x 10clock on timer B1 11clock on timer B2 The following registers are described in Table 9-17 and in Table 9-18. PGDRPort G data register. Reads value at pins. Writes to port G preload register. PGCRParallel Port G control register. This register is used to control the clocking of the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4, and 5 are reset to zero. PGFRPort G function register. Set bit to "1" to enable alternate output function. Bits 6 and 2 enable the asycnhronous or SDLC/HDLC serial ports E and F outputs. And bits 5-4 and 1-0 enable the SDLC/HDLC transmit and receive clock outputs for serial ports E and F. PGDCRParallel Port G drive control register. A "0" makes the corresponding pin a regular output. A "1" makes the corresponding pin an open-drain output. Write only. PGDDRPort G data direction register. Set to "1" to make corresponding pin an output. This register is zeroed on reset. On reset, the data direction register is zeroed, making all pins inputs. In addition certain bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers when loaded. All other registers associated with port G are not initialized on reset. 144 Rabbit 3000 Microprocessor 10. I/O BANK CONTROL REGISTERS The pins of Port E can be set individually to be I/O strobes. Each of the eight possible I/O strobes has a control register that controls the nature of the strobe and the number of wait states that will be inserted in the I/O bus cycle. Writes can also be suppressed for any of the strobes. The types of strobes are shown in Figure 10-1. Each of the eight I/O strobes is active for addresses occupying 1/8th of the 64K external I/O address space. T1 Tw T2 ADDR write data write strobe read data read strobe chip select strobe valid valid valid External I/O Timing (with 1 wait state) Figure 10-1. External I/O Bus Cycles Users Manual 145 Table 10-1 shows how the eight I/O bank control registers are organized. Table 10-1. I/O Bank x Control Register I/O Bank x Control Register (IB0CR) (IB1CR) (IB2CR) (IB3CR) (IB4CR) (IB5CR) (IB6CR) (IB7CR) Description Fifteen wait states for accesses in this bank. Seven wait states for accesses in this bank. Three wait states for accesses in this bank. One wait state for accesses in this bank. The Ix signal is an I/O chip select. The Ix signal is an I/O read strobe. The Ix signal is an I/O write strobe. The Ix signal is an I/O data (read or write) strobe. Writes are not allowed to this bank. Transactions are normal in every other way; only the write strobe is inhibited. Writes are allowed to this bank. I/O strobe (Ix) is active low. I/O strobe (Ix) is active high. These bits are ignored. (Address = 0x0080) (Address = 0x0081) (Address = 0x0082) (Address = 0x0083) (Address = 0x0084) (Address = 0x0085) (Address = 0x0086) (Address = 0x0087) Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 0 3 1 0 2 1 1:0 146 Rabbit 3000 Microprocessor The eight I/O bank control registers determine the number of I/O wait states applied to an external I/O access within the zone controlled by each register even if the associated strobes are not enabled. Note that the /IORD and /IOWR signals reflect these registers as well. The control over the generation of wait states is independent of whether or not the associated strobe in Port E is enabled. The upper 2 bits of each register determine the number of wait states. The four choices are 1, 3, 7, or 15 wait states. On reset, the bits are cleared, resulting in 15 wait states. There is always at least one external I/O wait state, and thus the minimum external I/O read cycle is three clocks long. The inhibit write function applies to both the Port E write strobes and the /IOWR signal. These control bits have no effect on the internal I/O space, which does not have wait states associated with read or write access. Internal I/O read or write cycles are two clocks long. The I/O strobes greatly simplify the interfacing of external devices. On reset, the upper 5 bits of each register are cleared. Parallel Port E will not output these signals unless the data-direction register bits are set for the desired output positions. In addition, the Port E function register must be set to "1" for each position. Each I/O bank is selected by the three most significant bits of the 16-bit I/O address. Table 10-2 shows the relationship between the I/O control register and its corresponding space in the 64K address space. Table 10-2. External I/O Register Address Range and Pin Mapping Control Register IB0CR IB1CR IB2CR IB3CR IB4CR IB5CR IB6CR IB7CR Port E I/O Address Pin A[15:13] PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 000 001 010 011 100 101 110 111 I/O Address Range 0x00000x1FFF 0x20000x3FFF 0x40000x5FFF 0x60000x7FFF 0x80000x9FFF 0xA0000xBFFF 0xC0000xDFFF 0xE0000xFFFF Users Manual 147 148 Rabbit 3000 Microprocessor 11. TIMERS There are two timersTimer A and Timer B. Timer A is intended mainly for generating the clock for various peripherals, baud clock for the serial ports, a periodic clock for clocking Parallel Ports D and E, or for generating periodic interrupts. Timers A1A7 are general-purpose timers, and Timers A8A10 are dedicated to specific peripherals. Timer B can be used for the same functions, but it cannot generate the baud clock. Timer B is more flexible when it can be used because the program can read the time from a continuously running counter and events can be programmed to occur at a specified future time. perclk A1 perclk/2 A3 Serial A A4 A8 A9 A10 Timer A1 perclk/2 perclk/8 10-bit counter compare 10 bits match reg Timer B System match preload Timer_B2 match reg match preload Timer_B1 Control Timer Synchronized outputs Input Capture PWM Quadrature Decode Serial B A5 Serial C A6 Serial D A7 Timer A System A2 Serial E Serial F perclk Figure 11-1. Block Diagram of Timers A and B Users Manual 149 11.1 Timer A Timer A consists of ten separate countdown timers A1A10 as shown in Figure 11-1. Timers A1 and A2A10 are 8-bit countdown registers as shown in Figure 11-2. The reload register can contain any number in the range from 0 to 255. The counter divides by (n+1). For example, if the reload register contains 127, then 128 pulses enter on the left before a pulse exits on the right. If the reload register contains zero, then each pulse on the left results in a pulse on the right, that is, there is division by one. 8-bit reload register Clock in 8-bit down counter load pulse on zero count out Input clock Count value 2 2 1 1 0 0 N N-1 Output pulse Figure 11-2. Reload Register Operation The timer systems can be driven by the peripheral clock, or peripheral clock divided by two. This clock is always the same as the processor clock, or it is faster than the processor clock by a factor of eight. The output pulses are always one clock long. Clocking of the counters takes place on the negative edge of this pulse. When the counter reaches zero, the reload register is loaded on the next input pulse instead of a count being performed. The reload registers may be reloaded at any time since the peripheral clock is synchronous with the processor clock. Timers A2, A3, A4, A5, A6 and A7 always provide the baud clock for Serial Ports E, F, A, B, C, and D respectively. Except for very low baud rates, clock A1 does not need to be used to prescale the input clock for timers A2A7. For example, if the system clock is 11.0592 MHz, and the timer A4 divides by 144, an asynchronous baud rate of 2400 bps can be achieved in one step (assuming that the timer is clocked by peripheral clock divided by two). The clock input to the serial port can be 8 or 16 times the baud rate for asynchronous mode and 8 times the baud rate for synchronous mode. The maximum asynchronous baud rate with a 11.0592 MHz clock would be (11,059,200/(1*8) = 1,382,400. 150 Rabbit 3000 Microprocessor For seven of the counters (A1A7), the terminal count condition is reported in a status register and can be programmed to generate an interrupt. There is one interrupt vector for Timer A and a common interrupt priority. A common status register (TACSR) has a bit for each timer that indicates if the output pulse for that timer has taken place since the last read of the status register. When the status register is read, these bits are cleared. No bit will be lost. Either it will be read by the status register read or it will be set after the status register read is complete. If a bit is on and the corresponding interrupt is enabled, an interrupt will occur when priorities allow. However, a separate interrupt is not guaranteed for each bit with an enabled interrupt. If the bit is read in the status register, it is cleared and no further interrupt corresponding to that bit will be requested. It is possible that one bit will cause an interrupt, and then one or more additional bits will be set before the status register is read. After these bits are cleared, they cannot cause an interrupt. If any bits are on, and the corresponding interrupt is enabled, then the interrupt will take place as soon as priorities allow. However, if the bit is cleared before the interrupt is latched, the bit will not cause an interrupt. The proper rule to follow is for the interrupt routine to handle all bits that it sees set. Although timers A8A10 are part of Timer A, they are dedicated to the input pulse capture, PWM, and quadrature decoder peripherals respectively. The peripherals clocked by these timers can generate interrupts but the timers themselves cannot. Furthermore, these timers cannot be cascaded with Timer A1. 11.1.1 Timer A I/O Registers The I/O registers for Timer A are listed in Table 11-1. Table 11-1. Timer A I/O Registers Register Name Timer A Control/Status Register Timer A Prescale Register Timer A Time Constant 1 Register Timer A Control Register Timer A Time Constant 2 Register Timer A Time Constant 8 Register Timer A Time Constant 3 Register Timer A Time Constant 9 Register Timer A Time Constant 4 Register Timer A Time Constant 10 Register Timer A Time Constant 5 Register Timer A Time Constant 6 Register Timer A Time Constant 7 Register Mnemonic TACSR TAPR TAT1R TACR TAT2R TAT8R TAT3R TAT9R TAT4R TAT10R TAT5R TAT6R TAT7R I/O address 0xA0 0xA1 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAD 0xAF R/W R/W W W W W W W W W W W W W Reset 00000000 xxxxxxx1 xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Users Manual 151 The following table summarizes Timer As capabilities. Table 11-2. Timer A Capabilities Timer A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Cascade none from A1 from A1 from A1 from A1 from A1 from A1 none none none Interrupt yes yes yes yes yes yes yes no no no Dedicated Connection Parallel Ports D-G, Timer B Serial Port E Serial Port F Serial Port A Serial Port B Serial Port C Serial Port D Input Capture Pulse Width Modulator Quadrature Decoder The control/status register for Timer A (TACSR) is laid out as shown in Table 11-3. Table 11-3. Timer A Control and Status Register Timer A Control and Status Register Bit(s) 7 (read) 7 (write) 6 (read) 6 (write) 5 (read) 5 (write) 4 (read) Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (TACSR) Description A7 counter has not reached its terminal count. A7 count done. This status bit is cleared by a read of this register. A7 interrupt disabled. A7 interrupt enabled. A6 counter has not reached its terminal count. A6 count done. This status bit is cleared by a read of this register. A6 interrupt disabled. A6 interrupt enabled. A5 counter has not reached its terminal count. A5 count done. This status bit is cleared by a read of this register. A5 interrupt disabled. A5 interrupt enabled. A4 counter has not reached its terminal count. A4 count done. This status bit is cleared by a read of this register. Rabbit 3000 Microprocessor (Address = 0x00A0) 152 Table 11-3. Timer A Control and Status Register (continued) Timer A Control and Status Register Bit(s) 4 (write) 3 (read) 3 (write) 2 (read) 2 (write) 1 (read) 1 (write) 0 (write-only) Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A4 interrupt disabled. A4 interrupt enabled. A3 counter has not reached its terminal count. A3 count done. This status bit is cleared by a read of this register. A3 interrupt disabled. A3 interrupt enabled. A2 counter has not reached its terminal count. A2 count done. This status bit is cleared by a read of this register. A2 interrupt disabled. A2 interrupt enabled. A1 counter has not reached its terminal count. A1 count done. This status bit is cleared by a read of this register. A1 interrupt disabled. A1 interrupt enabled. Disable Timer A main clock (perclk/2). Enable Timer A main clock (perclk/2). (TACSR) Description (Address = 0x00A0) Users Manual 153 The control register (TACR) is laid out as shown in Table 11-4. Table 11-4. Timer A Control Register Timer A Control Register Bit(s) 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 00 01 1:0 10 11 Timer A interrupts use Interrupt Priority 2. Timer A interrupts use Interrupt Priority 3. Timer A2 clocked by the output of Timer A1. Timer A interrupts are disabled. Timer A interrupts use Interrupt Priority 1. Timer A3 clocked by the output of Timer A1. Timer A2 clocked by the main Timer A clock. Timer A4 clocked by the output of Timer A1. Timer A3 clocked by the main Timer A clock. Timer A5 clocked by the output of Timer A1. Timer A4 clocked by the main Timer A clock. Timer A6 clocked by the output of Timer A1. Timer A5 clocked by the main Timer A clock. A7 Timer clocked by the output of Timer A1. Timer A6 clocked by the main Timer A clock. Value 0 (TACR) Description Timer A7 clocked by the main Timer A clock. (Address = 0x00A4) The Timer A Prescale Register (TAPR) specifies the main clock for Timer A. This will affect all of the timer A countdown timers. By default Timer A is clocked by peripheral clock divided by two. The prescale register (TAPR) is laid out as shown in Table 11-5. Table 11-5. Timer A Prescale Register Timer A Prescale Register Bit(s) 7:1 0 0 1 The main clock for Timer A is the peripheral clock divided by two. Value These bits are ignored. The main clock for Timer A is the peripheral clock. (TAPR) Description (Address = 0x00A1) 154 Rabbit 3000 Microprocessor The time constant register for each timer (TATxR) is simply an 8-bit data register holding a number between 0 and 255. This time constant will take effect the next time that the Timer A counter counts down to zero. The timer counts modulo (divide-by) n+1, where n is the programmed time constant. The time constant registers are write only. The time constant registers are listed in Table 11-1. 11.1.2 Practical Use of Timer A Timer A is disabled (bit 0 in control and status register) on power-up. Timer A is normally set up while the clock is disabled, but the timer setup can be changed while the timer is running when there is a need to do so. Timers that are not used should be driven from the output of A1 and the reload register should be set to 255. This will cause counting to be as slow as possible and consume minimum power. As for general-purpose timers, Timer A has seven separate subtimer units, A1 and A2A7, that are also referred to as timers. Most likely, if a serial port is going to be used and a timer is needed to provide the baud clock, that timer will be set up to be driven directly from the clock, and the interrupt associated with that timer will be disabled. (Serial port interrupts are generated by the serial port logic.) The value in the reload register can be changed while the timer is running to change the period of the next timer cycle. When the reload register is initialized, the contents of the countdown counter may be unknown, for example, during power-up initialization. If interrupts are enabled, then the first interrupt may take place at an unknown time. Similarly, if the timer output is being used to drive the clock for a parallel port or serial port, the first clock may come at a random time. If a periodic clock is desired, it is probably not important when the first clock takes place unless a phase relationship is desired relative to a different timers. A phase relationship between two timers can be obtained in several ways. One way is to set both reload registers to zero and to wait long enough for both timers to reload (maximum 256 clocks). Then both timers reload registers can be set to new values before or after both are clocked. Users Manual 155 11.2 Timer B Figure 11-1 shows a block diagram of Timer B. The Timer B counter can be driven directly by perclk/2, by that clock divided by 8, or by the output of Timer A1. Timer B has a continuously running 10-bit counter. The counter is compared against two match registers, the B1 match register and the B2 match register. When the counter transitions to a value equal to a match register, an internal pulse with a length of 1 peripheral clock is generated. The match pulse can be used to cause interrupts and/or clock the output registers of Parallel Ports D and E. The match registers are loaded from the match preload registers that are written to by an I/O instruction. The data byte in the match preload register is advanced to the next match register when the match pulse is generated. Every time a match condition occurs, the processor sets an internal bit that marks the match value in TBLxR as invalid. Reading TBCSR clears the interrupt condition. TBLxR must be reloaded to re-enable the interrupt. TBMxR does not need to be reloaded every time. If both match registers need to be changed, the most significant byte needs to be changed first. The I/O registers for Timer B are listed in Table 11-6. Table 11-6. Timer B Registers Register Name Timer B Control/Status Register Timer B Control Register Timer B MSB 1 Register Timer B LSB 1 Register Timer B MSB 2 Register Timer B LSB 2 Register Timer B Count MSB Register Timer B Count LSB Register Mnemonic TBCSR TBCR TBM1R TBL1R TBM2R TBL2R TBCMR TBCLR I/O address 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xBE 0xBF R/W R/W W W W W W R R Reset xxxxx000 xxxx0000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 156 Rabbit 3000 Microprocessor The control/status register for Timer B (TBCSR) is laid out as shown in Table 11-7. Table 11-7. Timer B Control and Status Register Timer B Control and Status Register Bit(s) 7:3 0 2 (read) 1 0 1 0 1 (read) 1 0 1 0 0 1 Enable the main clock for Timer B. Value (TBCSR) Description These bits are always read as zero. Timer B2 comparator has not encountered a match condition. Timer B2 comparator has encountered a match condition. This status bit and the Timer B2 interrupt (but not interrupt enable) are cleared by a read of this register. Timer B2 interrupt disabled. Timer B2 interrupt enabled. Timer B1 comparator has not encountered a match condition. Timer B1 comparator has encountered a match condition. This status bit and the Timer B1 interrupt (but not interrupt enable) are cleared by a read of this register. Timer B1 interrupt disabled. Timer B1 interrupt enabled. Disable the main clock for Timer B. (Address = 0x00B0) 2 (write) 1 (write) The control register for Timer B (TBCR) is laid out as shown in Table 11-8. Table 11-8. Timer B Control Register Timer B Control Register Bit(s) 7:4 00 3:2 01 1x 00 01 1:0 10 11 Timer B interrupts use Interrupt Priority 2. Timer B interrupts use Interrupt Priority 3. Value (TBCR) Description These bits are reserved and should be written with zeroes. Timer B clocked by the main Timer B clock (perclk/2). Timer B clocked by the output of Timer A1. Timer B clocked by the main Timer B clock (perclk/2) divided by 8. Timer B interrupts are disabled. Timer B interrupts use Interrupt Priority 1. (Address = 0x00B1) Users Manual 157 The MSB x registers for Timer B (TBM1R/TBM2R) are laid out as shown in Table 11-9. Table 11-9. Timer B Count MSB x Registers Timer B Count MSB x Register Bit(s) 7:6 5:0 Value Write (TBM1R) (TBM2R) Description The two MSBs of the comparae value for the Timer B comparator are stored. This compare value will be loaded into the actual comparator when the current compare detects a match. These bits are always read as zeroes. (Address = 0xB2) (Address = 0xB4) The LSB x registers for Timer B (TBL1R/TBL2R) are laid out as shown in Table 11-10. Table 11-10. Timer B Count LSB x Registers Timer B Count LSB x Register Bit(s) 7:0 Value Write (TBL1R) (TBL2R) Description The eight LSBs of the comparae value for the Timer B comparator are stored. This compare value will be loaded into the actual comparator when the current compare detects a match. (Address = 0xB3) (Address = 0xB5) Table 11-11. Timer B Count MSB Register Timer B Count MSB Register Bit(s) 7:6 5:0 Value Read (TBCMR) Description The current value of the two MSBs of the Timer B counter are reported. These bits are always read as zeroes. (Address = 0xBE) Table 11-12. Timer B Count LSB Register Timer B Count LSB Register Bit(s) 7:0 Value Read (TBCLR) Description The current value of the eight LSBs of the Timer B counter are reported. (Address = 0xBF) 158 Rabbit 3000 Microprocessor 11.2.1 Using Timer B Normally the prescaler is set to divide perclk/2 by a number that provides a counting rate appropriate to the problem. For example, if the clock is 22.1184 MHz, then perclk/2 is 11.0592 MHz. A Timer B clock rate of 11.0592 MHz will cause a complete cycle of the 10-bit clock in 92.6 s. Normally an interrupt will occur when either of the comparators in Timer B generates a pulse. The interrupt routine must detect which comparator is responsible for the interrupt and dispatch the interrupt to a service routine. The service routine sets up the next match value, which will become the match value after the next interrupt. If the clocked parallel ports are being used, then a value will normally be loaded into some bits of the parallel port register. These bits will become the output bits on the next match pulse. (It is necessary to keep a shadow register for the parallel port unless the bit-addressable feature of Ports D and E is used.) If you wish to read the time from the Timer B counter, either during an interrupt caused by the match pulse or in some other interrupt routine asynchronous to the match pulse, you will have to use a special procedure to read the counter because the upper 2 bits are in a different register than the lower 8 bits. The following method is suggested. 1. Read the lower 8 bits (read TBCLR register). 2. Read the upper 2 bits (read TBCMR register) 3. Read the lower 8 bits again (read TBCLR register) 4. If bit 7 changed from 1 to 0 between the first and second read of the lower 8 bits, there has been a carry to the upper 2 bits. In this case, read the upper 2 bits again and decrement those 2 bits to get the correct upper 2 bits. Use the first read of the lower 8 bits. This procedure assumes that the time between reads can be guaranteed to be less than 256 counts. This can be guaranteed in most systems by disabling the priority 1 interrupts, which will normally be disabled in any case in an interrupt routine. It is inadvisable to disable the high-priority interrupts (levels 2 and 3) as that defeats their purpose. If speed is critical, the three reads of the registers can be performed without testing for the carry. The three register values can be saved and the carry test can be performed by a lower priority analysis routine. Since the upper 2 bits are in the TBCMR register at address 0x0BE, and the lower 8 bits are in TBCLR at address 0x0BF, both registers can be read with a single 16-bit I/O instruction. The following sequence illustrates how the registers could be captured. ; enter from external interrupt on pulse input transition ; 19 clocks latency plus 10 clocks interrupt execution push af ; 7 push hl ioi ld a,(TBCLR) ; 11 get lower 8 bits of counter ioi ld hl,(TBCMR) ;13 get l=upper, h=lower Users Manual 159 Timer B can be used for various purposes. The 10-bit counter can be read to record the time at which an event takes place. If the event creates an interrupt, the timer can be read in the interrupt routine. The known time of execution of the interrupt routine can be subtracted. The variable interrupt latency is then the uncertainty in the event time. This can be as little 19 clocks if the interrupt is the highest priority interrupt. If the system clock is 20 MHz, the counter can count as fast as 10 MHz. The uncertainty in a pulse width measurement can be nearly as low as 38 clocks (2 x 19), or about 2 s for a 20 MHz system clock. Timer B can be used to change a parallel port output register at a particular specified time in the future. A pulse train with edges at arbitrary times can be generated with the restriction that two adjacent edges cannot be too close to each other since an interrupt must be serviced after each edge to set up the time for the next edge. This restriction limits the minimum pulse width to about 5 s, depending on the clock speed and interrupt priorities. 160 Rabbit 3000 Microprocessor 12. RABBIT SERIAL PORTS The Rabbit 3000 has 6 on-chip serial ports designated A, B, C, D, E, and F. All the ports can perform asynchronous serial communications at high baud rates. Ports A-D can operate as clocked ports. Ports A and B can be switched to alternate pins. Ports E and F support SDLC/HDLC synchronous communications in addition to standard asynchronous communications. Port A has the special capability of being used to remote boot the microprocessor via asynchronous, synchronous, or IrDA (asynchronous serial). Table 12-1 lists the synchronous serial port signals. Table 12-1. Serial Port Signals Serial Port Serial Port A TXA RXA CLKA ATXA ARXA Serial Port B TXB RXB CLKB ATXB ARXB Serial Port C TXC RXC CLKC Serial Port D TXD RXD CLKD Serial Port E TXE RXE TCLKE RCLKE Signal Name Function Serial Transmit Out Serial Transmit In Clock for clocked mode (bidirectional) Alternate serial transmit out Alternate serial receive in Serial Transmit Out Serial Transmit In Clock for clocked mode (bidirectional) Alternate serial transmit out Alternate serial receive in Serial Transmit Out Serial Transmit In Clock for clocked mode (bidirectional) Serial Transmit Out Serial Transmit In Clock for clocked mode (bidirectional) Serial Transmit Out Serial Transmit In Optional external transmit clock Optional external receive clock Users Manual 161 Table 12-1. Serial Port Signals (continued) Serial Port Serial Port F TXF RXF TCLKF RCLKF Signal Name Function Serial Transmit Out Serial Transmit In Optional external transmit clock Optional external receive clock Figure 12-1 shows a block diagram of the serial ports. CLKA TXA RXA ATXA ARXA CLKB TXB RXB ATXB ARXB CLKC TXC RXC CLKD Timer A7 Serial Port D TXD RXD Timer A4 Serial Port A Timer A5 Serial Port B Timer A6 Serial Port C Input to timers perclk or perclk/2 or prescaled (Timer A1) TXE RXE RCLKE TCLKE Timer A2 Serial Port E RCLKF TCLKF Timer A3 Serial Port F TXF RXF Figure 12-1. Block Diagram of Rabbit Serial Ports 162 Rabbit 3000 Microprocessor The individual serial ports are capable of operating at baud rates in excess of 500,000 bps in the asynchronous mode, and 8 times faster than that in the synchronous mode. Either 7 or 8 data bits may be transmitted and received in the asynchronous mode. The so-called "9th" bit or address bit mode of operation is also supported. The 9th bit can be set high or low by accessing the appropriate serial port register. Although Parity and multiple stop bits are not directly supported by the hardware, the 9th bit can be used to issue an extra stop bit (9th-bit high) or toggled to indicate parity. Users Manual 163 12.1 Serial Port Register Layout Figure 12-2 shows a functional block diagram of a serial port. Each serial port has a data register, a control register and a status register. Writing to the data register starts transmission. The least significant bit (LSB) is always transmitted first. This is true for both asycnchronous and synchronous communication. If the write is performed to an alternate data register address, the extra address bit or 9th bit (8th bit if 7 data bits) is sent. When data bits have been received, they are read from the data register (LSB first). The control register is used to set the transmit and receive parameters. The status register may be tested to check on the operation of the serial port. long stop register Read Data Write Data Data In Reg Data Out Reg 9th bit zero 9th bit one fifo ports E, F only (4-bytes deep) fifo ports E, F only (4-bytes deep) alternate data out registers address register Input Shift Reg output shift reg Tx serial data out LSB First Rx serial data in LSB First Bit 0 Tx 0 Start Bit Bit 0 Tx 0 Start Bit 9th bit Signals Shown at Microprocessor Tx Pin Stop Bit 1 1 0 1 0 1 1 1 2 3 4 5 6 7 A 1 1 0 1 0 1 1 Stop Bit stop 1 2 3 4 5 6 7 stop Transmitting 0x0D6 Transmitting 0x0D6 with 9th bit zero Figure 12-2. Functional Block Diagram of a Serial Port 164 Rabbit 3000 Microprocessor The clock input to the serial port unit must be 8 or 16 (selectable) times the baud rate in the asynchronous mode and 2 times the baud rate for the clocked serial mode when the internal clock is used. Timers A2A7 supply the input clock for Serial Ports AF. These timers can divide the frequency by any number from 1 to 256 (see Chapter 11). The input frequency to the timers can be selected in different ways described in the documentation for the timers. One choice is the peripheral clockwith that choice and a well-chosen crystal frequency for the main oscillator, the most commonly used baud rates can be obtained down to approximately 2400 bps or lower by prescaling timer A0 at the highest Rabbit clock frequencies (see Section A.3 in Appendix A). Users Manual 165 12.2 Serial Port Registers Each serial port has 6 registers shown in the tables below. The status, control and extended registers may have somewhat different formats for different serial ports. Table 12-2. Serial Port A Registers Register Name Serial Port A Data Register Serial Port A Address Register Serial Port A Long Stop Register Serial Port A Status Register Serial Port A Control Register Serial Port A Extended Register Mnemonic SADR SAAR SALR SASR SACR SAER I/O Address 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 R/W R/W W W R W W Reset xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 Table 12-3. Serial Port B Registers Register Name Serial Port B Data Register Serial Port B Address Register Serial Port B Long Stop Register Serial Port B Status Register Serial Port B Control Register Serial Port B Extended Register Mnemonic SBDR SBAR SBLR SBSR SBCR SBER I/O Address 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 R/W R/W W W R W W Reset xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 Table 12-4. Serial Port C Registers Register Name Serial Port C Data Register Serial Port C Address Register Serial Port C Long Stop Register Serial Port C Status Register Serial Port C Control Register Serial Port C Extended Register Mnemonic SCDR SCAR SCLR SCSR SCCR SCER I/O Address 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 R/W R/W W W R W W Reset xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 166 Rabbit 3000 Microprocessor Table 12-5. Serial Port D Registers Register Name Serial Port D Data Register Serial Port D Address Register Serial Port D Long Stop Register Serial Port D Status Register Serial Port D Control Register Serial Port D Extended Register Mnemonic SDDR SDAR SDLR SDSR SDCR SDER I/O Address 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 R/W R/W W W R W W Reset xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 Table 12-6. Serial Port E Registers Register Name Serial Port E Data Register Serial Port E Address Register Serial Port E Long Stop Register Serial Port E Status Register Serial Port E Control Register Serial Port E Extended Register Mnemonic SEDR SEAR SELR SESR SECR SEER I/O Address 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD R/W R/W W W R W W Reset xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 000x000x Table 12-7. Serial Port F Registers Register Name Serial Port F Data Register Serial Port F Address Register Serial Port F Long Stop Register Serial Port F Status Register Serial Port F Control Register Serial Port F Extended Register Mnemonic SFDR SFAR SFLR SFSR SFCR SFER I/O Address 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD R/W R/W W W R W W Reset xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 000x000x Users Manual 167 Table 12-8. Data Register All Ports Serial Port x Data Register (SADR) (SBDR) (SCDR) (SDDR) (SEDR) (SFDR) Description Returns the contents of the receive buffer. Loads the transmit buffer with a data byte for transmission. (Address = 0xC0) (Address = 0xD0) (Address = 0xE0) (Address = 0xF0) (Address = 0xC8) (Address = 0xD8) Bit(s) 7:0 Value Read Write Table 12-9. Address Register All Ports Serial Port x Address Register (SAAR) (SBAR) (SCAR) (SDAR) (SEAR) (SFAR) Description Returns the contents of the receive buffer. In Clocked Serial mode reading the data from this register automatically causes the receiver to start a byte receive operation (the current contents of the receive buffer are read first), eliminating the need for software to issue the Start Receive command. Loads the transmit buffer with an address byte, marked with a zero address bit, for transmission. In HDLC mode, the last byte of a frame must be written to this register to enable subsequent CRC and closing Flag transmission. In Clocked Serial mode writing the data to this register causes the transmitter to start a byte transmit operation, eliminating the need for the software to issue the Start Transmit command. (Address = 0xC1) (Address = 0xD1) (Address = 0xE1) (Address = 0xF1) (Address = 0xC9) (Address = 0xD9) Bit(s) Value Read 7:0 Write 168 Rabbit 3000 Microprocessor Table 12-10. Long Stop Register All Ports Serial Port x Long Stop Register (SALR) (SBLR) (SCLR) (SDLR) (SELR) (SFLR) Description Returns the contents of the receive buffer. Loads the transmit buffer with an address byte, marked with a one address bit, for transmission. In HDLC mode the last byte of a frame is written to this register to enable subsequent closing Flag transmission. (Address = 0xC2) (Address = 0xD2) (Address = 0xE2) (Address = 0xF2) (Address = 0xCA) (Address = 0xDA) Bit(s) Value Read 7:0 Write Users Manual 169 Table 12-11. Status Register Asynchronous Mode Only (All Ports) Serial Port x Status Register (SASR) (SBSR) (SCSR) (SDSR) (SESR) (SFSR) (Address = 0xC3) (Address = 0xD3) (Address = 0xE3) (Address = 0xF3) (Address = 0xCB) (Address = 0xDB) Bit(s) Value 0 Description (Async mode only) The receive data register is emptyno input character is ready. There is a byte in the receive buffer. The transition from "0" to "1" sets the receiver interrupt request flip-flop. The interrupt FF is cleared when the character is read from the data buffer. The interrupt FF will be immediately set again if there are more characters available in the FIFO or shift register to be transferred into the data buffer. The byte in the receive buffer is data, received with a valid Stop bit. Address bit or 9th (8th) bit received. This bit is set if the character in the receiver data register has a 9th (8th) bit. This bit is cleared and should be checked before reading a data register since a new data value with a new address bit may be loaded immediately when the data register is read. The byte in the receive buffer is an address, or a byte with a framing error. If an address bit is not expected. If the data in the buffer is all zeros, this may be a Break. The receive buffer was not overrun. This bit is set if the receiver is overrun. This happens if the shift register and the data register are full and a start bit is detected. This bit is cleared when the receiver data register is read. This bit is always zero in async mode. The transmit buffer is empty. 7 1 0 6 1 0 5 1 4 0 0 3 1 Transmitter data buffer full. This bit is set when the transmit data register is full, that is, a byte is written to the serial port data register. It is cleared when a byte is transferred to the transmitter shift register or FIFO, or a write operation is performed to the serial port status register. This bit will request an interrupt on the transition from 1 to 0 if interrupts are enabled. Transmit interrupts are cleared when the transmit buffer is written, or any value (which will be ignored) is written to this register. The transmitter is idle. Transmitter busy bit. This bit is set if the transmitter shift register is busy sending data. It is set on the falling edge of the start bit, which is also the clock edge that transfers data from the transmitter data register to the transmitter shift register. The transmitter busy bit is cleared at the end of the stop bit of the character sent. This bit will cause an interrupt to be latched when it goes from busy to not busy status after the last character has been sent (there are no more data in the transmitter data register). These bits are always zero in async mode. 0 2 1 1:0 00 170 Rabbit 3000 Microprocessor Table 12-12. Status Register Clocked Serial (Ports A-D only) Serial Port x Status Register (SASR) (SBSR) (SCSR) (SDSR) (Address = (Address = (Address = (Address = 0xC3) 0xD3) 0xE3) 0xF3) Bit(s) Value 0 Description (Clocked serial mode only) The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty. This bit is always zero in clocked serial mode. The receive buffer was not overrun. The receive buffer was overrun. This bit is cleared by reading the receive buffer. This bit is always zero in clocked serial mode. The transmit buffer is empty. The transmit buffer is not empty. The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer. Transmit interrupts are cleared when the transmit buffer is written, or any value (which will be ignored) is written to this register. The transmitter is idle. The transmitter is sending a byte. An interrupt is generated when the transmitter clears this bit, which occurs only if the transmitter is ready to start sending another byte but the transmit buffer is empty. These bits are always zero in clocked serial mode. 7 1 6 5 1 4 0 0 3 1 0 0 0 2 1 1:0 00 Users Manual 171 Table 12-13. Status Register HDLC Mode (Ports E and F only) Serial Port x Status Register Bit(s) Value 0 7 1 00 01 6,4 10 11 0 5 1 0 3 1 The receive buffer was overrun. This bit is cleared by reading the receive buffer. The transmit buffer is empty. The transmit buffer is not empty. The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer, unless the byte is marked as the last in the frame. Transmit interrupts are cleared when the transmit buffer is written, or any value (which will be ignored) is written to this register. Transmit interrupt due to buffer empty condition. Transmitter finished sending CRC. An interrupt is generated at the end of CRC transmission. Data written in response to this interrupt will cause only one Flag to be transmitted between frames, and no interrupt will be generated by this Flag. Transmitter finished sending an Abort. An interrupt is generated at the end of an Abort transmission. The transmitter finished sending a closing Flag. Data written in response to this interrupt will cause at least two Flags to be transmitted between frames. The byte in the receiver buffer is 8 bits. The byte in the receiver buffer is less than 8 bits. The byte in the receive buffer is the last in the frame, with valid CRC. The byte in the receive buffer is the last in the frame, with a CRC error. The receive buffer was not overrun. (SESR) (SFSR) (Address = 0xCB) (Address = 0xD3) Description (HDLC mode only) The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty. The byte in the receive buffer is data. The byte in the receive buffer was followed by an Abort. 00 01 2:1 10 11 0 0 1 172 Rabbit 3000 Microprocessor Table 12-14. Serial Port Control Register Ports A and B Serial Port x Control Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 1x 3:2 00 01 (SACR) (SBCR) Description No operation. These bits are ignored in the Async mode. In clocked serial mode, start a byte receive operation. In clocked serial mode, start a byte transmit operation. In clocked serial mode, start a byte transmit operation and a byte receive operation simultaneously. Parallel Port C is used for input. Parallel Port D is used for input. Disable the receiver input. Async mode with 8 bits per character. Async mode with 7 bits per character. In this mode the most significant bit of a byte is ignored for transmit, and is always zero in receive data. Clocked serial mode with external clock. Serial Port A clock is on Parallel Port PB1 Serial Port B clock is on Parallel Port PB0 Clocked serial mode with internal clock. Serial Port A clock is on Parallel Port PB1 Serial Port B clock is on Parallel Port PB0 The Serial Port interrupt is disabled. The Serial Port uses Interrupt Priority 1. The Serial Port uses Interrupt Priority 2. (Address = 0xC4) (Address = 0xD4) 10 11 1:0 00 01 10 Users Manual 173 Table 12-15. Serial Port Control Register Ports C and D Serial Port x Control Register Bit(s) Value 00 01 7:6 10 11 0 5 1 4 x 00 01 Disable the receiver input. This bit is ignored. 8 bits per character. 7 bits per character. In this mode the most significant bit of a byte is ignored for transmit, and is always zero in receive data. Clocked serial mode with external clock. Serial Port C clock is on Parallel Port PF1 Serial Port D clock is on Parallel Port PF0 Clocked serial mode with internal clock. Serial Port C clock is on Parallel Port PF1 Serial Port D clock is on Parallel Port PF0 The serial port interrupt is disabled. The serial port uses Interrupt Priority 1. The serial port uses Interrupt Priority 2. The serial port uses Interrupt Priority 3. (SCCR) (SDCR) Description No operation. These bits are ignored in the async mode. In clocked serial mode, start a byte receive operation. In clocked serial mode, start a byte transmit operation. In clocked serial mode, start a byte transmit operation and a byte receive operation simultaneously. Enable the receiver input. (Address = 0xE4) (Address = 0xF4) 3:2 10 11 00 01 1:0 10 11 174 Rabbit 3000 Microprocessor Table 12-16. Serial Port Control Register Ports E and F Serial Port x Control Register Bit(s) Value 00 01 7:6 10 11 0 5 1 4 x 00 01 Disable the receiver input. This bit is ignored. Async mode with 8 bits per character. Async mode with 7 bits per character. In this mode the most significant bit of a byte is ignored for transmit, and is always zero in receive data. HDLC mode with external clock. The external clocks are supplied as follows: 3:2 10 No operation. In HDLC mode, transmit an Abort pattern. Enable the receiver input. (SECR) (SFCR) Description No operation. These bits are ignored in the Async mode. In HDLC mode, force receiver in Flag Search mode. (Address = 0xCC) (Address = 0xDC) Transmit clock (Serial Port F)pins PG0 and PG1on Parallel Port G. Receive clock (Serial Port E)pins PG4 and PG5 on Parallel Port G. HDLC mode with internal clock. The clock is 16 the data rate, and the DPLL is used to recover the receive clock. If necessary, the clocks are supplied as follows: 11 Transmit clock (Serial Port F)pins PG0 and PG1on Parallel Port G. Receive clock (Serial Port E)pins PG4 and PG5 on Parallel Port G. The serial port interrupt is disabled. The serial port uses Interrupt Priority 1. The serial port uses Interrupt Priority 2. The serial port uses Interrupt Priority 3. 00 01 1:0 10 11 Users Manual 175 Table 12-17. Extended Register Asynchronous Mode All Ports Serial Port x Extended Register (SAER) (SBER) (SCER) (SDER) (SEER) (SFER) (Address = 0xC5) (Address = 0xD5) (Address = 0xE5) (Address = 0xF5) (Address = 0xCD) (Address = 0xDD) Bit(s) 7:5 4 Value xxx 0 1 0 Description (Async mode only) These bits are ignored in async mode. Normal async data encoding. Enable RZI coding (3/16ths bit cell IrDA-compliant). Normal Break operation. This option should be selected when address bits are expected. Fast Break termination. At the end of Break a dummy character is written to the buffer, and the receiver can start character assembly after one bit time. Async clock is 16X data rate. Async clock is 8X data rate. These bits are ignored in async mode. 3 1 0 2 1 1:0 xx 176 Rabbit 3000 Microprocessor Table 12-18. Extended Register Clocked Serial Mode (Ports A-D only) Serial Port x Extended Register (SAER) (SBER) (SCER) (SDER) (Address = 0xC5) (Address = 0xD5) (Address = 0xE5) (Address = 0xF5) Bit(s) 7 Value 0 1 0 Description (Clocked serial mode only) Normal clocked serial operation. Timer synchronized clocked serial operation. Timer-synchronized clocked serial uses Timer B1. Timer-synchronized clocked serial uses Timer B2. Normal clocked serial clock polarity, inactive High. Internal or external clock. Normal clocked serial clock polarity, inactive Low. Internal clock only. Inverted clocked serial clock polarity, inactive Low. Internal or external clock. Inverted clocked serial clock polarity, inactive High. Internal clock only. These bits are ignored in clocked serial mode. No effect on transmitter. Terminate current clocked serial transmission. No effect on buffer. No effect on receiver. Terminate current clocked serial reception. 6 1 00 01 5:4 10 11 3:2 1 1 0 0 1 xx 0 Users Manual 177 Table 12-19. Extended Register HDLC Mode (Ports E and F only) Serial Port x Extended Register Bit(s) Value 000 010 7:5 100 110 111 0 4 1 0 3 1 0 2 1 1:0 xx Transmit Abort on underrun. These bits are ignored in HDLC mode. Idle line condition is all ones. Transmit Flag on underrun. (SEER) (SFER) (Address = 0xCD) (Address = 0xDD) Description (HDLC mode only) NRZ data encoding for HDLC receiver and transmitter. NRZI data encoding for HDLC receiver and transmitter. Biphase-Level (Manchester) data encoding for HDLC receiver and transmitter. Biphase-Space data encoding for HDLC receiver and transmitter. Biphase-Mark data encoding for HDLC receiver and transmitter. Normal HDLC data encoding. Enable RZI coding (1/4th bit cell IRDA-compliant). This mode can only be used with internal clock and NRZ data encoding. Idle line condition is Flags. 178 Rabbit 3000 Microprocessor 12.3 Serial Port Interrupt A common interrupt vector is used for the receive and transmit interrupts. There is a separate interrupt request flip-flop for the receiver and transmitter. If either of these flip-flops is set, a serial port interrupt is requested. The flip-flops are set by a rising edge only. The flip-flops are cleared by a pulse generated by an I/O read or write operation as shown in Figure 12-3. When an interrupt is requested, it will take place immediately when priorities allow and an instruction execution is complete. The interrupt is lost if the request flip-flop is cleared before the interrupt takes place. If the flip-flop is not cleared in the interrupt, another interrupt will take place when priorities are lowered. Transmitter IRQ Transmitter Data Buffer Empty or Transmitter not Busy Request Interrupt Write Transmitter Data Register or Write Status Register Receiver IRQ Receiver Data Buffer Full Read Receiver Data Register Figure 12-3. Generation of Serial Port Interrupts The receive interrupt request flip-flop is set after the stop bit is sampled on receive, nominally 1/2 of the way through the stop bit. Data bits are transferred on this same clock from the receive shift register to the receive data register. The transmit interrupt request flip-flop is set on the leading edge of the start bit for data register empty and at the trailing edge of the stop bit for shift register empty (transmitter idle). Unless the data register is empty on this trailing edge of the stop bit, the transmitter does not become idle. The transmitter becomes idle only if the data register is empty at the trailing edge of the stop bit. The serial port interrupt vectors are shown in Table 6-1. Users Manual 179 12.4 Transmit Serial Data Timing On transmit, if the interrupts are enabled, an interrupt is requested when the transmit register becomes empty and, in addition, an interrupt occurs when the shift register and transmit register both become empty, that is, when the transmitter becomes idle. The shift register is empty when the last bit is shifted out. When the transmit data register contains data and the shift register finishes sending data, the data bits are clocked from the transmit register to the shift register, and the shift register is never idle. The interrupt request is cleared either by writing to the data register or by writing to the status register (which does not affect the status register). The data register normally is clocked into the shift register each time the shift register finishes sending data, leaving the data register empty. This causes an interrupt request. The interrupt routine normally answers the interrupt before the shift register runs dry (9 to 11 baud clocks, depending on the mode of operation). The interrupt routine stores the next data item in the data register, clearing the interrupt request and supplying the next data bits to be sent. When all the characters have been sent, the interrupt service routine answers the interrupt once the data register becomes empty. Since it has no more data, it clears the interrupt request by storing to the status register. At this point the routine should check if the shift register is empty; normally it wont be. If it is, because the interrupt was answered late, the interrupt routine should do any final cleanup and store to the status register again in case the shift register became empty after the pending interrupt is cleared. Normally, though, the interrupt service routine will return and there will be a final interrupt to give the routine a chance to disable the output buffers, as in the case for RS-485 transmission. 180 Rabbit 3000 Microprocessor 12.5 Receive Serial Data Timing When the receiver is ready to receive data, a falling edge indicates that a start bit must be detected. The falling edge is detected as a different Rx input between two different clocks, the clock being 8x or 16x the baud rate. Once the start bit has been detected, data bits are sampled at the middle of each data bit and are shifted into the receive shift register. After 7 or 8 data bits have been received, the next bit will be either a 9th (8th) address bit, or a stop bit will be sampled. If the Rx line is low, it is an address bit and the address bit received bit in the status register will be enabled. If an address bit is detected, the receiver will attempt to sample the stop bit. If the line is high when sampled, it is a stop bit and a new scan for a new start bit will begin after the sample point. At the same time, the data bits are transferred into the receive data register and an interrupt, if enabled, is requested. On receive, an interrupt is requested when the receiver data register has data. This happens when data bits are transferred from the receive shift register to the data register. This also sets bit 7 of the status register. The interrupt request and bit 7 are cleared when the data register is read. An interrupt is requested if bit 7 is high. The interrupt is requested on the edge of the transmitter data register becoming empty or the transmitter shift register becoming empty. The transmitter interrupt is cleared by writing to the status register or to the data register. On receive, the scan for the next start bit starts immediately after the stop bit is detected. The stop bit is normally detected at a sample clock that nominally occurs in the center of the stop bit. If there is a 9th (8th) address bit, the stop bit follows that bit. The serial clock can be configured to be either 16 the data rate or 8 the data rate. Serial Port Input Clock 8 clocks stop bit Receiver Data Ready Bit start bit sampling point Asynchronous Receive Transmitter Data Reg Full Asynchronous Transmit Figure 12-4. Serial Port Synchronization Users Manual 181 12.6 Clocked Serial Ports Ports AD can operate in clocked mode. The data line and clock line are driven as shown in Figure 12-4. The data and clock are provided as 8-bit bursts with the LSB shifted out and/or received first. By default the transmit shift register advances on the falling edge of the clock and the receiver samples the data on the rising edge of the clock. The serial port can generate the clock or the clock can be provided externally. The clock polarity is programmable in clocked serial mode according to Figure . The clocked serial transfer may also be synchronized to the output of either of the match conditions in Timer B to give precisely timed transfers. To enable the clocked serial mode, a code must be in bits (3,2) of the control register, enabling the clocked serial mode with either an internal clock or an external clock. The transition between the external and the internal clock should be performed with care. Normally a pullup resistor is needed on the clock line to prevent spurious clocks while neither party is driving the clock. CLK (Mode 00) CLK (Mode 01) CLK (Mode 10) CLK (Mode 11) Tx D0 D1 D2 D3 D4 D5 D6 D7 Rx D0 D1 D2 D3 D4 D5 D6 D7 Figure 12-5. Clock Polarities Supported in Clocked Serial Mode In clocked serial mode the shift register and the data register work in the same fashion as for asynchronous communications. However, to initiate basic sending or receiving, a command must be issued by writing to bits (7,6) of the control register for each byte sent or received. One command is for sending a byte, a different command is for receiving a byte, and yet another command can initiate a transmit and receive at the same time for full duplex communication. Alternatively, a read or write to the Serial Ports A-D Address registers (SxAR) eliminates the need to issue separate receive and transmit commands. In clocked serial mode, reading the data from the corresponding SxAR register automatically causes the receiver to start a byte receive operation, eliminating the need for software to issue the Start Receive command. Any data contained in the receive buffer will be read first before being replaced 182 Rabbit 3000 Microprocessor with new incoming data. Similarly, writing the data to the SxAR register causes the transmitter to start a byte transmit operation, eliminating the need for the software to issue the Start Transmit command. The effect of these codes is different, depending on whether the mode is internal clock or external clock. To transmit in internal clock mode, the user must first load the data register (which must be empty) and then store the send code. When the shift register finishes sending the current character, if any, the data register will be loaded into the shift register and transmitted by an 8-clock burst. One character can be in the process of transmitting while another character is waiting in the data register tagged with the send code. The send code is effectively double-buffered. To receive a character in internal clock mode, the receive shift register should be idle. The user then stores the receive code in the control register. A burst of 8 clocks will be generated and the sender must detect the clocks and shift output data to the data line on the falling edge of each clock. The receiver will sample the data on the rising edge of each clock for clock modes 00 and 01 or the falling edge for clock modes 10 and 11. The receive mode cannot double-buffer characters when using the internal clock. The shift register must be idle before another character receive can be initiated. However, the interrupt request and character ready takes place on the rising edge of the last clock pulse. If the next receive code is stored before the natural location of the next falling edge, another receive will be initiated without pausing the clock. To do this, the interrupt has to be serviced within 1/2 clock. To transmit each byte in external clock mode, the user must load the data register and then store the send code. When the shift register is idle and the receiver provides a clock burst, the data bits are transferred to the shift register and are shifted out. Once the transfer is made to the shift register, a new byte can be loaded into the transmit register and a new send code can be stored. To receive a byte in external clock mode, the user must set the receive code for the first byte and then store the receive code for the next byte after each byte is removed from the data register. Since the receive code must be stored before the transmitter sends the next byte, the receiver must service the interrupt within 1/2 baud clock to maintain full-speed transmission. This is usually not practical unless a flow control arrangement is made or the transmitter inserts gaps between the clock bursts. In order to carry on high-speed communication, the best arrangement will usually be for the receiver to provide the clock. When the receiver provides the clock, the transmitter should always be able to keep up because it is double-buffered and has a full character time to answer the transmitter data register empty interrupt. The receiver will answer interrupts that are generated on the last clock rising edge. If the interrupt can be serviced within 1/2 clock, there will be no pause in the data rate. If it takes the receiver longer to answer, then there will be a gap between bytes, the length of which depends on the interrupt latency. For example, if the baud rate is 400,000 bps, then up to 50,000 bytes per second could be transmitted, or a byte every 20 s. No data will be lost if the transmitter can Users Manual 183 answer its interrupts within 20 s. There will be no slow down if the receiver can answer its interrupt within 1/2 clock or 1.25 s. If it can answer within 1.5 clocks, or 2.75 s, the data rate will slow to 44,444 bytes per second. If it can answer in 2.5 clocks or 6.25 s, the data rate slows to 40,000 bytes per second. If it can answer in 3.5 clocks or 8.75 s, the data rate will slow to 36,363 bytes per second, and so forth. If two-way half-duplex communication is desired, the clock can be turned around so that the receiver always provides the clock. This is slightly more complicated since the receiver cannot initiate a message. If the receiver attempts to receive a character and the transmitter is not transmitting, the last bit sent will be received for all eight bits. 184 Rabbit 3000 Microprocessor 12.7 Clocked Serial Timing 12.7.1 Clocked Serial Timing With Internal Clock For synchronous serial communication, the serial clock can be either generated by the Rabbit or by an external device. The timing diagram in Figure 12-6 below can be applied to both full-duplex and half-duplex clocked serial communication where the serial clock is generated internally by the Rabbit. Other SPI compatible clock modes supported by the Rabbit 3000 are shown in Figure 12-5. With an internal clock, the maximum serial clock rate is perclk/2. CYCLE CLKA TxA RxA LSB LSB BIT 1 BIT 1 BIT 2 BIT 2 BIT 3 BIT 3 BIT 4 BIT 4 BIT 5 BIT 5 BIT 6 BIT 6 MSB MSB 1 2 3 4 5 6 7 8 Rx Capture Strobe Figure 12-6. Full-Duplex Clocked Serial Timing Diagram with Internal Clock (Mode 00) 12.7.2 Clocked Serial Timing with External Clock In a system where the Rabbit serial clock is generated by an external device, the clock signal has to be synchronized with the internal peripheral clock (perclk) before data can be transmitted or received by the Rabbit. Depending on when the external serial clock is generated, in relation to perclk, it may take anywhere from 2 to 3 clock cycles for the external clock to be synchronized with the internal clock before any data can be transferred. Figure 12-7 shows the timing relationship among perclk, the external serial clock, and data transmit. perclk CLKA (ext.) TxA Figure 12-7. Synchronous Serial Data Transmit Timing with External Clock (Mode 00) Users Manual 185 Figure 12-8 shows the timing relationship among perclk, the external serial clock, and data receive. Note that RxA is sampled by the rising edge of perclk. perclk CLKA (Ext.) RxA Valid Figure 12-8. Synchronous Serial Data Receive Timing with External Clock (Mode 00) When clocking the Rabbit externally, the maximum serial clock frequency is limited by the amount of time required to synchronize the external clock with the Rabbit perclk. If we sum the maximum number of perclk cycles required to perform clock synchronization for each of the receive and transmit cases, then the fastest external serial clock frequency would be limited to perclk/6. 186 Rabbit 3000 Microprocessor 12.8 Synchronous Communications on Ports E and F Serial Port E and F are a dual-function serial ports that can be used in either asynchronous or HDLC mode. Four bytes of buffering are available for both receiver and transmitter to reduce interrupt overhead. An interrupt is generated whenever at least one byte is available in the receiver buffer and every time a byte is removed from the transmitter buffer. Serial Port E is clocked by the output of Timer A2 and Serial Port F by A3. In asynchronous mode this clock can be either sixteen (the default) or eight times the data rate. In HDLC mode this clock is sixteen times the data rate. Note that the fastest output from Timer A2 or A3 is the same frequency as the peripheral clock. Thus the maximum data rate is the peripheral clock frequency divided by eight in async mode and divided by sixteen in HDLC mode. The HDLC receiver employs a Digital Phase-Locked-Loop (DPLL) to generate a synchronized receive clock for the incoming data stream. HDLC mode also allows for an external 1x (same speed as the data rate) clock for both the receiver and the transmitter. HDLC receive and transmit clocks can be input or output, as appropriate, via the specified pins. When using an external clock, the maximum data rate is one-sixth of the peripheral clock rate. In asynchronous mode the port can send and receive seven or eight bits and has the option of appending and recognizing an additional address bit. On transmit, the address bit is automatically appended to the data when this data is written to the address register or long stop register. Writing to the address register appends an zero address bit to the data, while writing to the long stop register appends an one address bit to the data. The address bit is followed by a normal stop bit. Normal data is written to the data register to be transmitted. On receive, a status bit distinguishes normal data from address data. This status bit is set to one if a zero address bit is received. In non-address bit applications, this indicates a framing error. This status bit can also indicate a received break, if the accompanying data is all zeros (this is the definition of break). Asynchronous mode operates full-duplex. Either the receive data available, transmit buffer empty or transmit idle conditions can be programmed to generate an interrupt. The HDLC mode allows full-duplex synchronous communication. Either an internal or external clock may be selected for both the receiver and the transmitter. HDLC mode encapsulates data within opening and closing Flags, and sixteen bits of CRC precedes the closing Flag. All information between the opening and closing Flag is "zero-stuffed". That is, if five consecutive ones occur, independent of byte boundaries, a zero is automatically inserted by the transmitter and automatically deleted by the receiver. This allows a Flag byte (0x07E) to be unique within the serial bit stream. The standard CRC-CCITT polynomial (x16 + x12 + x5 + 1) is implemented, with the generator and checker preset to all ones. Both receive and transmit operation are essentially automatic. In the receiver, each byte is marked with status to indicate end-of-frame, short frame and CRC error. The receiver automatically synchronizes on Flag bytes and presets the CRC checker appropriately. If Users Manual 187 the current receive frame is not needed (because it is addressed to a different station, for example) a Flag Search command is available. This command forces the receiver to ignore the incoming data stream until another Flag is received. In the transmitter, the CRC generator is preset and the opening Flag is transmitted automatically after the first byte is written to the transmitter buffer, and CRC and the closing flag are transmitted after the byte that is written to the buffer through the Address Register. If no CRC is required, writing the last byte of the frame to the Long Stop Register automatically appends a closing flag after the last byte. If the transmitter underflows, either an Abort or a Flag will be transmitted, under program control. A command is available to send the Abort pattern (seven consecutive ones) if a transmit frame needs to be aborted prematurely. The Abort command takes effect on the next byte boundary, and causes the transmission of an 0xFE (a zero followed by seven ones), after which the transmitter will send the idle line condition. The Abort command also purges the transmit FIFO. The idle line condition may be either Flags or all ones. Both the receiver and transmitter contain four bytes of buffering for the data. Status bits are buffered along with the data in both receiver and transmitter. The receiver automatically generates an interrupt at the end of a received frame, and the transmitter generates an interrupt at the end of CRC transmission, at the end of the transmission of an Abort sequence, and at the end of the transmission of a closing Flag. The transmitter is not capable of sending an arbitrary number of bits, but only a multiple of bytes. However, the receiver can receive frames of any bit length. If the last "byte" in the frame is not eight bits, the receiver sets a status flag that is buffered along with this last byte. Software can then use the table below to determine the number of valid data bits in this last "byte." Note that the receiver transfers all bits between the opening and closing Flags, except for the inserted zeros, to the receiver data buffer. Last Byte Bit Pattern bbbbbbb0 bbbbbb01 bbbbb011 bbbb0111 bbb01111 bb011111 b0111111 Valid Data Hits 7 6 5 4 3 2 1 Several types of data encoding are available in the HDLC mode. In addition to the normal NRZ, they are NRZI, Biphase-Level (Manchester), Biphase-Space (FM0) and BiphaseMark (FM1). Examples of these encodings are shown in the Figure below. Note that in NRZI, Biphase-Space and Biphase-Mark the signal level does not convey information. Rather it is the placement of the transitions that determine the data. In Biphase-Level it is the polarity of the transition that determines the data. 188 Rabbit 3000 Microprocessor Serial Clock NRZ Data NRZI NRZI Biphase-Level Biphase-Space Biphase-Space Biphase-Mark Biphase-Mark data "1" "0" "1" "1" "0" "0" "1" "0" In HDLC mode the internal clock comes from the output of Timer A2. This timer output is divided by sixteen to form the transmit clock, and is fed to the Digital Phase-Locked Loop (DPLL) to form the receive clock. The DPLL is basically just a divide-by-16 counter that uses the timing of the transitions on the receive data stream to adjust its count. The DPLL adjust the count so that the output of the DPLL will be properly placed in the bit cells to sample the receive data. To work properly, then, transitions are required in the receive data stream. NRZ data encoding does not guarantee transitions in all cases (a long string of zeros for example), but the other data encodings do. NRZI guarantees transitions because of the inserted zeros, and the Biphase encodings all have at least one transition per bit cell. The DPLL counter normally counts by sixteen, but if a transition occurs earlier or later than expected the count will be modified during the next count cycle. If the transition occurs earlier than expected, it means that the bit cell boundaries are early with respect to the DPLL-tracked bit cell boundaries, so the count is shortened, either by one or two counts. If the transition occurs later than expected, it means that the bit cell boundaries are late with respect to the DPLL-tracked bit cell boundaries, so the count is lengthened, either by one or two counts. The decision to adjust by one or by two depends on how far off the DPLL-tracked bit cell boundaries are. This tracking allows for minor differences in the transmit and receive clock frequencies. With NRZ and NRZI data encoding, the DPLL counter runs continuously, and adjusts after every receive data transition. Since NRZ encoding does not guarantee a minimum density of transitions, the difference between the sending data rate and the DPLL output Users Manual 189 clock rate must be very small, and depends on the longest possible run of zeros in the received frame. NRZI encoding guarantees at least one transition every six bits (with the inserted zeros). Since the DPLL can adjust by two counts every bit cell, the maximum difference between the sending data rate and the DPLL output clock rate is 1/48 (~2%). With Biphase data encoding (either -Level, -Mark or -Space), the DPLL runs only as long as transitions are present in the receive data stream. Two consecutive missed transitions causes the DPLL to halt operation and wait for the next available transition. This mode of operation is necessary because it is possible for the DPLL to lock onto the optional transitions in the receive data stream. Since they are optional, they will eventually not be present and the DPLL can attempt to lock onto the required transitions. Since the DPLL can adjust by one count every bit cell, the maximum difference between the sending data rate and the DPLL output clock rate is 1/16 (~6%). With Biphase data encoding the DPLL is designed to work in multiple-access conditions where there may not be Flags on an idle line. The DPLL will properly generate an output clock based on the first transition in the leading zero of an opening Flag. Similarly, only the completion of the closing Flag is necessary for the DPLL to provide the extra two clocks to the receiver to properly assemble the data. In Biphase-Level mode, this means the transition that defines the last zero of the closing Flag. In Biphase-Mark and Biphase-Space modes this means the transition that defines the end of the last zero of the closing Flag. The figure below shows the adjustment ranges and output clock for the different modes of operation of the DPLL. Each mode of operation will be described in turn. Bit cell NRZI adj none add one add two subtract two subtract one none NRZI Clock Bi-L adj ignore transitions subtract one none add one ignore transitions Bi-L Clock Bi-S adj none add one ignore transitions subtract one none Bi-S Clock Bi-M adj none add one ignore transitions subtract one none Bi-M Clock 190 Rabbit 3000 Microprocessor With NRZ and NRZI encoding all transitions occur on bit-cell boundaries and the data should be sampled in the middle of the bit cell. If a transition occurs after the expected bitcell boundary (but before the midpoint) the DPLL needs to lengthen the count to line up the bit-cell boundaries. This corresponds to the add one and add two regions shown. If a transition occurs before the bit cell boundary (but after the midpoint) the DPLL needs to shorten the count to line up the bit-cell boundaries. This corresponds to the subtract one and subtract two regions shown. The DPLL makes no adjustment if the bit-cell boundaries are lined up within one count of the divide-by-sixteen counter. The regions that adjust the count by two allow the DPLL to synchronize faster to the data stream when starting up. With Biphase-Level encoding there is a guaranteed clock transition at the center of every bit cell and optional data transitions at the bit cell boundaries. The DPLL only uses the clock transitions to track the bit cell boundaries, by ignoring all transitions occurring outside a window around the center of the bit cell. This window is half a bit-cell wide. Additionally, because the clock transitions are guaranteed, the DPLL requires that they always be present. If no transition is found in the window around the center of the bit cell for two successive bit cells the DPLL is not in lock and immediately enters the search mode. Search mode assumes that the next transition seen is a clock transition and immediately synchronizes to this transition. No clock output is provided to the receiver during the search operation. Decoding Biphase-Level data requires that the data be sampled at either the quarter or three-quarter point in the bit cell. The DPLL here uses the quarter point to sample the data. Biphase-Mark and Biphase space encoding are identical as far as the DPLL is concerned, and are similar to Biphase-Level. The primary difference is the placement of the clock and data transitions. With these encodings the clock transitions are at the bit-cell boundary and the data transitions are at the center of the bit cell, and the DPLL operation is adjusted accordingly. Decoding Biphase-Mark or Biphase-Space encoding requires that the data be sampled by both edges of the recovered receive clock. An optional IRDA (Infrared Data Association) -compliant encode and decode function is available in both asynchronous mode and HDLC mode. The encoder sends an active-High pulse for a zero and no pulse for a one. In the asynchronous 16x mode this pulse is 3/16ths of a bit cell wide, while in the asynchronous 8x mode it is 1/8th of a bit cell wide. In HDLC mode the pulse is 1/4th of a bit cell wide. In all modes the decoder watches for active-Low pulses, which are stretched to one bit time wide to recreate the normal asynchronous waveform for the receiver. Enabling the IRDA-compliant encode/decode modifies the transmitter in HDLC mode so that there are always two opening Flags transmitted. Users Manual 191 12.9 Serial Port Software Suggestions The receiver and transmitter share the same interrupt vector, but it is possible to make the receive and transmit interrupt service routines (ISRs) separate by dispatching the interrupt to either of two different routines. This is desirable to make the ISR less complex and to reduce the interrupt off time. No interrupts will be lost since distinct interrupt flip-flops exist for receive and transmit. The dispatcher can test the receiver data register full bit to dispatch. If this bit is on, the interrupt is dispatched for receive, otherwise for transmit. The receiver receives first consideration because it must be serviced attentively or data could be lost. The dispatcher might look as follows. interrupt: PUSH AF IOI LD A,(SCSR) JP m,receive ; 10 ; 7 get status register serial port C ; 7 go service the receive interrupt ; else service transmit interrupt The individual interrupts would assume that register AF has been saved and the status register has been loaded into Register A. The interrupt service routines can, as a matter of good practice and obtaining optimum performance, remove the cause of the interrupt and re-enable the interrupts as soon as possible. This keeps the interrupt latency down and allows the fastest transmission speed on all serial ports. All the serial ports will normally generate priority level 1 interrupts. In exceptional circumstances, one or more serial ports can be configured to use a higher priority interrupt. There is an exception to be aware of when a serial port has to operate at an extremely high speed. At 115,200 bps, the highest speed of a PC serial port, the interrupts must be serviced in 10 baud times, or 86 s, in order not to lose the received characters. If all six serial ports were operating at this receive speed, it would be necessary to service the interrupt in less than 21.5 s to assure no lost characters. In addition, the time taken by other interrupts of equal or higher priority would have to be considered. A receiver service routine might appear as follows below. The byte at bufptr is used to address the buffer where data bits are stored. It is necessary to save and increment this byte because characters could be handled out of order if two receiver interrupts take place in quick succession. receive: PUSH HL PUSH DE LD HL,struct LD A,(HL) LD E,A INC HL CMP A,(HL) JR Z,roverrun INC A AND A,mask DEC HL 192 ; ; ; ; ; ; ; ; ; ; ; 10 save HL 10 save DE 6 5 get in-pointer 2 save in pointer in E 2 point to out-pointer 5 see if in-pointer=out-pointer (buffer full) 5 go fix up receiver over run 2 incement the in pointer 4 mask such as 11110000 if 16 buffer locs 2 Rabbit 3000 Microprocessor LD (HL),A ; 6 update the in pointer IOI LD A,(SCDR) ; 11 get data register port C, clears interrupt request IPRES ; 4 restore the interrupt priority ; 68 clocks to here ; to level before interrupt took place ; more interrupts could now take place, ; but receiver data is in registers ; now handle the rest of the receiver interrupt routine LD HL,bufbase ; 6 LD D,0 ; 6 ADD HL,DE ; 2 location to store data LD (HL),A ; 6 put away the data byte POP DE ; 7 POP HL ; 7 POP AF ; 7 RET ; 8 from interrupt ; 117 clocks to here This routine gets the interrupts turned on in about 68 clocks or 3.5 s at a clock speed of 20 MHz. Although two characters may be handled out of order, this will be invisible to a higher level routine checking the status of the input buffer because all the interrupts will be completed before the higher level routine can perform a check on the buffer status. A typical way to organize the buffers is to have an in-pointer and an out-pointer that increment through the addresses in the data buffer in a circular manner. The interrupt routine manipulates the in-pointer and the higher level routine manipulates the out-pointer. If the in-pointer equals the out-pointer, the buffer is considered full. If the out-pointer plus 1 equals the in-pointer, the buffer is empty. All increments are done in a circular fashion, most easily accomplished by making the buffer a power of two in length, then anding a mask after the increment. The actual memory address is the pointer plus a buffer base address. 12.9.1 Controlling an RS-485 Driver and Receiver RS-485 uses a half-duplex method of communication. One station enables its driver and sends a message. After the message is complete, the station disables the driver and listens to the line for a reply. The driver must be enabled before the start bit is sent and not disabled until the stop bit has been sent. The transmitter idle interrupt is normally used to disable the RS-485 driver and possibly enable the receiver. 12.9.2 Transmitting Dummy Characters It may be desired to operate the serial transmitter without actually sending any data. Dummy characters are transmitted to pass time or to measure time. The output of the transmitter may be disconnected from the transmitter output pin by manipulating the control registers for Parallel Port C or D, which are used as output pins. For example, if Serial Port B is to be temporarily disconnected from its output pin, which is bit 4 of Parallel Port C, this can be done as follows. 1. Store a "1" in bit 4 of the parallel port data output register to provide the quiescent state of the drive line. Users Manual 193 2. Clear bit 4 of the Parallel Port C function register so that the output no longer comes from the serial port. Of course, this should not be done until the transmitter is idle. A similar procedure can be used if the serial port is set up to use alternate output pins on port D. Only Serial Ports A and B can use alternate outputs on Parallel Port D. If an RS-485 driver is being used, dummy characters can be transmitted by disabling the driver after the stop bit has been sent. This is an alternative to the above procedure. 12.9.3 Transmitting and Detecting a Break A break is created when the output of the transmitter is driven low for an extended period. If a break is received, it will appear as a series of characters filled with zeros and with the 9th bit detected low. This could only be confused with a legitimate message if a protocol using the 9th bit was in effect. Break is not usually used as a message in such protocols. A break can be transmitted by transmitting a byte of zeros at a very slow baud rate. Another and probably better method is to disconnect the transmitter from the output pin, and use the parallel port bit to set the line low while sending dummy characters to time out the break. The use of break as a signaling device should be avoided because it is slow, erratically supported by different types of hardware, and usually creates more problems than it solves. 12.9.4 Using A Serial Port to Generate a Periodic Interrupt A serial port may be used to generate a periodic interrupt by continuously transmitting characters. Since the Tx output via Parallel Port C or D can be disabled, the transmitted characters are transmitted to nowhere. Because the character output path is double-buffered, there will be no gaps in the character transmission, and the interrupts will be exactly periodic. The interrupts can happen every 9, 10 or 11 baud times, depending on whether 7 or 8 bits are transmitted and on whether the 9th (8th) bit is sent. 12.9.5 Extra Stop Bits, Sending Parity, 9th Bit Communication Schemes Some systems may require two stop bits. In some cases, it may be necessary to send a parity bit. Certain systems, such as some 8051-based multidrop communications systems, use a 9th data bit to mark the start of a message frame. The Rabbit 3000 can receive parity or message formats that contain a 9th bit without problem. Transmitting messages with parity or messages that always contain a 9th bit is also possible. It is quite easy to do so for byte formats that use only 7 data bits, in which case the 9th bit or parity bit is actually an 8th bit. Sending a 9th low bit is supported by hardware. Sending a 9th bit as a high value requires a write to the Serial Port A-F Long Stop Register (SxLR) which is the same as two stop bits. 194 Rabbit 3000 Microprocessor Figure 12-9 illustrates the standard asynchronous serial output patterns. stop bit 0 start bit data bits Character with 9th bit low 0 start bit Character w/o 9th bit low 0 start bit 7 9th bit high Generated by a Write to SxLR 7 stop bit 7 9th bit low stop bit Character w. 9th bit high Signal shown at output pin on processor. A 1 is high. Figure 12-9. Asynchronous Serial Output Patterns 12.9.6 Parity, Extra Stop Bits with 7-Data-Bit Characters If only 7 data bits are being sent, sending an additional parity or signal bit is easily solved by sending 8 bits and always setting bit 7 (the eighth bit) of the byte to "1" or 0 depending on what is desired. No special precautions are needed if two stop bits are to be received. If parity is received with 7 data bits, receive the data as 8 bits, and the parity will be in the high bit of the byte. 12.9.7 Parity, Extra Stop Bits with 8-Data-Bit Characters In order to receive parity with 8 data bits, a check is made on each character for a 9th bit low. The 9th bit, or parity bit, is low if bit 6 of the serial port status register (SxSR) is set to a "1" after the character is received. If the 9th bit is not a zero, then the serial port treats it as an extra stop bit. So if the 9th bit low flag is not set, it should be assumed that the parity bit is a "1." Setting the 9th bit high or low can easily be done in the Rabbit 3000. The 9th bit can be set low by a write to the Serial Port A-F Address Register (SxAR) and the 9th bit can be set high by a write to the Serial Port A-F Long Stop Register (SxLR). Users Manual 195 12.9.8 Supporting 9th Bit Communication Protocols This section describes how 9th bit communication protocols work. 9th bit communication protocols are supported by processors such as the 8051 and the Z180, and by companies such as Cimentrics Technology. The data bytes have an extra 9th bit appended where a parity bit would normally be placed. Requests from the network master to one of its slaves consist of a frame of bytesthe first byte has the 9th bit set to "1" (as the signal is observed at the Tx pin of the processor) and the following bytes have the 9th bit set to "0." The first byte is identified as the address byte, which specifies the slave unit where the message is directed. This enables a slave to find the start of a message, which is the byte with the 9th bit set, and to determine if the message is directed to it. If the message is directed to a particular slave, the slave will then read the characters in the rest of the message; otherwise the slave will continue to scan for a start of message character containing its address. Normally the 9th bit is set to "1" only on the first byte of a request transmitted by the network master. The subsequent bytes and the slave replies have the 9th bit set to zero. Since the majority of the traffic has a 9th bit set low, it is only necessary to stretch the stop bit for the first bytes or address bytes. This can be done without sacrificing performance by sending a dummy character (transmitter disconnected) after the address byte. Some microprocessor serial ports have a wake up mode of operation. In this mode, characters without the 9th bit set to "1" are ignored, and no interrupt is generated. When the start of a frame is detected, an interrupt takes place on that byte. If the byte contains the address of the slave, then the wake up mode is turned off so that the remaining characters in the frame can be read. This scheme reduces the overhead associated with messages directed to other slaves, but it does not really help with the worst-case load. In most cases, the worst-case compute load is the governing factor for embedded systems. In addition, it is quite easy for the interrupt driver to dismiss characters not directed to the system. For these reasons, the wake up mode was not implemented for the Rabbit. The 9th bit protocols suffer from a major problem that the IBM-PC uarts can support the 9th bit only by using special drivers. 12.9.9 Rabbit-Only Master/Slave Protocol If only Rabbit microprocessors are connected, the 9th bit low can be set on the address byte, and the remaining bytes can be transmitted in the normal 8-bit mode. This is more efficient than other 9th bit protocols because only the first byte requires 11 baud times; the remaining bytes are transmitted in 10 baud times. 12.9.10 Data Framing/Modbus Some protocols, for example, Modbus, depend on a gap in the data frame to detect the beginning of the next frame. The 9th bit protocol is another way to detect the start of a data frame. The Modbus protocol requires that data frames begin with a minimum 3.5-character quiet time. The receiver uses this 3.5-character gap to detect the start of a frame. In order for 196 Rabbit 3000 Microprocessor the receiving interrupt service routine to detect this gap, it is suggested that dummy characters be transmitted to help detect the gap. This can be done in the following manner. The transmitter starts transmitting dummy characters when the first character interrupt is received. Each time there is an interrupt, either receiver data register full or transmitter data register empty, a dummy character is transmitted if the transmitter data register is empty. Although the transmitter and receiver operate at approximately the same baud rate, there can be a difference of up to about 5% between their baud rates. Thus the receiver full and transmitter empty interrupts will become out of phase with each other, assuming that the remote station transmits without gaps between characters. A counter is zeroed each time a character is received, and the counter is incremented each time a character is transmitted. If this counter holds (n), this indicates that a gap has been detected in the frame; the length of the gap is (n - 1) to (n) characters. The start of frame could be marked by (n) reaching 3, indicating that the existence of a gap at least two characters long. Users Manual 197 198 Rabbit 3000 Microprocessor 13. RABBIT SLAVE PORT When a Rabbit microprocessor is configured as a slave, Parallel Port A and certain other data lines are used as communication lines between the slave and the master. The slave unit is a Rabbit configured as a slave. The master can be another Rabbit or any other type of processor. Rabbits configured as slaves can themselves have slaves. The master and slave communicate with each other via the slave port. The slave port is a physical device that includes data registers, a data bus and various handshaking lines. The slave port is a part of the slave Rabbit, but logically it is an independent device that is used to communicate between the two processors. A diagram of the slave port is shown in Figure 13-1. SPSR SPD2R 81-88 98 97 95 96 21 100 SD0-SD7 SA1 SA0 /SWR /SRD /SCS /SLAVEATTN SPD1R SPD0R CPU Figure 13-1. Rabbit Slave Port The slave port has three data registers for each direction of communication. Three registers, named SPD0R, SPD1R, and SPD2R, can be written by the master and read by the slave. Three different registers, also named SPD0R, SPD1R, and SPD2R, can be written by the slave and read by the master. The same names are used for different registers since it is usually clear from the context which register is meant. If it is necessary to distinguish between registers, we will refer to the registers as SPD0R writable by the slave or SPD0R writable by the master. Users Manual 199 A status register can be read by either the slave or the master. The status register has full/ empty bits for each of the six registers. A data register is considered full when it is written to by whichever side is capable of writing to it. If the same register is then read by either side it is considered to be empty. The flag for that register is thus set to a "1" when the register is written to, and the flag is set to a "0" when the register is read. The registers appear to be internal I/O registers to the slave. To the master, at least for a Rabbit master, the registers appear to be external I/O registers. The figure below shows the sequence of events when the master reads/writes the slave port registers. Slave Port Read Cycle /SCS Tsu(SCS) Th(SCS) SA1, SA0 Tsu(SA) Th(SA) /SRD Tw(SRD) SD[7:0] Ten(SRD) Ta(SRD) Tdis(SRD) /SWR Tsu(SWR SRD) Slave Port Write Cycle /SCS Tsu(SCS) Th(SCS) SA1, SA0 Tsu(SA) Th(SA) /SWR Tw(SWR) SD[7:0] Th(SD) Tsu(SD) /SRD Tsu(SRD SWR) Figure 13-2. Slave Port R/W Sequencing 200 Rabbit 3000 Microprocessor The following table explains the parameters used in Figure 13-2. Symbol Tsu(SCS) Th(SCS) Tsu(SA) Th(SA) Tw(SRD) Ten(SRD) Ta(SRD) Tdis(SRD) Parameter /SCS Setup Time /SCS Hold Time SA Setup Time SA Hold Time /SRD Low Pulse Width /SRD to SD Enable Time /SRD to SD Access Time /SRD to SD Disable Time Minimum (ns) 5 0 5 0 40 0 40 40 10 5 40 Maximum (ns) 30 15 Tsu(SRW SRD) /SWR High to /SRD Low Setup Time Tw(SWR) Tsu(SD) Th(SD) /SWR Low Pulse Width SD Setup Time SD Hold Time Tsu(SRD SWR) /SRD High to /SWR Low Setup Time The two SPD0R registers have special functionality not shared by the other data registers. If the master writes to SPD0R, an inbound interrupt flip-flop is set. If slave port interrupts are enabled, the slave processor will take a slave port interrupt. If the slave writes to the other SPD0R register, the slave attention line (/SLAVEATTN, pin 100) is asserted (driven low) by the slave processor. This line can be used to create an interrupt in the master. Either side that is interrupted can clear the signal that is causing an interrupt request by writing to the slave port status register. The data bits are ignored, but the flip-flop that is the source of the interrupt request is cleared. Figure 13-3 shows a logical schematic of this functionality. Users Manual 201 Master writes SPD0R Slave inbound interrupt requested Visible in status register Slave writes status register Slave writes SPD0R /SLAVEATTN (PB7) Visible in status register Master writes status register Figure 13-3. Slave Port Handshaking and Interrupts Figure 13-4 shows a sample connection of two slave Rabbits to a master Rabbit. The master drives the slave reset line for both slaves and provides the main processor clock from its own clock. There is no requirement that the master and slave share a clock, but doing so makes it unnecessary to connect a crystal to the slaves. Each Rabbit in Figure 13-4 has to have RAM memory. The master must also have flash memory. However, the slaves do not need nonvolatile memory since the master can cold boot them over the slave port and download their program. In order for this to happen, the SMODE0 and SMODE1 pins must be properly configured as shown in Figure 13-4 to begin a cold boot process at the end of the slave reset. 202 Rabbit 3000 Microprocessor Master Rabbit D0D7 /IORD /IOWR A0 A1 CLK portout INT0A /I7 INT1A /I6 First Slave Rabbit SD0SD7 /SRD /SWR SA0 SA1 SMODE0 /XTALB1 SMODE1 /RESET /SLAVEATTN /SCS + Second Slave Rabbit + Reset Pulldown /SLAVEATTN /SCS SMODE0 SMODE1 Figure 13-4. Typical Connection Slave Rabbit to Master Rabbit The slave port lines are shown in Figure 13-1. The function of these lines is described below. SD0SD7These are bidirectional data lines, and are generally connected to the data bus of the master processor. Multiple slaves can be connected to the data bus. The slave drives the data lines only when /SCS and /SRD are both pulled low. SA1, SA0These are address lines used to select one of the four data registers of the slave interface. Normally these lines are connected to the low-order address lines of the master. The master always drives these lines which are always inputs to the slave. /SCSInput. Slave chip select. The slave ignores read or write requests unless the chip select is low. If a Rabbit is used as a master, this line can be connected to one of the masters programmable chip select lines /I0/I7. /SRDInput. If /SCS is also low, this line pulled low causes the contents of the register selected by the address lines to be driven on the data bus. If a Rabbit is used as a master, this line is normally connected to the global I/O read strobe /IORD. /SWRInput. If /SCS is also low, this line causes the data bits on the data bus to be clocked into the register selected by the address lines on the rising edge of /SWR or /SCS, whichever rises first. If a Rabbit is used as a master, this line is normally connected to the global I/O write strobe /IOWR. Users Manual 203 /SLAVEATTNThis line is set low (asserted) if the slave writes to the SPD0R register. This line is set high if the master writes anything to the slave status register. This line is usually connected to cause the master to be interrupted when it goes low. The data lines of the slave port are shared with Parallel Port A that uses the same package pins. The slave port can be enabled, and Parallel Port A be disabled, by storing an appropriate code in the slave port control register (SCR). After the processor is reset, all the pins belonging to the slave interface are configured as parallel-port inputs unless (SMODE1, SMODE0) are set to (0,1), in which case the slave port is enabled after reset and the slave starts the cold-boot sequence using the slave port. 13.1 Hardware Design of Slave Port Interconnection Figure 13-4 shows a typical circuit diagram for connecting two slave Rabbits to a master Rabbit. The designer has the option of cold-booting the slave and downloading the program to RAM on each cold start. Another option is to configure the slave with both RAM and flash memory. In this case, the slave will only have the program downloaded for maintenance or upgrades. Usually, the flash would not be written to on every startup because of the limited number of lifetime writes to flash memory. The slaves reset in Figure 13-4 is under the program control of the master. If the master is reset, the slave will also be reset because the masters drive of the reset line will be lost on reset and the pulldown resistor will pull the slaves resets low. This may be undesirable because it forces the slave to crash if the master crashes and has a watchdog timeout. 13.2 Slave Port Registers The slave port registers are listed in Table 13-1. These registers, each of which is actually two separate registers, one for read and one for write, are accessible to the slave at the I/O addresses shown in the table and they are accessible to the master at the external address shown which specifies the value of the slave address (SA0, SA1) input to the slave when the master reads or writes the registers. The register that can be written by the slave can only be read by the master and vice versa. If one side were to attempt to read a register at the same time that the other side attempted to write the register the result of the read could be scrambled. However, the protocols and handshaking bits used in communication are normally such that this never happens. Table 13-1. Slave Port Registers Register Slave Port Data 0 Register Slave Port Data 1 Register Slave Port Data 2 Register Slave Port Status Register Slave Port Control Register Mnemonic SPD0R SPD1R SPD2R SPSR SPCR Internal Address 0x20 0x21 0x22 0x23 0x24 0 1 2 3 N.A. External Address 204 Rabbit 3000 Microprocessor If the user for some reason wants to depart from the suggested protocols and poll a register while waiting for the other side to write something to the register, the user should be aware that all the bits might not change at the exact same time when the result changes, and a transitional value could be read from the register where some bits have changed to the new value and others have not. To avoid being confused by a transitional value, the user can read the register twice and make sure both values are the same before accepting the value, or the user can test only one bit for a change. The transitional value can only exist for one read of the register, and each bit will have its old value change to the new value at some point without wavering back and forth. The existence of a transitional value could be very rare and has the potential to create a bug that happens often enough to be serious, but so infrequently as to be difficult to diagnose. Thus, the user is cautioned to avoid this situation. Table 13-2 describes the slave port control register. Table 13-2. Slave Port Control Register (SPCR) (adr = 0x024) Bit 7 (Write Only) Bits 6,5 (Read Only) Bit 4 Bit 3,2 (Write Only) 00disable slave port, port A is a byte wide input port 01disable slave port, port A is a byte wide output port 10enable the slave port 11Enable the auxilliary I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:2] is used for the address bus. Bits 1,0 (Write Only) 00no slave interrupt ppenable slave port interrupt 01 priority 1 10 priority 2 11 priority 3 0obey SMODE Reads SMODE pins pins 1ignore SMODE smode1,smode0 pins x The functionality of the bits is as follows: Bit 7If set to "0," the cold-boot feature will be enabled. Normally this bit is set to a "1" after the cold boot is complete. The cold boot for the slave port is enabled automatically if (SMODE1, SMODE0) lines are set to (0,1) after the reset ends. This features disables the normal operation of the processor and causes commands to be accepted via the slave port register SPD0R. These commands cause data to be stored in memory or I/O space. When the master that is managing the cold boot has finished setting up memory and I/O space, the (SMODE1, SMODE0) pins are changed to code (0,0), which causes execution to start at address zero. Typically this will start execution of a secondary boot program. At some point, bit 7 will be set to a "1" so that the SMODEx pins can be used as normal input pins. Bits 6,5May be used to read the input pins SMODE, SMODE0. Bits 3,2A 10 written to bits 3,2 enables the slave port disabling Parallel Port A and various other port lines. Bits 3,2 are automatically set to a "10" if a cold boot is done via the slave port. If bit 3 is "0," then bit 2 controls whether Parallel Port A is an input (bit 2 = 0) or an output (bit 2 = 1). A 11 written to bits 3,2 enables the Auxilliary I/O bus. Users Manual 205 Bits 1,0This 2-bit field sets the priority of the slave port interrupt. The interrupt is disabled by (0,0). Table 13-3 describes the slave port status register. The status register has 6 bits that are set if the particular register is full. That means that the register has been written by the processor that can write to it but it has not been read by the processor that can read it. The bits for SPD0R are used to control the slave interrupt and the handshaking lines as shown in Figure 13-3. Table 13-3. Slave Port Status Register (SPSR) (adr = 0x023) Bit 7 1set by master write to SPD0R. Cleared by slave write to SPSR. Bit 6 1set by master write to SPD2R. Cleared when slave reads register. Bit 5 1set by master write to SPD1R. Cleared when slave reads register. Bit 4 1set by master write to SPD0R. Cleared when slave reads register. Bit 3 1set by slave write to SPD0R. Cleared by master write to SPSR. Bit 2 1set by slave write to SPD2R. Cleared when master reads register. Bit 1 1set by slave write to SPD1R. Cleared when master reads register. Bit 0 1set by slave write to SPD0R. Cleared when master reads register. 13.3 Applications and Communications Protocols for Slaves The communications protocol used with the slave port depends on the application. A slave processor may be used for various reasons. Some possible applications are listed below. Keep in mind that the Rabbit can also be operated as a slave processor via a serial port and some of the protocols will work well via a serial communications connection. If a serial connection is used, the protocol becomes more complicated if errors in transmission need to be taken into account. If the physical link can be controlled so that transmission errors do not occur, a realistic possibility if the interconnection environment is controlled, the serial protocol is simpler and faster than if error correction needs to be taken into account. 13.3.1 Slave Applications Motion ControllerMany types of motion control require fast action, may be compute-intensive or both. Traditional servo system solutions may be overly expensive or not work very well because of system nonlinearities. The basic communications model for a motion controller is for the master to send short messagespositioning commandsto the slave. The slave acknowledges execution of the commands and reports exception conditions. Communications Protocol ProcessorCommunications protocols may be very complex, may require fast responses, or may be compute-intensive. Graphics ControllerThe Rabbit can be used to perform operations such as drawing geometric figures and generating characters. Digital Signal ProcessingAlthough the Rabbit is not a speciality digital signal processor, it has enough compute speed to handle some types of jobs that might otherwise 206 Rabbit 3000 Microprocessor require a speciality processor. The slave processor can process data to perform pattern recognition or to extract a specific parameter from a data stream. 13.3.2 Master-Slave Messaging Protocol In this protocol the master sends messages to the slave and receives an acknowledgement message. The protocol can be polled or interrupt driven. Generally, the master sends a message that has a message type code, perhaps a byte count, and the text of the message. The slave responds with a similar message as an acknowledgement. Nothing happens unless the master sends a message. The slave is not allowed to initiate a message, but the slave could signal the master by using a parallel port line other than /SLAVEATN or by placing data in one of the registers the master can read without interfering with the message protocol. The master sends a message byte by storing it in SPD0R. The slave notices that SPD0R is full and reads the byte. When the master notices that SPD0R is empty because the slave read it, the master stores the next byte in SPD0R. Either side can tell if any register is empty or full by reading the status register. When the slave acknowledges the message with a reply message, the process is reversed. To perform the protocol with interrupts, a slave interrupt can be generated each time the slave receives a character. The slave can acknowledge the master by reading SPD0R if the master is polling for the slave response to each character. If the master is to be interrupted to acknowledge each character, the slave can create an interrupt in the master by storing a dummy character in SPD0R to create a master interrupt, assuming that the /SLAVEATTN line is wired to interrupt the master. The acknowledgement message works in a similar manner, except that the master writes a dummy character to interrupt the slave to say that it has the character. Several problems can arise if there are dual interrupts for each character transmitted. One problem is that the message transmission rate will free run at a speed limited by the interrupt latency and compute speed of each processor. This could consume a high percentage of the compute resources of one or both processors, starving other processes and especially interrupt routines, for compute time. If this is a problem, then a timed interrupt can be used to drive the process on one side, thus limiting the data transmission rate. Another solution, which may be better than limiting the transmission rate, is to use interrupts only for the first byte of the message on the slave side, and then lower the interrupt priority and conduct the rest of the transaction as a polled transaction. On the master side the entire transaction can be a polled transaction. In this case, the entire transaction takes place in the interrupt routine on the slave, but other interrupts are not inhibited since the priority has been lowered. A typical slave system consists of a Rabbit microprocessor and a RAM memory connected to it. The clock can be provided either by connecting a crystal, or crystals to the slave or by providing an external clock, which could be the masters clock. The reset line of the slave would normally be driven by the master. At system startup time the master resets the slave and cold boots it via the slave port. (The SMODE pins must be configured Users Manual 207 for this.) Once the software is loaded into the slave, the slave can begin to perform its function. As a simple example, suppose that the slave is to be used as a four-port UART. It has the capability to send or receive characters on any of its four serial ports. Leaving aside the question of setup for parameters, such as the baud rate, we could define a protocol as follows. SPD0R readable by master is a status register with bits indicating which of the four receivers and four transmitters is ready, that is, has a character received or is ready to send a character. SPD0R writable by the master is a control register used to send commands to the slave. SPD1R is used to send or receive data characters or control bytes. The line /SLAVEATTN is wired to the external interrupt request of the master so that the master is interrupted when the slave writes to SPD0R. Typically the slave will write to SPD0R when there is a change of status on one of the serial ports. The slave can interrupt the master at any time by storing to SPD0R. It will do this every time an enabled transmitter is ready to accept a character or every time an enabled receiver receives a character. When it stores to SPD0R, it will store a code indicating the reason for the interrupt, that is, receive or transmit and channel number. If the cause is receive, the received character will also be placed in SPD1R writable by the slave. When the master is interrupted for any reason, the master will sneak a peek at SPD0R by reading SPSR. If the interrupt is caused by a receive character, it will remove the character from SPD1R and read SPD0R to handshake with the slave. If the master is interrupted for transmitter ready, as determined by the sneak peek, it will place the outgoing character in SPD1R and write a code to SPD0R indicating transmit and channel number. This will cause the slave to be interrupted, and the slave will take the character and handshake by reading SPD0R. This handshake does not interrupt the master. 208 Rabbit 3000 Microprocessor 14. RABBIT 3000 CLOCKS The Rabbit 3000 normally uses two clocks, the main clock and the 32.768 kHz clock. The 32.768 kHz clock is needed for the battery-backable clock, the watchdog timer, and the cold-boot function. The main oscillator provides the run-time clock for the microprocessor. Figure 14-1 shows the main oscillator circuit. TN235, External 32.768 kHz Oscillator Circuits, provides further information on the 32.768 kHz oscillator circuit and selecting the values of components to use in the oscillator circuit. XTALB2 2 kW 33 pF 1 MW 11.0592 MHz XTALB1 33 pF Main Oscillator Circuit Figure 14-1. Rabbit 3000 Main Oscillator Circuit NOTE: You may have to adjust resistors and capacitors for various frequencies and crystal load capacitances. The 32.768 kHz oscillator is slow to start oscillating after power-on. For this reason, a wait loop in the BIOS waits until this oscillator is oscillating regularly before continuing the startup procedure. If the clock is battery-backed, there will be no startup delay since the oscillator is already oscillating. The startup delay may be as much as 5 seconds. Crystals with low series resistance (R < 35 k) will start faster. Users Manual 209 14.1 Low-Power Design The power consumption is proportional to the clock frequency and to the square of the operating voltage. Thus, operating at 3.3 V instead of 5 V will reduce the power consumption by a factor of 10.9/25, or 43% of the power required at 5 V. The clock speed is reduced proportionally to the voltage at the lower operating voltage. Thus the clock speed at 3.3 V will be about 2/3 of the clock speed at 5 V. The operating current is reduced in proportion to the operating voltage. The Rabbit 3000 does not have a "standby" mode that some microprocessors have. Instead, the Rabbit has the ability to switch its clock to the 32.768 kHz oscillator. This is called the sleepy mode. When this is done, the power consumption is decreased dramatically. The current consumption is often reduced to the region of 100 A at this clock speed. The Rabbit executes about 6 instructions per millisecond at this low clock speed. Generally, when the speed is reduced to this extent, the Rabbit will be in a tight polling loop looking for an event that will wake it up. The clock speed is increased to wake up the Rabbit. 210 Rabbit 3000 Microprocessor 15. EMI CONTROL EMI or electromagnetic interference from unintentional radiation is of concern to the microprocessor system designer. One concern is passing the tests sometimes required by the U.S. Federal Communications Commission (FCC) or by the European EMC Directive. For example, in the U.S. the FCC requires that computing devices intended for use in the home or in office environments (but not industrial or medical environments) not have unintentional electromagnetic radiation above certain limits of field strength that depend on frequency and whether the device is intended for home or office use. This is verified by measuring radiation from the device at a test site. The device under test (DUT) is operated in a typical fashion with a typical mechanical and electrical configuration while the electromagnetic radiation is measured by a calibrated antenna located either 3 or 10 m from the device. The output of the antenna is connected to a spectrum analyzer. For the purposes of the test, the spectral power is measured by using a filter with a bandwidth of 120 kHz. The peak power is measured by using a quasi peak detector in the spectrum analyzer. The quasi peak detector has a charge time constant of 1 ms and a discharge time constant of 550 ms. In this manner the peak radiated signal strength is measured. The tests required by the FCC and the EC are practically identical. The Rabbit 3000 has important features that aid in the control if EMI. The power supply for the processor core is on separate pins from the power supply for the I/O buffers associated with the processor and various peripheral devices. A spectrum spreader in the clock circuit can be enabled to spread the spectrum of the clock by varying the clock frequency in a regular pattern. The built in clock doubler allows the external oscillator circuitry to operate at 1/2 the ultimate clock frequency. In most cases it is not necessary to route the system clock outside the package, although a pin is provided for this purpose in the unusual circumstances where it might be necessary. The high speed clock on PC board traces is a major cause of EMI. If all the EMI suppression features of the Rabbit 3000 are properly utilized and low EMI design techniques are used on the printed circuit board, system EMI will likely be reduced to a very low level, probably much lower than is necessary to pass government tests. Users Manual 211 15.1 Power Supply Connections and Board Layout Refer to Technical Note TN221, PC Board Layout Suggestions for the Rabbit 3000 Microprocessor, for recommendations on laying out a PC board to minmize EMI emsissions. 15.2 Using the Clock Spectrum Spreader The spectrum spreader is very powerful for reducing EMI because it will reduce all sources of EMI above 100 MHz that are related to the clock by about 15 dB. This is a very large reduction since it is common to struggle to reduce EMI by 5 dB in order to pass government tests. 15dB Strong Spreading 10 Normal Spreading 5 50 100 150 200 MHz 250 300 350 Figure 15-1. Peak Spectral Amplitude Reduction from Spectrum Spreader The spectrum spreader modulates the clock so as to spread out the spectrum of the clock and its harmonics. Since the government tests use a 120 kHz bandwidth to measure EMI, spreading the energy of a given harmonic over a wider bandwidth will decrease the amount of EMI measured for a given harmonic. The spectrum spreader not only reduces the EMI measured in government tests, but it will also often reduce the interference created for radio and television reception. The spectrum spreader has three settings under software control (see Table 15-1 and Table 15-2): off, standard spreading and strong spreading. Two registers control the clock spectrum spreader. These registers must be loaded in a specific manner with proper time delays. GCM0R is only read by the spectrum spreader at the moment when the spectrum spreader is enabled by storing 0x080 in GCM1R. If GCM1R is cleared (when disabling the spectrum spreader), there is up to a 500-clock delay before the spectrum spreader is actually disabled. The proper procedure is to clear GCM1R, wait for 500 clocks, set GCM0R, and then enable the spreader by storing 0x080 in GCM1R. 212 Rabbit 3000 Microprocessor Table 15-1. Spread Spectrum Enable/Disable Register Global Clock Modulator 0 Register Bit(s) 7 1 6:0 Enable strong spectrum spreading. These bits are reserved. Value 0 (GCM0R) Description Enable normal spectrum spreading. (Address = 0x0A) Table 15-2. Spread Spectrum Mode Select Global Clock Modulator 1 Register Bit(s) 7 1 6:0 Enable the spectrum spreader. These bits are reserved. Value 0 Disable the spectrum spreader. (GCM1R) Description (Address = 0x0B) When the spectrum spreader is engaged, the frequency is modulated, and individual clock cycles may be shortened or lengthened by an amount that depends on whether the clock doubler is engaged and whether the spectrum spreader is set to the normal or strong setting. The frequency modulation amplitude and the change in clock cycle length is greater at lower voltages or higher temperatures since it is sensitive to process parameters. The spectrum spreader also introduces a time offset in the system clock edge and an equal offset in edges generated relative to the system clock. A feedback system limits the worst case time error of any signal edge derived from the system clock to plus or minus 20 ns for the normal setting and plus or minus 40 ns for the strong setting at 3.3 V. The maximum time offset is inversely proportional to operating voltage. The time error will not usually interfere with communications channels, except perhaps at the extreme upper data rates. More details on dealing with the clock variation introduced are available elsewhere (see Chapter 16, AC Timing Specifications). If the input oscillator frequency is 4 MHz or less the spectrum spreader modulation of frequency will enter the audio range of 20 kHz or less and may generate an audible whistle in FM stations. For this reason it may be desirable to disable the spreader for low speed oscillators (where it is probably unnecessary anyway). However, in practical cases the whistle may not be audible due to the very low level of the interference from a system with low oscillator frequency and the spectrum spreader engaged. Each halving of clock frequency reduces the amplitude of the harmonics at a given frequency by 6 dB or more. The effect of pure harmonic noise on an FM station is to either completely block out a station near the harmonic frequency or to disturb reception of that station. If the spectrum spreader is engaged then interference will be spread across the band but will generally be Users Manual 213 so low as to be undetectable, except perhaps for extremely weak stations. The effect of a pure harmonic on TV reception is to create a herringbone pattern created by a harmonic falling within the stations band. If the spreader is engaged the pattern will disappear unless the station is very weak, in which case the interference will be seen as noise distributed over the screen. 214 Rabbit 3000 Microprocessor 16. AC TIMING SPECIFICATIONS The Rabbit 3000 processor may be operated at voltages between 1.8 V and 3.6 V, and at temperatures from 40C to +85C with use possible use over the extended range -55C to +105C. For long life it is desirable not to exceed a die temperature of 125C. Most users will operate the Rabbit at 3.3 V. 16.1 Memory Access Time Required memory address and output enable access time for some important typical cases are given in the table below. It is assumed that the clock doubler is used, that the clock spreader is enabled in the normal mode, that the memory early output enable is on, and that the address bus has 60 pF load. Table 16-1. Memory Requirements at 3.3 V, -40C to +85C, Adr Bus 60 pF Clock Frequency (MHz) 18.43 22.11 24.00 25.80 29.49 44.24 Period (ns) 54 45 42 39 34 22.5 Clock Doubler Memory Address Memory Output Nominal Delay Access Enable Access (ns) (ns) (ns) 20 20 19 17 16 10 97 78 72 66 56 33.5 60 51 45 43 37 22 All important signals on the Rabbit 3000 are output synchronized with the internal clock. The internal clock is closely synchronized with the external clock (CLK) that may be optionally output from pin 2 of the TQFP package. The delay in signal output depends on the capacitive load on the output lines. In the case of the address lines, which are critically important for establishing memory access time requirements, the capacitive loading is usually in the range of 25100 pF, and the load is due to the input capacitance of the memory devices and PC trace capacitance. Delays are expressed from the waveform midpoint in keeping with the convention used by memory manufacturers. Users Manual 215 Figure 16-1 illustrates the parameters used to describe memory access time. delay capacitive loading setup time data to clock Figure 16-1. Parameters Used to Describe Memory Access Time Table 16-2 lists the delays in gross memory access time for several values of VDD. Table 16-2. Data and Clock Delays VDD 10%, Temp, -40C+85C (maximum) Clock to Address Output Delay (ns) VDD 30 pF 3.3 2.7 2.5 1.8 6 7 8 18 60 pF 8 10 11 24 90 pF 11 13 15 33 Data Setup Time Delay (ns) 1 1.5 1.5 3 Spectrum Spreader Delay (ns) Normal no dbl/dbl 3/4.5 3.5/5.5 4/6 8/12 Strong no dbl/dbl 4.5/9 5.5/11 6/12 11/22 When the spectrum spreader is enabled with the clock doubler, every other clock cycle is shortened (sometimes lengthened) by a maximum amount given in the table above. The shortening takes place by shortening the high part of the clock. If the doubler is not enabled, then every clock is shortened during the low part of the clock period. The maximum shortening for a pair of clocks combined is shown in the table. 216 Rabbit 3000 Microprocessor Figure 16-2 and Figure 16-3 illustrate the memory read and write cycles. The Rabbit 3000 operates at 2 clocks per bus cycle plus any wait states that might be specified. Memory Read (no wait states) T1 T2 CLK A[19:0] Tadr valid /CSx /OEx D[7:0] TCSx TCSx TOEx Tsetup valid Thold TOEx Memory Write (no extra wait states) T1 Tw T2 CLK A[19:0] /CSx /WEx D[7:0] Tadr TCSx TCSx valid TWEx TWEx valid TDHZV TDVHZ Figure 16-2. Memory Read and Write Cycles Users Manual 217 The following memory read time delays were measured. Table 16-3. Memory Read Time Delays Output Capacitance Time Delay 30 pF Max. clock to address delay (Tadr) Max. clock to memory chip select delay (TCSx) Max. clock to memory read strobe delay (TOEx) Min. data setup time (Tsetup) Min. data hold time (Thold) 6 ns 6 ns 6 ns 60 pF 8 ns 8 ns 8 ns 1 ns 0 ns 90 pF 11 ns 11 ns 11 ns The measurements were taken at the 50% points under the following conditions. T = -40C to 85C, V = 3.3 V Internal clock to nonloaded CLK pin delay 1 ns @ 85C/3.0 V The following memory write time delays were measured. Table 16-4. Memory Write Time Delays Output Capacitance Time Delay 30 pF Max. clock to address delay (Tadr) Max. clock to memory chip select delay (TCSx) Max. clock to memory write strobe delay (TWEx) Max. high Z to data valid rel. to clock (TDHZV) Max. data valid to high Z rel. to clock (TDVHZ) 6 ns 6 ns 6 ns 10 ns 10 ns 60 pF 8 ns 8 ns 8 ns 12 ns 12 ns 90 pF 11 ns 11 ns 11 ns 15 ns 15 ns The measurements were taken at the 50% points under the same conditions that the memory read delays were measured. See Table 16-2 for delays at other voltages. 218 Rabbit 3000 Microprocessor Memory Read (no wait states) T1 T2 CLK A[19:0] Tadr valid /CSx /OEx D[7:0] TCSx TCSx TOEx Tsetup valid Thold TOEx Memory Write (no extra wait states) T1 Tw T2 CLK A[19:0] /CSx /WEx D[7:0] Tadr TCSx TCSx valid TWEx TWEx valid TDHZV TDVHZ Figure 16-3. Memory Read and Write CyclesEarly Output Enable and Write Enable Timing Users Manual 219 Figure 16-4 illustrates the sources that create memory access time delays. clock period shortening due to spectrum spreader clock address data out clock to address output data in setup time memory access time output enable (early) memory output enable time Figure 16-4. Sources of Memory Access Time Delays The gross memory access time is 2T, where T is the clock period. To calculate the actual memory access time, subtract the clock to address output time, the data in setup time, and the clock period shortening due to the clock spectrum spreader from 2T. Example clock = 29.49 MHz, T = 34 ns, operating voltage is 3.3 V, bus loading is 60 pF, address to output time = 8 ns (see Table 16-2), data setup time = 1 ns, the spectrum spreader is on in normal mode, resulting in a loss of 3 ns. The access time is given by access time = 2T - (clock to address) - (data setup) - (spreader delay) = 68 ns - 8 ns - 1 ns - 3 ns = 56 ns 220 Rabbit 3000 Microprocessor The required memory output enable access time is more complicated since it is affected by the clock doubler delays. The clock doubler setup register creates a nominal delay time ranging from 6 to 20 ns, resulting in a nominal clock low time ranging from 6 to 20 ns. The clock low time depends on internal delays, and is subject to variation arising from process variation, operating voltage and temperature. Minimum and maximum clock low times for various doubler settings are given in the formulas and in the graph below. Max. delay @ 3.3 V = 6.1 + 1.21(n - 6) Min. delay @ 3.3 V = 3.7 + 0.75(n - 6) Max. delay @ 2.5 V = 7.6 + 1.67(n - 6) Min. delay @ 2.5 V = 4.7 + 1.03(n - 6) Max. delay @ 1.8 V = 12.2 + 2.7(n - 6) Min. delay @ 1.8 V = 6.6 + 1.44(n - 6) [n is the nominal delay, 620 ns) 60.0 50.0 40.0 Delay (ns) 3.3 V 30.0 2.5 V 1.8 V 20.0 10.0 0.0 0 5 10 15 20 25 Nominal Delay (ns) Figure 16-5. Clock Doubler Max-Min Clock Low Times Users Manual 221 The following factors have to be taken into account when calculating the output enable access time required. The gross output enable access time is T + minimum clock low time (it is assumed that the early output enable option is enabled) This is reduced by the spectrum spreader loss, the time from clock to output for the output enable signal, the data setup time, and a correction for the asymmetry of the original oscillator clock. Example Clock = 29.49 MHz, T = 34 ns, operating voltage is 3.3 V, the clock doubler has a nominal delay of 16 ns, resulting in a minimum clock low time of 12.8 ns, the spectrum spreader is on in normal mode, resulting in a loss of 3 ns, clock to output enable is 5 ns (assuming 20 pF load), the clock asymmetry is 52-48, resulting in a loss of 4% of the clock period, or 1.4 ns. The output enable access time is given by access time = T + (min. clock low) - (clock to output enable) - (spreader delay) - (asymmetry delay) - (data setup time) = 34 ns + 12.8 ns - 5 ns - 3 ns - 1.36 ns - 1 ns = 36.5 ns 222 Rabbit 3000 Microprocessor 16.2 I/O Access Time Figure 16-6 illustrates the I/O read and write cycles. External I/O Read (no extra wait states) T1 Tw T2 CLK A[15:0] Tadr valid /CSx /IOCSx /IORD /BUFEN D[7:0] TCSx TCSx TIOCSx TIOCSx TIORD TIORD TBUFEN TBUFEN Tsetup valid Thold External I/O Write (no extra wait states) T1 Tw T2 CLK A[15:0] Tadr valid /CSx /IOCSx /IOWR /BUFEN D[7:0] TCSx TCSx TIOCSx TIOCSx TIOWR TIOWR TBUFEN valid TDHZV TBUFEN TDVHZ Figure 16-6. I/O Read and Write CyclesNo Extra Wait States NOTE: /IOCSx can be programmed to be active low (default) or active high. Users Manual 223 The following I/O read time delays were measured. Table 16-5. I/O Read Time Delays Output Capacitance Time Delay 30 pF Max. clock to address delay (Tadr) Max. clock to memory chip select delay (TCSx) Max. clock to I/O chip select delay (TIOCSx) Max. clock to I/O read strobe delay (TIORD) Max. clock to I/O buffer enable delay (TBUFEN) Min. data setup time (Tsetup) Min. data hold time (Thold) 6 ns 6 ns 6 ns 6 ns 6 ns 60 pF 8 ns 8 ns 8 ns 8 ns 8 ns 1 ns 0 ns 90 pF 11 ns 11 ns 11 ns 11 ns 11 ns The measurements were taken at the 50% points under the following conditions. T = -40C to 85C, V = 3.3 V Internal clock to nonloaded CLK pin delay 1 ns @ 85C/3.0 V The following I/O write time delays were measured. Table 16-6. I/O Write Time Delays Output Capacitance Time Delay 30 pF Max. clock to address delay (Tadr) Max. clock to memory chip select delay (TCSx) Max. clock to I/O chip select delay (TIOCSx) Max. clock to I/O write strobe delay (TIOWR) Max. clock to I/O buffer enable delay (TBUFEN) Max. high Z to data valid rel. to clock (TDHZV) Max. data valid to high Z rel. to clock (TDVHZ) 6 ns 6 ns 6 ns 6 ns 6 ns 10 ns 10 ns 60 pF 8 ns 8 ns 8 ns 8 ns 8 ns 12 ns 12 ns 90 pF 11 ns 11 ns 11 ns 11 ns 11 ns 15 ns 15 ns The measurements were taken at the 50% points under the same conditions that the I/O read delays were measured. I/O bus cycles have an automatic wait state and thus require 3 clocks plus any extra wait states specified. See Table 16-2 for delays at other voltages. 224 Rabbit 3000 Microprocessor 16.3 Further Discussion of Bus and Clock Timing The clock doubler is normally used, except in situations where low-frequency systems are specifically being used. The clock doubler works by oring the clock with a delayed version of itself. The nominal delay varies from 6 to 20 ns, and is settable under program control. Any asymmetry in the oscillator waveform before it is doubled will result in alternate clocks having slightly different periods. Using the suggested oscillator circuit, the asymmetry is no worse than 52%48%. This results in a given clock being shortened by the ratio 50/52, or 4%. Memory access time is not affected because memory bus cycle is 2 clocks long and includes both a long and a short clock, resulting in no net change due to asymmetry. However, if an odd number of wait states is used, then the memory access time will be affected slightly. When the clock spectrum spreader is enabled, clock periods are shortened by a small amount depending on whether the normal or the strong spreader setting is used, and depending on the operating voltage. If the clock doubler is used, the spectrum spreader affects every other cycle and reduces the clock high time. If the doubler is not used, then the spreader affects every clock cycle, and the clock low time is reduced. Of course, the spectrum spreader also lengthens clock cycles, but only the worst case shortening is relevant for calculating worst case access times. The numbers given for clock shortening with the doubler disabled are the combined shortening for 2 consecutive clock cycles, worst case. In computing memory requirements, the important considerations are address access time, output enable access time, and minimum write pulse required. Increasing the clock doubler delay increases the output enable time, but decreases memory write pulse width. The early write pulse option can be used to ensure a long-enough write pulse, but then it must be ensured that the write pulse does not begin before the address lines have stabilized. Users Manual 225 P Oscillator Oscillator delayed and inverted Doubled clock Delay time 0.48P 0.52P 0.48P 0.52P 48% 52% Example Write Cycle address, /CS Data out write pulse early write pulse option address, /CS Example Read Cycle Valid data out from mem output enb early output enb option Figure 16-7. Clock Doubler and Memory Timing 226 Rabbit 3000 Microprocessor 16.4 Maximum Clock Speeds The Rabbit 3000 is rated for a minimum clock period of 17 ns (commercial specifications) and 18 ns (industrial specifications). The commercial rating calls for a 5% voltage variation from 3.3 V and a temperature range from -40 to + 70C. The industrial ratings stretch the voltage variation to 10% and a temperature range from -40 to + 85C. This corresponds to maximum clock frequencies of 58.8 MHz (commercial) and 55.5 MHz (industrial). If the clock doubler or spectrum spreader is used, these maximum ratings must be reduced as shown in the following table. When the doubler is used, the duty cycle of the clock becomes a critical parameter. The duty cycle should be measured at the separate clock output pin (pin 2). The minimum period must be increased by any amount that the clock high time is greater or less than specified in the duty-cycle requirement. Table 16-7. Maximum Clock Speeds at 3.3 V [Preliminary] Commercial Ratings Conditions Minimum Period (ns) 17 20 21 19 Maximum Frequency (MHz) 58.8 50.0 47.6 52.6 Industrial Ratings Minimum Period (ns) 18 21 22 20 Maximum Frequency (MHz) 55.5 47.6 45.4 50.0 1 > (clock low clock high) > 0 1 > (clock low clock high) > -1 Duty Cycle Requirements (ns) No doubler or spreader Spreader only normal Spreader only strong Doubler only (8 ns delay) Doubler only (internal 50% clock) Spreader normal with doubler (8 ns delay) Spreader normal with doubler (8 ns delay), internal 50% clock Spreader only strong Spreader strong with doubler (8 ns delay) 20 50 21 47.6 21 47.6 22 45.4 4 > (clock low clock high) > 2 24 41.6 25 40.0 1 > (clock low clock high) > -1 21.5 46.5 22.5 45.0 8 > (clock low clock high) > 6 23 43.5 24 41.6 Users Manual 227 Example The spreader and doubler are enabled, with 8 ns nominal delay in the doubler. The high and low clock are equal to within 1 ns. This violates the duty cycle requirement by 3 ns since (clock low - clock high) can be as small as -1 ns, but the requirement is that it not be less than 2 ns. Thus, 3 ns must be added to the minimum period of 21 ns, giving a minimum period of 24 ns, and a maximum frequency of 41.6 MHz (commercial). Since the built-in high-speed oscillator buffer generates a clock that is very close to having a 50% duty cycle, to obtain the highest clock speeds using the clock doubler you must use an external oscillator buffer that will allow for duty-cycle adjustment by changing the resistance of the power and ground connections as shown below. +3.3 V Adjust the values of these resistors to vary the duty cycle XTALA1 Figure 16-8. External Oscillator Buffer 228 Rabbit 3000 Microprocessor 16.5 Power and Current Consumption With the Rabbit 3000 it is possible to design systems that perform their task with very low power consumption. Unlike competitive processors, the Rabbit 3000 has short chip select features designed to minimize power consumption by external memories, which can easily become the dominant power consumers at low clock frequencies if not well handled. The preferred configuration for a Rabbit-based system is to use an external crystal or resonator that has a frequency of the maximum internal clock frequency. The oscillator frequency can be doubled or divided by 2, 4, 6, or 8, giving a variety of operating speeds from the same crystal frequency. In addition, the 32.768 kHz oscillator the drives the battery-backable clock can be used as the main processor clock and, to save the substantial power consumed by the fast oscillator, the fast oscillator can be turned off. This scenario is called the sleepy mode with a clock speed in the range of 2 kHz to 32 kHz, and with an operating system current consumption in the range of 10 to 120 A depending on frequency and voltage. Up to an operating speed of 29.5 MHz, a SST39LF512020 256K 8, 45 ns access time flash memory combined with any of several 55 ns low-power SRAMs is assumed for calculating the current consumption estimates below. A crystal frequency of 3.6864 MHz is a good choice for a low-power system consuming between 2 and 18 mA at 3.3 V as the clock frequency is throttled between 0.46 MHz and 7.37 MHz. The required memory access time is about 250 ns, however, a faster memory may result in less power since a short chip select cycle can then be used. A crystal frequency of 11.0592 MHz is a good choice for a medium-power system consuming between 5 and 50 mA at 3.3 V as the clock frequency is throttled between 1.4 MHz and 22 MHz. The required memory access time is 70 ns. A crystal frequency of 14.7456 MHz is a good choice for a faster medium-power system consuming between 6 and 65 mA at 3.3 V as the clock frequency is throttled between 1.8 and 29.5 MHz. The required memory access time is 55 ns. A maximum-speed system that will require fast RAM for program and data can be constructed using a 25.8048 MHz crystal. This system will consume between 12 and 112 mA at 3.3V as the clock speed is throttled between 3 and 51.6 MHz. The required memory access time is about 20 ns. Typical system current consumptions are shown in the graphs below. These are for the processor and oscillator only, and do not include current consumed by memory and other devices. It is assumed that approximately 30 pF is connected to each address line, particularly A0 and A1, which account for three quarters of the charging current due to the address lines. Users Manual 229 120 100 80 I (mA) xtal=25.80 xtal=14.74 xtal=11.05 xtal=3.68 60 40 20 0 0 10 20 30 40 50 60 Clock Frequency (MHz) Figure 16-9. Rabbit 3000 System Current vs. Frequency at 3.3 V 40 35 30 25 I (mA) 20 15 10 5 0 0 2 4 6 8 10 12 14 16 Clock Frequency (MHz) xtal=25.80 xtal=14.74 xtal=11.05 xtal=3.68 Figure 16-10. Rabbit 3000 System Current vs. Frequency at 3.3 V (enlarged view over 016 MHz range) 230 Rabbit 3000 Microprocessor Lowering the operating voltage will greatly reduce current consumption and power. Dropping to 2.7 V from 3.3 V will result in 70% current consumption and 60% of the power. Further dropping to 1.8 V will reduce current to 40% and power to 20% compared to 3.3 V. Naturally this complicates the selection of memories, especially at 1.8 V. It is important to know that the lowest speed crystal will not always give the lowest power consumption because when the crystal is divided internally the short chip select option can be used to reduce the chip select duty cycle of the flash memory or fast RAM, greatly reducing the static current consumption associated with some memories. In sleepy mode, power consumption consists of the processor core, the external recommended external tiny logic 32 kHz oscillator, and the memory. The oscillator consumes 17 A at 3.3 V, and this drops rapidly to about 2 A at 1.8 V. The processor core consumes between 3 and 50 A at 3.3 V as the frequency is throttled from 2 kHz to 32 kHz, and about 40% as much at 1.8 V. If the flash memory specified above is used for memory and a self-timed 106 ns chip select is used, then the memory will consume 22 A at 32 MHz and 1.4 A at 2 kHz. In addition to these items, a low-power reset controller may consume about 8 A and CMOS leakage may consume several A, increasing with higher temperatures. The graph below shows current consumption including the tiny logic core, but not including memory or the reset controller. 80 70 60 1.8V 50 I (A) 40 30 20 10 0 2.048 4.096 8.192 16.384 32.768 Clock Frequency (kHz) 2.2V 2.7V 3.0V 3.3V Figure 16-11. Sleepy Mode Current Consumption Users Manual 231 16.6 Current Consumption Mechanisms The following mechanisms contribute to the current consumption of the Rabbit 3000 while it is operating. 1. A current proportional to voltage and clock frequency that results from the charging of internal and external capacitances. At 3.3 V (see (2) below) approximately 57% of the current is due to charging and 43% is due to crossover current. 2. A crossover current that is proportional to clock frequency and to the overdrive voltage Vc = V [(V/2) 0.7], where V is the operating voltage of the Rabbit 3000. The crossover current results from a brief short circuit when both the P and N transistors of a CMOS buffer are turned on at the same time. This component drops as the voltage drops, and becomes negligible at 1.4 V. 3. The current consumed by the built-in main oscillator when turned on. This current is also proportional to Vc, and is equal to 1 mA at 3.3 V. 4. The current drawn by the logic that is driven at the oscillator (crystal frequency). This is considered distinct because it varies with the crystal frequency, but is not reduced when the clock frequency is divided. This current becomes zero when the main oscillator is turned off, and is 2.5 mA at 3.3 V when the crystal frequency is 14.7 MHz. This current is divided between capacitive and crossover components in the same manner as the currents in (1) and (2) above. All of the above currents can be combined according to the following formula: Itotal (mA) = 0.32 V f + 0.23 Vc f + 0.30 Vc + 0.029 V fc + 0.025 Vc fc where V = the operating voltage of the Rabbit 3000, Vc = V [(V/2) 0.7], fc = frequency of crystal oscillator in MHz, and f = clock frequency in MHz. 232 Rabbit 3000 Microprocessor 16.7 Sleepy Mode Current Consumption In sleepy mode the unit operates from the 32.768 kHz clock, which may be divided down to as slow as 2.048 kHz. The current consumption is given by: Itotal (A) = 0.32 V f + 0.23 Vc f + 5 Vc where f is in kHz, V is the operating voltage, and Vc = V [(V/2) - 0.7]. Leakage, the standby current of the reset generator, the current consumption of the oscillator and the real-time clock, and the current consumption of memories must be added to the sleepy mode current consumption. Generally the self-timed chip select mode is used to reduce memory current consumption. Users Manual 233 16.8 Memory Current Consumption Since there are many different memories available, lets look at an example using one of the recommended flash and SRAM memories. Flash memorySST part SST39LF512020, 256K 8, 45 ns access time. Standby current: nil. Static Current (chip select low): 3.5 mA @ 3.3 V Dynamic Current: 7 mA at 14.7 MHz bus speed and 3.3 V The total current is 10 mA at a clock speed of 29.49 MHz or a bus speed of 5 MHz. The static part of the current is computed using 3.5 (chip select duty cycle). The dynamic part is computed using 0.5 f in mA, where f is the bus speed in MHz. At 0.46 MHz (3.68 MHz/8), and using a short chip select, the duty cycle is about 10%, giving a static current of about 0.35 mA. The dynamic current is 0.25 mA, for a total current of 0.6 mA. Added to the approximately 2.5 mA operating current gives a total current of 3.1 mA at 0.46 MHz. In sleepy mode with a self-timed chip select of 106 ns and a clock speed of 32 kHz, the duty cycle will be 0.106/66 = 1/600, and the static current will be 3.5/600= 6 A. If the clock is divided down by a factor of 2, then the static current is reduced to 3 A. The dynamic current will be 16 A at 32 kHz (10000.5f) and 8 A at 16 kHz. 234 Rabbit 3000 Microprocessor 16.9 Battery-Backed Clock Current Consumption When using the suggested tiny logic oscillator, the oscillator and clock consume current as shown in Figure 16-12 below. Normally a resistor is placed in the battery circuit to limit the current to about 3 A, which results in a voltage setpoint of about 1.7 V. When operating at 3.3 V in sleepy mode, the current of the oscillator and the real-time clockabout 12 Amust be added. Using the suggested tiny logic oscillator circuit, the external 32.768 kHz oscillator consumes the following current in A, where V is the operating voltage. Iosc (A) = 0.35 V2 + 0.31 V Generally the oscillator will not start unless the voltage is about 1.4 V. However, the oscillator will continue to run until the voltage drops to about 0.8 V. If the oscillator stops, the current draw is very much lower than when it is running. Below about 1.4 V most of the current draw is used to charge and discharge the capacitive load. The current consumed by the battery-backed portion of the Rabbit 3000, which is driven by the 32.768 kHz oscillator, is given by Irab (A) = 0.91 V2 - 1.04 V (V > 1.14 V) The current is negligible for V < 1.14 V. Total Battery Backed Rabbit 3000 Real-Time Clock Tiny Logic 32 kHz Osc 12.00 10.00 Current (A) 8.00 6.00 4.00 2.00 0.00 2 4 6 8 2 4 6 8 1 2 1. 1. 1. 1. 2. 2. 2. 2. 3 3. 2 Battery-Backup Voltage (V) Figure 16-12. Current ConsumptionReal-Time Clock and 32 kHz Oscillator Circuit Users Manual 235 16.10 Reduced-Power External Main Oscillator The circuit in Figure 16-13 can be used to generate the main clock using less power than with the built-in oscillator buffer. The power consumption is less because of the currentlimiting resistors that cannot be used with the built-in buffer. The 2.2 k series resistor must be reduced as the clock frequency increases, as must be the current-limiting resistors. To Rabbit 3000 XTALA1 2.2 kW 33 pF +3.3 V SN74HCT1G04DBVR 1 MW 3.68 MHz (CL = 20 pF) Optional current-reducing resistors 33 pF Figure 16-13. Reduced-Power External Main Oscillator Table 16-8 lists results for the reduced-power external oscillator with no current-limiting resistors. Table 16-8. Current Draw Using Reduced-Power External Oscillator (0 current-limiting resistors) Voltage (V) 3.3 2.5 1.8 Current (incl built-in buffer) (mA) 0.635 0.380 0.252 Design Recommendations Add current-limiting resistors to reduce current without inhibiting oscillator start-up Increase the 1 M resistor to improve gain Minimize loop area to reduce EMI 236 Rabbit 3000 Microprocessor 17. RABBIT BIOS AND VIRTUAL DRIVER When a program is compiled by Dynamic C for a Rabbit target, the Virtual Driver is automatically incorporated into the program. Virtual Driver is the name given to some initialization routines and a group of services performed by the periodic interrupt. The Rabbit BIOS, software that handles startup, shutdown and various basic features of the Rabbit, is compiled to the target along with the application program. Z-World provides the full source code for the BIOS and Virtual Driver so the user can modify them and examine details of the operation that are not apparent from the documentation. More details on the BIOS and Virtual Driver software can be found in the Dynamic C Users Manual, the Rabbit 3000 Designers Handbook, and the source code in the Dynamic C libraries. 17.1 The BIOS The BIOS provided with Dynamic C will work with all Z-World and Rabbit Semiconductor Rabbit board products. The BIOS is compiled separately from the users application. It occupies space at the bottom of the root code segment. When execution of the users program starts at address zero on power-up or reset, it starts in the BIOS. When Dynamic C cold-boots the target and downloads the binary image of the BIOS, the BIOS symbol table is retained to make its entry points and global data available to the user application. Board specific drivers are compiled with the users program after the BIOS is compiled. 17.1.1 BIOS Services The BIOS includes support for the following services. System startup: including setup of memory, wait states and clock speed. Writing to flash. Writes to the primary code memory require turning off interrupts for up to 20 ms or so. To protect the System Identification Block (see the Rabbit 3000 Designers Handbook for more information on the System ID Block), the flash driver will not write to that block. A routine that can actually write this block is not included in the BIOS to make it hard to accidently corrupt this block. Run-time exception handling and logging to handle fatal errors and watchdog time-outs (error logging not implemented in older versions). Debugging and PC-target communication Users Manual 237 17.1.2 BIOS Assumptions The BIOS makes certain assumptions concerning the physical configuration of the processor. Processors are expected to have RAM connected to /CS1, /WE1, and /OE1. Flash is expected to be connected to /CS0, /WE0, and /OE0. (See the Rabbit 3000 Designers Handbook Memory Planning chapter if you want to design a board with RAM only.) The crystal frequency is expected to be n*1.8432 MHz. The Rabbit 3000 Designers Handbook has a chapter on the Rabbit BIOS with more details. 17.2 Virtual Driver The Virtual Driver is compiled with the users application. It includes support for the following services. Hitting the hardware watchdog timer. Decrementing software watchdog timers. Synchronizing the system timer variables with the real-time clock and keeping them updated. Driving uC/OS-II multi-tasking. Driving slice statement multi-tasking. 17.2.1 Periodic Interrupt The periodic interrupt that drives the Virtual Driver occurs every 16 clocks or every 488 s. If the 32.768 kHz oscillator is absent, it is possible to substitute a different periodic interrupt. This alternative is not supported by Z-World since the cost of connecting a crystal is very small. The periodic interrupt keeps the interrupts turned off (that is, the processor priority is raised to 1 from zero) for about 75 clocks, so it contributes little to interrupt latency. The periodic interrupt is turned on by default before main() is called. It can be disabled if needed. The Dynamic C Userss Manual chapter on the Virtual Driver provides more details on the periodic interrupt. The Rabbit 3000 microprocessor requires the 32 kHz oscillator in order to boot via Dynamic C, unless a custom loader and BIOS are used. 17.2.2 Watchdog Timer Support A microprocessor system can crash for a variety of reasons. A software bug or an electrical upset are common reasons. When the system crashes the program will typically settle into an endless loop because parameters that govern looping behavior have been corrupted. Typically, the stack becomes corrupted and returns are made to random addresses. The usual corrective action taken in response to a crash is to reset the microprocessor and reboot the system. The crash can be detected either because an anomaly is detected by pro238 Rabbit 3000 Microprocessor gram consistency checking or because a part of the program that should be executing periodically is not executing and the watchdog times out. The Virtual Drivers periodic interrupt hits the hardware watchdog timer with a 2 second time-out. If the periodic interrupt stops working, then the watchdog will time out after 2 seconds. The Virtual Driver provides a number of additional virtual watchdog timers for use in other parts of the code that must be entered periodically. The user program must hit each virtual watchdog periodically. The best practice is to let the periodic interrupt hit the hardware watchdog exclusively, and use virtual watchdogs for other code that must be run periodically. If hits to the hardware watchdog are scattered through a program, then it may be possible for the code to enter an endless loop where the watchdog is hit, and therefore rendered useless for detecting the endless loop condition. If no virtual watchdogs are used, an undetected endless loop condition could still occur since the periodic interrupt can still hit the hardware watchdog. If any of the virtual watchdogs times out, then hits are withheld from the hardware watchdog and it times out, resulting in a hardware reset. Virtual watchdogs may be allocated, deallocated, enabled and disabled. The advantage of the virtual watchdogs is that if any of them fail an error is detected. The Dynamic C Userss Manual chapter on the Virtual Driver provides more details on virtual watchdogs. Users Manual 239 240 Rabbit 3000 Microprocessor 18. OTHER RABBIT SOFTWARE 18.1 Power Management Support The power consumption and speed of operation can be throttled up and down with rough synchronism. This is done by changing the clock speed or the clock doubler. The range of control is quite wide: the speed can vary by a factor of 16 when the main clock is driving the processor. In addition, the main clock can be switched to the 32.768 kHz clock. In this case, the slowdown is very dramatic, a factor of perhaps 500. In this ultra slow mode, each clock takes about 30 s, and a typical instruction takes 150 s to execute. At this speed, the periodic interrupt cannot operate because the interrupt routine would execute too slowly to keep up with an interrupt every 16 clocks. Only about 3 instructions could be executed between ticks. A different set of rules applies in the ultra slow or sleepy mode. The Rabbit 3000 automatically disables periodic interrupts when the clock mode is switched to 32 kHz or one of the multiples of 32 kHz. This means that the periodic-interrupt hardware does not function when running at any of these 32 kHz clock speeds simply because there are not enough clock cycles available to service the interrupt. Hence virtual watchdogs (which depend on the periodic interrupt) cannot be used in the sleepy mode. The user must set up an endless loop to determine when to exit sleepy mode. A routine, updateTimers(), is provided to update the system timer variables by directly reading the real-time clock and to hit the watchdog while in sleepy mode. If the users routine cannot get around the loop in the maximum watchdog timer time-out time, the user should put several calls to updateTimers() in the loop. The user should avoid indiscriminate direct access to the watchdog timer and real-time clock. The least significant bits of the real-time clock cannot be read in ultra slow mode because they count fast compared to the instruction execution time. To reduce bus activity and thus power consumption, it is useful to multiply zero by zero. This requires 12 clocks for one memory cycle and reduces power consumption. Typically a number of mul instructions can be executed between each test of the condition being waited for. Dynamic C libraries also provide functions to change clock speeds to enter and exit sleepy mode. See the Rabbit 3000 Designers Handbook chapter Low Power Design and Support for more details. Users Manual 241 18.2 Reading and Writing I/O Registers The Rabbit has two I/O spaces: internal I/O registers and external I/O registers. 18.2.1 Using Assembly Language The fastest way to read and write I/O registers in Dynamic C is to use a short segment of assembly language inserted in the C program. Access is the same as for accessing data memory except that the instruction is preceded by a prefix (IOI or IOE) to indicate the internal or external I/O space. For example: // compute value and write to Port A Data Register value=x+y #asm ld a,(value) ioi ld (PADR),a #endasm ; value to write ; write value to PADR In the example above the IOI prefix changes a store to memory to a store to an internal I/O port. The prefix ioe is used for writes to external I/O ports. 18.2.2 Using Library Functions Dynamic C functions are available to read and write I/O registers. These functions are provided for convenience. For speed, assembly code is recommended. For a complete description of the functions noted in this section, refer to the Dynamic C Users Manual or from the Help menu in Dynamic C, access the HTML Function Reference or Function Lookup options. To read internal I/O registers, there are two functions. int RdPortI(int PORT) ; // returns PORT, high byte zero int BitRdPortI(int PORT, int bitcode); // bit code 0-7 To write internal I/O registers, there are two functions. void WrPortI(int PORT, char *PORTShadow, int value); void BitWrPortI(int PORT, char *PORTShadow, int value, int bitcode); The external registers are also accessible with Dynamic C functions. int int int int RdPortE(int PORT) ; // returns PORT, high byte zero BitRdPortE(int PORT, int bitcode); // bit code 0-7 WrPortE(int PORT, char *PORTShadow, int value); BitWrPortE(int PORT, char *PORTShadow, int value, int bitcode); In order to read a port the following code could be used: k=RdPortI(PADR); // returns Port A Data Register 242 Rabbit 3000 Microprocessor 18.3 Shadow Registers Many of the registers of the Rabbits internal I/O devices are write-only. This saves gates on the chip, making possible greater capability at lower cost. Write-only registers are easier to use if a memory location, called a shadow register, is associated with each writeonly register. To make shadow register names easy to remember, the word shadow is appended to the register name. For example the register GOCR (Global Output Control register) has the shadow GOCRShadow. Some shadow registers are defined in the BIOS source code as shown below. char GCSRShadow; // Global Control Status Register char GOCRShadow; // Global Output Control Register char GCDRShadow; // Global Clock Doubler Register If the port is a write-only port, the shadow register can be used to find out the ports contents. For example GCSR has a number of write-only bits. These can be read by consulting the shadow, provided that the shadow register is always updated when writing to the register. k=GCSRShadow; 18.3.1 Updating Shadow Registers If the address of a shadow register is passed as an argument to one of the functions that write to the internal or external I/O registers, then the shadow register will be updated as well as the specified I/O register. A NULL pointer may replace the pointer to a shadow register as an argument to WrPortI() and WrPortE(); the shadow register associated with the port will not be updated. A pointer to the shadow register is mandatory for BitWrPortI() and BitWrPortE(). 18.3.2 Interrupt While Updating Registers When manipulating I/O registers and shadow registers, the programmer must keep in mind that an interrupt can take place in the middle of the sequence of operations, and then the interrupt routine may manipulate the same registers. If this possibility exists, then a solution must be crafted for the particular situation. Usually it is not necessary to disable the interrupts while manipulating registers and their associated shadow registers. 18.3.2.1 Atomic Instruction As an example, consider the Parallel Port D data direction register (PDDDR). This register is write only, and it contains 8 bits corresponding to the 8 I/O pins of Parallel Port D. If a bit in this register is a 1, the corresponding port pin is an output, otherwise it is an input. It is easy to imagine a situation where different parts of the application, such as an interrupt routine and a background routine, need to be in charge of different bits in the PDDDR register. The following code sets a bit in the shadow and then sets the I/O register. If an interrupt takes place between the set and the LDD, and changes the shadow register and PDDDR, the correct value will still be set in PDDDR. Users Manual 243 ld hl,PDDDRShadow ; point to shadow register ld de,PDDDR ; set de to point to I/O reg set 5,(hl) ; set bit 5 of shadow register ; use ldd instruction for atomic transfer ioi ldd ; (io de)<-(hl) side effect: hl--, de-- In this case, the ldd instruction when used with an I/O prefix provides a convenient data move from a memory location to an I/O location. Importantly, the ldd instruction is an atomic operation so there is no danger that an interrupt routine could change the shadow register during the move to the PDDDR register. 18.3.2.2 Non-atomic Instructions If the following two instructions were used instead of the ldd instruction, ld a,(hl) ld (PDDDR),a ; output to PDDDR then an interrupt could take place after the first instruction, change the shadow register and the PDDDR register, and then after a return from the interrupt, the second instruction would execute and store an obsolete copy of the shadow register in the PDDDR, setting it to a wrong value. 18.3.3 Write-only Registers Without Shadow Registers Shadow register are not needed for many of the registers that can be written to. In some cases, writing to registers is used as a handy way of changing a peripherals state, and the data bits written are ignored. For example, a write to the status register in the Rabbit serial ports is used to clear the transmitter interrupt request, but the data bits are ignored, and the status register is actually a read-only register except for the special functionality attached to the act of writing the register. An illustration of a write-only register for which a shadow is unnecessary is the transmitter data register in the Rabbit serial port. The transmitter data register is a write-only register, but there is little reason to have a shadow register since any data bits stored are transmitted promptly on the serial port. 18.4 Timer and Clock Usage The battery-backable real-time clock is a 48 bit counter that counts at 32768 counts per second. The counting frequency comes from the 32.768 kHz oscillator which is separate from the main oscillator. Two other important devices are also powered from the 32.768 kHz oscillator: the periodic interrupt and the watchdog timer. It is assumed that all measurements of time will derive from the real-time clock and not the main processor clock which operates at a much higher frequency (e.g. 22.1184 MHz). This allows the main processor oscillator to use less expensive ceramic resonators rather than quartz crystals. Ceramic resonators typically have an error of 5 parts in 1000, while crystals are much more accurate, to a few seconds per day. 244 Rabbit 3000 Microprocessor Two library functions are provided to read and write the real-time clock: unsigned long int read_rtc(void) ; // read bits 15-46 rtc void write_rtc(unsigned long int time) ; // write bits 15-46 // note: bits 0-14 and bit 47 are zeroed However, it is not intended that the real-time clock be read and written frequently. The procedure to read it is lengthy and has an uncertain execution time. The procedure for writing the clock is even more complicated. Instead, Dynamic C software maintains a long variable SEC_TIMER in memory. SEC_TIMER is synchronized with the real-time clock when the Virtual Driver starts, and updated every second by the periodic interrupt. It may be read or written directly by the users programs. Since SEC_TIMER is driven by the same oscillator as the real-time clock there is no relative gain or loss of time between the two. A millisecond timer variable, MS_TIMER, is also maintained by the Virtual Driver. Two utility routines are provided that can be used to convert times between the traditional format (10-Jan-2000 17:34:12) and the seconds since 1-Jan-1980 format. // converts time structure to seconds unsigned long mktime(struct tm *timeptr); // seconds to structure unsigned int mktm(struct tm *timeptr, unsigned long time); The format of the structure used is the following struct tm { char tm_sec; char tm_min; char tm_hour; char tm_mday; char tm_mon; char tm_year; char tm_wday; }; // // // // // // // seconds 0-59 0-59 0-59 1-31 1-12 00-150 (1900-2050) 0-6 0==sunday The day of the week is not used to compute the long seconds, but it is generated when computing from long seconds to the structure. A utility program, setclock.c, is available to set the date and time in the real-time clock from the Dynamic C STDIO console. Users Manual 245 246 Rabbit 3000 Microprocessor 19. RABBIT INSTRUCTIONS Summary Load Immediate Data on page 250 Load & Store to Immediate Address on page 250 8-bit Indexed Load and Store on page 250 16-bit Indexed Loads and Stores on page 250 16-bit Load and Store 20-bit Address on page 251 Register to Register Moves on page 251 Exchange Instructions on page 252 Stack Manipulation Instructions on page 252 16-bit Arithmetic and Logical Ops on page 252 8-bit Arithmetic and Logical Ops on page 253 8-bit Bit Set, Reset and Test on page 254 8-bit Increment and Decrement on page 254 8-bit Fast A Register Operations on page 255 8-bit Shifts and Rotates on page 255 Instruction Prefixes on page 256 Block Move Instructions on page 256 Control Instructions - Jumps and Calls on page 257 Miscellaneous Instructions on page 257 Privileged Instructions on page 258 Instructions in Alphabetical Order With Binary Encoding on page 261 Users Manual 247 Spreadsheet Conventions ALTD (A Column) Symbol Key Flag f fr r s Description ALTD selects alternate flags ALTD selects alternate flags and register ALTD selects alternate register ALTD operation is a special case IOI and IOE (I Column) Symbol Key Flag b d s Description IOI and IOE affect source and destination IOI and IOE affect destination IOI and IOE affect source Flag Register Key S * * L V 0 * * 0 1 Z L/V* C Description Sign flag affected Sign flag not affected Zero flag affected Zero flag not affected LV flag contains logical check result LV flag contains arithmetic overflow result LV flag is cleared LV flag is affected Carry flag is affected Carry flag is not affected Carry flag is cleared Carry flag is set * The L/V (logical/overflow) flag serves a dual purpose L/V is set to 1 for logical operations if any of the four most significant bits of the result are 1, and L/V is reset to 0 if all four of the most significant bits of the result are 0. 248 Rabbit 3000 Microprocessor Symbols Rabbit Z180 Bit select: 000 = bit 0, 001 = bit 1, 010 = bit 2, 011 = bit 3, 100 = bit 4, 101 = bit 5, 110 = bit 6, 111 = bit 7 Condition code select: 00 = NZ, 01 = Z, 10 = NC, 11 = C 7-bit (signed) displacement. Expressed in twos complement. Word register select destination: 00 = BC, 01 = DE, 10 = HL, 11 = SP Word register select alternate: 00 = BC, 01 = DE, 10 = HL j Meaning b b cc cc d dd dd e d ww 8-bit (signed) displacement added to PC. Condition code select: 000 = NZ (non zero),001 = Z (zero), 010 = NC (non carry), 011 = C (carry), 100 = LZ* (logical zero), 101 = LO (logical one), 110 = P (sign plus), 111 = M (sign minus) MSB of a 16-bit constant. 16-bit constant. 8-bit constant or LSB of a 16-bit constant. Byte register select: 000 = B, 001 = C, 010 = D, 011 = E, 100 = H, 101 = L, 111 = A Word register select (source): 00 = BC, 01 = DE, 10 = HL, 11 = SP Restart address select: 010 = 0x0020, 011 = 0x0030, 100 = 0x0040, 101 = 0x0050, 111 = 0x0070 Word register select: 00 = BC, 01 = DE, 10 = IX, 11 = SP Word register select: 00 = BC, 01 = DE, 10 = IY, 11 = SP Word register select: 00 = BC, 01 = DE, 10 = HL, 11 = AF f f m mn n m mn n r, g g, g ss ww v v xx yy zz xx yy zz * Logical zero if all four of the most significant bits of the result are 0. Logical one if any of the four most significant bits of the result are 1. Users Manual 249 19.1 Load Immediate Data Instruction LD IX,mn LD IY,mn LD dd,mn LD r,n clk 8 8 6 4 A I S Z V C Operation IX = mn IY = mn dd = mn r = n r r 19.2 Load & Store to Immediate Address Instruction LD (mn),A LD A,(mn) LD (mn),HL LD (mn),IX LD (mn),IY LD (mn),ss LD HL,(mn) LD IX,(mn) LD IY,(mn) LD dd,(mn) clk 10 9 13 15 15 15 11 13 13 13 A r I d s d d d d s s s s S Z V C Operation (mn) = A A = (mn) (mn) = L; (mn+1) = H (mn) = IXL; (mn+1) = IXH (mn) = IYL; (mn+1) = IYH (mn) = ssl; (mn+1) = ssh L = (mn); H = (mn+1) IXL = (mn); IXH = (mn+1) IYL = (mn); IYH = (mn+1) ddl = (mn); ddh = (mn+1) r r 19.3 8-bit Indexed Load and Store Instruction LD A,(BC) LD A,(DE) LD (BC),A LD (DE),A LD (HL),n LD (HL),r LD r,(HL) LD (IX+d),n LD (IX+d),r LD r,(IX+d) LD (IY+d),n LD (IY+d),r LD r,(IY+d) clk 6 6 7 7 7 6 5 11 10 9 11 10 9 A r r I s s d d d d s d d s d d s S Z V C Operation A = (BC) A = (DE) (BC) = A (DE) = A (HL) = n (HL) = r = B, C, D, E, H, L, A r = (HL) (IX+d) = n (IX+d) = r r = (IX+d) (IY+d) = n (Iy+d) = r r = (IY+d) r r r 19.4 16-bit Indexed Loads and Stores Instruction LD (HL+d),HL LD HL,(HL+d) LD (SP+n),HL LD (SP+n),IX LD (SP+n),IY LD HL,(SP+n) LD IX,(SP+n) LD IY,(SP+n) LD (IX+d),HL LD HL,(IX+d) LD (IY+d),HL LD HL,(IY+d) clk 13 11 11 13 13 9 11 11 11 9 13 11 I S Z V C Operation d - - - - (HL+d) = L; (HL+d+1) = H r s - - - - L = (HL+d); H = (HL+d+1) - - - - (SP+n) = L; (SP+n+1) = H - - - - (SP+n) = IXL; (SP+n+1) = IXH - - - - (SP+n) = IYL; (SP+n+1) = IYH r - - - - L = (SP+n); H = (SP+n+1) - - - - IXL = (SP+n); IXH = (SP+n+1) - - - - IYL = (SP+n); IYH = (SP+n+1) d - - - - (IX+d) = L; (IX+d+1) = H r s - - - - L = (IX+d); H = (IX+d+1) d - - - - (IY+d) = L; (IY+d+1) = H r s - - - - L = (IY+d); H = (IY+d+1) A 250 Rabbit 3000 Microprocessor 19.5 16-bit Load and Store 20-bit Address Instruction LDP (HL),HL LDP (IX),HL LDP (IY),HL LDP HL,(HL) LDP HL,(IX) LDP HL,(IY) LDP (mn),HL LDP (mn),IX LDP (mn),IY LDP HL,(mn) LDP IX,(mn) LDP IY,(mn) clk 12 12 12 10 10 10 15 15 15 13 13 13 A I S Z V C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Operation (HL) = L; (HL+1) = H. (Adr[19:16] = A[3:0]) (IX) = L; (IX+1) = H. (Adr[19:16] = A[3:0]) (IY) = L; (IY+1) = H. (Adr[19:16] = A[3:0]) L = (HL); H = (HL+1). (Adr[19:16] = A[3:0]) L = (IX); H = (IX+1). (Adr[19:16] = A[3:0]) L = (IY); H = (IY+1). (Adr[19:16] = A[3:0]) (mn) = L; (mn+1) = H. (Adr[19:16] = A[3:0]) (mn) = IXL; (mn+1) = IXH. (Adr[19:16] = A[3:0]) (mn) = IYL; (mn+1) = IYH. (Adr[19:16] = A[3:0]) L = (mn); H = (mn+1). (Adr[19:16] = A[3:0]) IXL = (mn); IXH = (mn+1). (Adr[19:16] = A[3:0]) IYL = (mn); IYH = (mn+1). (Adr[19:16] = A[3:0]) Note that the LDP instructions wrap around on a 64K page boundary. Since the LDP instruction operates on two-byte values, the second byte will wrap around and be written at the start of the page if you try to read or write across a page boundary. Thus, if you fetch or store at address 0xn,0xFFFF, you will get the bytes located at 0xn,0xFFFF and 0xn,0x0000 instead of 0xn,0xFFFFand 0x(n+1),0x0000 as you might expect. Therefore, do not use LDP at any physical address ending in 0xFFFF. 19.6 Register to Register Moves Instruction LD r,g LD A,EIR LD A,IIR LD A,XPC LD EIR,A LD IIR,A LD XPC,A LD HL,IX LD HL,IY LD IX,HL LD IY,HL LD SP,HL LD SP,IX LD SP,IY LD dd,BC LD dd,DE clk 2 4 4 4 4 4 4 4 4 4 4 2 4 4 4 4 A I S Z V C r - - - fr * * - fr * * - r - - - - - - - - - - - - r - - - r - - - - - - - - - - - - - - - - - - - - - - - - Operation r = g, r, g any of B, C, D, E, H, L, A A = EIR A = IIR A = MMU EIR = A IIR = A XPC = A HL = IX HL = IY IX = HL IY = HL SP = HL SP = IX SP = IY dd = BC (dd: 00-BC, 01-DE, 10-HL) dd = DE (dd: 00-BC, 01-DE, 10-HL) Users Manual 251 19.7 Exchange Instructions Instruction EX (SP),HL EX (SP),IX EX (SP),IY EX AF,AF EX DE,HL EX DE,HL EX DE,HL EX DE,HL EXX clk 15 15 15 2 2 4 2 4 2 A r I S Z V C Operation - - - - H <-> (SP+1); L <-> (SP) - - - - IXH <-> (SP+1); IXL <-> (SP) - - - - IYH <-> (SP+1); IYL <-> (SP) - - - - AF <-> AF - - - - if (!ALTD) then DE <-> HL else DE <-> HL - - - DE <-> HL - - - - if (!ALTD) then DE <-> HL else DE <-> HL - - - - DE <-> HL - - - - BC <-> BC; DE <-> DE; HL <-> HL s s s s EX DE,HL A F H L D E B C EX AF,AF EX DE,HL A F H L EX DE,HL D EX DE,HL E B C EXX - exchange HL,HL,DE,DE,BC,BC 19.8 Stack Manipulation Instructions Instruction ADD SP,d POP IP POP IX POP IY POP zz PUSH IP PUSH IX PUSH IY PUSH zz clk 4 7 9 9 7 9 12 12 10 r A f I S Z V C * Operation SP = SP + d -- d=0 to 255 IP = (SP); SP = SP+1 IXL = (SP); IXH = (SP+1); SP = SP+2 IYL = (SP); IYH = (SP+1); SP = SP+2 zzl = (SP); zzh = (SP+1); SP=SP+2 -- zz= BC,DE,HL,AF (SP-1) = IP; SP = SP-1 (SP-1) = IXH; (SP-2) = IXL; SP = SP-2 (SP-1) = IYH; (SP-2) = IYL; SP = SP-2 (SP-1) = zzh; (SP-2) = zzl; SP=SP-2 --zz= BC,DE,HL,AF - - - - - - - - - - - - - - - - - - - 19.9 16-bit Arithmetic and Logical Ops Instruction ADC HL,ss ADD HL,ss ADD IX,xx clk 4 2 4 A I S Z V C fr * * V * fr f - - - * - - - * Operation HL = HL + ss + CF -- ss=BC, DE, HL, SP HL = HL + ss IX = IX + xx -- xx=BC, DE, IX, SP 252 Rabbit 3000 Microprocessor ADD IY,yy ADD SP,d AND HL,DE AND IX,DE AND IY,DE BOOL HL BOOL IX BOOL IY DEC IX DEC IY DEC ss INC IX INC IY INC ss MUL OR OR OR RL HL,DE IX,DE IY,DE DE 4 4 2 4 4 2 4 4 4 4 2 4 4 2 12 2 4 4 2 2 2 4 4 4 f f fr f f fr f f - - - * * * * * * * * * * * * * L L L 0 0 0 * 0 0 0 0 0 0 - r r - - - - - - - - - - - - - fr f f fr fr fr f f fr * * * * * * * * * * * * * * * * * * L L L L L L L L V 0 0 0 * * * * * * RR DE RR HL RR IX RR IY SBC HL,ss IY = IY + yy -- yy=BC, DE, IY, SP SP = SP + d -- d=0 to 255 HL = HL & DE IX = IX & DE IY = IY & DE if (HL != 0) HL = 1, set flags to match HL if (IX != 0) IX = 1 if (IY != 0) IY = 1 IX = IX - 1 IY = IY - 1 ss = ss - 1 -- ss= BC, DE, HL, SP IX = IX + 1 IY = IY + 1 ss = ss + 1 -- ss= BC, DE, HL, SP HL:BC = BC * DE, signed 32 bit result. DE unchanged HL = HL | DE -- bitwise or IX = IX | DE IY = IY | DE {CY,DE} = {DE,CY} -left shift with CF {DE,CY} = {CY,DE} {HL,CY} = {CY,HL} {IX,CY} = {CY,IX} {IY,CY} = {CY,IY} HL=HL-ss-CY (cout if (ss-CY)>hl) 19.10 8-bit Arithmetic and Logical Ops Instruction ADC A,(HL) ADC A,(IX+d) ADC A,(IY+d) ADC A,n ADC A,r ADD A,(HL) ADD A,(IX+d) ADD A,(IY+d) ADD A,n ADD A,r AND (HL) AND (IX+d) AND (IY+d) AND n AND r CP* (HL) CP* (IX+d) CP* (IY+d) clk 5 9 9 4 2 5 9 9 4 2 5 9 9 4 2 5 9 9 A fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr f f f I s s s S * * * * * * * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * V V V V V V V V V V V L L L L L V V V C * * * * * * * * * * 0 0 0 0 0 * * * Operation A = A + (HL) + CF A = A + (IX+d) + CF A = A + (IY+d) + CF A = A + n + CF A = A + r + CF A = A + (HL) A = A + (IX+d) A = A + (IY+d) A = A + n A = A + r A = A & (HL) A = A & (IX+d) A = A & (IY+d) A = A & n A = A & r A - (HL) A - (IX+d) A - (IY+d) s s s s s s s s s Users Manual 253 CP* n CP* r OR (HL) OR (IX+d) OR (IY+d) OR n OR r SBC* (IX+d) SBC* (IY+d) SBC* A,(HL) SBC* A,n SBC* A,r SUB (HL) SUB (IX+d) SUB (IY+d) SUB n SUB r XOR (HL) XOR (IX+d) XOR (IY+d) XOR n XOR r 4 2 5 9 9 4 2 9 9 5 4 2 5 9 9 4 2 5 9 9 4 2 f * * V * f * * V * fr s * * L 0 fr s * * L 0 fr s * * L 0 fr * * L 0 fr * * L 0 fr s * * V * fr s * * V * fr s * * V * fr * * V * fr * * V * fr s * * V * fr s * * V * fr s * * V * fr * * V * fr * * V * fr s * * L 0 fr s * * L 0 fr s * * L 0 fr * * L 0 fr * * L 0 A A A A A A A A A A A A A A A A A A n r A | (HL) A | (IX+d) A | (IY+d) A | n A | r A - (IX+d) - CY A - (IY+d) - CY A - (HL) - CY A-n-CY (cout if (r-CY)>A) A-r-CY (cout if (r-CY)>A) A - (HL) A - (IX+d) A - (IY+d) A - n A - r [A & ~(HL)] | [~A & (HL)] A = [A & ~(IX+d)] | [~A & (IX+d)] A = [A & ~(IY+d)] | [~A & (IY+d)] A = [A & ~n] | [~A & n] A = [A & ~r] | [~A & r] = = = = = = = = = = = = = = = = * SBC and CP instruction output inverted carry. C is set if A<B if the operation or virtual operation is (A-B). Carry is cleared if A>=B. SUB outputs carry in opposite sense from SBC and CP. 19.11 8-bit Bit Set, Reset and Test Instruction BIT b,(HL) BIT b,(IX+d)) BIT b,(IY+d)) BIT b,r RES b,(HL) RES b,(IX+d) RES b,(IY+d) RES b,r SET b,(HL) SET b,(IX+d) SET b,(IY+d) SET b,r clk 7 10 10 4 10 13 13 4 10 13 13 4 A f f f f I s s s d d d r b b b r S Z * * * * V C Operation (HL) & bit (IX+d) & bit (IY+d) & bit r & bit (HL) = (HL) & ~bit (IX+d) = (IX+d) & ~bit (IY+d) = (IY+d) & ~bit r = r & ~bit (HL) = (HL) | bit (IX+d) = (IX+d) | bit (IY+d) = (IY+d) | bit r = r | bit - - - - 19.12 8-bit Increment and Decrement Instruction DEC (HL) DEC (IX+d) DEC (IY+d) DEC r INC (HL) INC (IX+d) INC (IY+d) INC r clk 8 12 12 2 8 12 12 2 A f f f fr f f f fr I b b b S * * * * b * b * b * * Z * * * * * * * * V V V V V V V V V C Operation (HL) = (HL) - 1 (IX+d) = (IX+d) (IY+d) = (IY+d) r = r - 1 (HL) = (HL) + 1 (IX+d) = (IX+d) (IY+d) = (IY+d) r = r + 1 -1 -1 + 1 + 1 254 Rabbit 3000 Microprocessor 19.13 8-bit Fast A Register Operations Instruction CPL NEG RLA RLCA RRA RRCA clk 2 4 2 2 2 2 A I S Z V C r - - - fr * * V * fr - - - * fr - - - * fr - - - * fr - - - * Operation A = ~A A = 0 - A {CY,A} = {A,CY} A = {A[6,0],A[7]}; CY = A[7] {A,CY} = {CY,A} A = {A[0],A[7,1]}; CY = A[0] 19.14 8-bit Shifts and Rotates RL, RLA C C C C clk 10 13 13 4 10 13 13 4 10 13 13 4 10 13 13 4 10 13 13 A f f f fr f f f fr f f f fr f f f I b b b S * * * * b * Z * * * * * V L L L L L C * * * * * SLA C C 0 0 RLC, RLCA SRA RR, RRA SRL C RRC, RRCA Instruction RL (HL) RL (IX+d) RL (IY+d) RL r RLC (HL) RLC (IX+d) RLC (IY+d) RLC r RR (HL) RR (IX+d) RR (IY+d) RR r RRC (HL) RRC (IX+d) RRC (IY+d) RRC r SLA (HL) SLA (IX+d) SLA (IY+d) b * * L * b * * L * * * L b * * L b * * L b * * L * * L b * * L * * * * * * b * * L * b * * L * fr * * L * f b * * L * f f b * * L * b * * L * Operation {CY,(HL)} = {(HL),CY} {CY,(IX+d)} = {(IX+d),CY} {CY,(IY+d)} = {(IY+d),CY} {CY,r} = {r,CY} (HL) = {(HL)[6,0],(HL)[7]}; CY = (HL)[7] (IX+d) = {(IX+d)[6,0], (IX+d)[7]}; CY = (IX+d)[7] (IY+d) = {(IY+d)[6,0], (IY+d)[7]}; CY = (IY+d)[7] r = {r[6,0],r[7]}; CY = r[7] {(HL),CY} = {CY,(HL)} {(IX+d),CY} = {CY,(IX+d)} {(IY+d),CY} = {CY,(IY+d)} {r,CY} = {CY,r} (HL) = {(HL)[0],(HL)[7,1]}; CY = (HL)[0] (IX+d) = {(IX+d)[0], (IX+d)[7,1]}; CY = (IX+d)[0] (IY+d) = {(IY+d)[0],( IY+d)[7,1]}; CY = (IY+d)[0] r = {r[0],r[7,1]}; CY = r[0] (HL) = {(HL)[6,0],0}; CY = (HL)[7] (IX+d) = {(IX+d)[6,0],0}; CY = (IX+d)[7] (IY+d) = {(IY+d)[6,0],0}; CY = (IY+d)[7] Users Manual 255 SLA r SRA (HL) SRA (IX+d) SRA (IY+d) SRA r SRL (HL) SRL (IX+d) SRL (IY+d) SRL r 4 10 13 13 4 10 13 13 4 fr * * L * f b * * L * f f b * * L * b * * L * fr * * L * f b * * L * f f fr b * * L * b * * L * * * L * r = {r[6,0],0}; CY = r[7] (HL) = {(HL)[7],(HL)[7,1]}; CY = (HL)[0] (IX+d) = {(IX+d)[7], (IX+d)[7,1]}; CY = (IX+d)[0] (IY+d) = {(IY+d)[7], (IY+d)[7,1]}; CY = (IY+d)[0] r = {r[7],r[7,1]}; CY = r[0] (HL) = {0,(HL)[7,1]}; CY = (HL)[0] (IX+d) = {0,(IX+d)[7,1]}; CY = (IX+d)[0] (IY+d) = {0,(IY+d)[7,1]}; CY = (IY+d)[0] r = {0,r[7,1]}; CY = r[0] 19.15 Instruction Prefixes Instruction ALTD IOE IOI clk 2 2 2 A I S Z V C Operation - - - - alternate register destinatIn for next Instruction - - - - I/O external prefix - - - - I/O internal prefix 19.16 Block Move Instructions Instruction LDD LDDR LDI LDIR clk 10 6+7i 10 6+7i A I S Z V C d - - * d - - * d - - * d - - * Operation (DE) = (HL); BC = BC-1; DE = DE-1; HL = HL-1 if {BC != 0} repeat: (DE) = (HL); BC = BC-1; DE = DE+1; HL = HL+1 if {BC != 0} repeat: If any of the block move instructions are prefixed by an I/O prefix, the destination will be in the specified I/O space. Add 1 clock for each iteration for the prefix if the prefix is IOI (internal I/O). If the prefix is IOE, add 2 clocks plus the number of I/O wait states enabled. The V flag is set when BC transitions from 1 to 0. If the V flag is not set another step is performed for the repeating versions of the instructions. Interrupts can occur between different repeats, but not within an iteration equivalent to LDD or LDI. Return from the interrupt is to the first byte of the instruction which is the I/O prefix byte if there is one. A new LDIR/LDDR bug was discovered in September, 2002. The problem has to do with wait states and the block move operations. With this problem, the first iteration of LDIR/LDDR uses the correct number of wait states for both the read and the write. However, all subsequent iterations use the number of waits programmed for the memory located at the write address for both the read and the write cycles. This becomes a problem when moving a block of data from a slow memory device requiring wait states to a fast memory device requiring no wait states. With respect to external I/O operations, the LDIR or LDDR performs reads with zero wait states independent of the waits programmed for the I/O for all but the first iteration. The first iteration is correct. This bug is automatically corrected by Dynamic C, and will be fixed in future generations of the chip. 256 Rabbit 3000 Microprocessor 19.17 Control Instructions - Jumps and Calls Instruction CALL mn DJNZ j JP (HL) JP (IX) JP (IY) JP f,mn JP mn JR cc,e JR e LCALL xpc,mn clk 12 5 4 6 6 7 7 5 5 19 A I S Z V C - - - Operation (SP-1) = PCH; (SP-2) = PCL; PC = mn; SP = SP-2 B = B-1; if {B != 0} PC = PC + j PC = HL PC = IX PC = IY if {f} PC = mn PC = mn if {cc} PC = PC + e PC = PC + e (if e==0 next seq inst is executed) (SP-1) = XPC; (SP-2) = PCH; (SP-3) = PCL; XPC=xpc; PC = mn; SP = (SP-3) XPC=xpc; PC = mn PCL = (SP); PCH = (SP+1); XPC = (SP+2); SP = SP+3 PCL = (SP); PCH = (SP+1); SP = SP+2 if {f} PCL = (SP); PCH = (SP+1); SP = SP+2 IP = (SP); PCL = (SP+1); PCH = (SP+2); SP = SP+3 (SP-1) = PCH; (SP-2) = PCL; SP = SP - 2; PC = {R,v) v=10,18,20,28,38 only r - - - - LJP xpc,mn LRET RET RET f RETI RST v 10 13 8 8/2 12 10 - - - - - - - - - - - - - - - - - - - 19.18 Miscellaneous Instructions Instruction CCF IPSET 0 IPSET 1 IPSET 2 IPSET 3 IPRES LD A,EIR LD A,IIR LD A,XPC LD EIR,A LD IIR,A LD XPC,A NOP POP IP PUSH IP SCF clk 2 4 4 4 4 4 4 4 4 4 4 4 2 7 9 2 A f I S fr * fr * r f Z * * V C * 1 Operation CF = ~CF IP = {IP[5:0], 00} IP = {IP[5:0], 01} IP = {IP[5:0], 10} IP = {IP[5:0], 11} IP = {IP[1:0], IP[7:2]} A = EIR A = IIR A = MMU EIR = A IIR = A XPC = A No Operation IP = (SP); SP = SP+1 (SP-1) = IP; SP = SP-1 CF = 1 Users Manual 257 19.19 Privileged Instructions The privileged instructions are described in this section. Privilege means that an interrupt cannot take place between the privileged instruction and the following instruction. The three instructions below are privileged. LD SP,HL LD SP,IY LD SP,IX ; load the stack pointer The instructions to load the stack are privileged so that they can be followed by an instruction to load the stack segment (SSEG) register without the danger of an interrupt taking place with and incorrect association between the stack pointer and the stack segment register. For example, LD SP,HL IOI LD (STACKSEG),A The following instructions are privileged. IPSET 0 IPSET 1 IPSET 2 IPSET 3 IPRES POP IP ; shift IP left and set priority 00 in bits 1,0 ; rotate IP right 2 bits, restoring previous priority ; pop IP register from stack The instructions to modify the IP register are privileged so that they can be followed by a return instructions that is guaranteed to execute before another interrupt takes place. This avoids the possibility of an ever-growing stack. RETI ; pops IP from stack and then pops return address The instruction reti can be used to set both the return address and the IP in a single instruction. If preceded by a LD XPC, a complete jump or call to a computed address can be done with no possible interrupt. LD A,XPC ; get and set the XPC LD XPC,A The instruction LD XPC,A is privileged so that it can be followed by other code setting interrupt priority or program counter without an intervening interrupt. BIT B,(HL) ; test a bit in memory The instruction bit B,(HL) is privileged to make it possible to implement a semaphore without disabling interrupts. The following sequence is used. A bit is a semaphore, and the first task to set the bit owns the semaphore and has a right to manipulate the resources associated with the semaphore. BIT B,(HL) SET B,(HL) JP z,ihaveit ; here I dont have it The SET instruction has no effect on the flags. Since no interrupt takes place after the BIT instruction, if the flag is zero that means that the semaphore was not set when tested by the bit instruction and that the set instruction has set the semaphore. If an interrupt was allowed between the BIT and set instructions, another routine could set the semaphore and two routines could think that they both owned the semaphore. 258 Rabbit 3000 Microprocessor 20. DIFFERENCES RABBIT VS. Z80/Z180 INSTRUCTIONS The Rabbit is highly code compatible with the Z80 and Z180, and it is easy to port non I/O dependent code. The main areas of incompatibility are instructions that are concerned with I/O or particular hardware implementations. The more important instructions that were dropped from the Z80/Z180 are automatically simulated by an instruction sequence in the Dynamic C assembler. A few fairly useless instructions have been dropped and cannot be easily simulated. Code using these instructions should be rewritten. The following Z80/Z180 instructions have been dropped and there are no exact substitutes. DAA, HALT, DI, EI, IM 0, IM 1, IM 2, OUT, IN, OUT0, IN0, SLP, OUTI, IND, OUTD, INIR, OTIR, INDR, OTDR, TESTIO, MLT SP, RRD, RLD, CPI, CPIR, CPD, CPDR Most of these op codes deal with I/O devices and thus do not represent transportable code. The only opcodes that are not processor I/O related are MLT SP, DAA, RRD, RLD, CPI, CPIR, CPD, and CPDR. MLT SP is not a practical op code. The codes that are concerned with decimal arithmetic, DAA, RRD, and RLD, could be simulated, but the simulation is very inefficient. (The bit in the status register used for half carry is available and can be set and cleared using the PUSH AF and POP AF instructions to gain access.) Usually code that uses these instructions should be rewritten. The instructions CPI, CPIR, CPD, and CPDR are repeating compare instructions. These instructions are not very useful because the scan stops when equal compare is detected. Unequal compare would be more useful. They are difficult to simulate efficiently, so it is suggested that code using these instructions be rewritten, which in most cases should be quite easy. The following op codes are dropped. RST 0, RST 8, RST 0x30 The remaining RST instructions are kept, but the interrupt vector is relocated to a variable location the base of which is established by the EIR register. RST can be simulated by a call instruction, but this is not done automatically by the assembler since most of these instructions are used for debugging by Dynamic C. The following instruction has had its op code changed. EX (SP),HL - old opcode 0x0E3, new opcode - 0x0ED-0x054 Users Manual 259 The following instructions use different register names. LD LD LD LD A,EIR EIR,A IIR,A A,IIR ; was R register ; was I register The following Z80/Z180 instructions have been dropped and are not supported. Alternative Rabbit instructions are provided. Z80/Z180 Instructions Dropped CALL CC,ADR Rabbit Instructions to Use JR (JP) CALL ADR xxx: ncc,xxx ; reverse condition TST R ((HL),n) PUSH DE PUSH AF AND r ((HL), n) POP DE ; get a in h LD A,d POP DE 260 Rabbit 3000 Microprocessor 21. INSTRUCTIONS IN ALPHABETICAL ORDER WITH BINARY ENCODING Spreadsheet Conventions ALTD (A Column) Symbol Key Flag f fr r s Description ALTD selects alternate flags ALTD selects alternate flags and register ALTD selects alternate register ALTD operation is a special case IOI and IOE (I Column) Symbol Key Flag b d s Description IOI and IOE affect source and destination IOI and IOE affect destination IOI and IOE affect source Flag Register Key S * * L V 0 * * 0 1 * Z L/V * C Sign flag affected Description Sign flag not affected Zero flag affected Zero flag not affected L/V flag contains logical check result L/V flag contains arithmetic overflow result L/V flag is cleared L/V flag is affected Carry flag is affected Carry flag is not affected Carry flag is cleared Carry flag is set The L/V (logical/overflow) flag serves a dual purposeL/V is set to 1 for logical operations if any of the four most significant bits of the result are 1, and L/V is reset to 0 if all four of the most significant bits of the result are 0. 261 Users Manual Symbols Rabbit Z180 Meaning b b Bit select: 000 = bit 0, 010 = bit 2, 100 = bit 4, 110 = bit 6, 001 = bit 1, 011 = bit 3, 101 = bit 5, 111 = bit 7 cc cc Condition code select: 00 = NZ, 01 = Z, 10 = NC, 11 = C 7-bit (signed) displacement. Expressed in twos complement. Word register select destination: 00 = BC, 01 = DE, 10 = HL, 11 = SP Word register select alternate: 00 = BC ', 01 = DE ', 10 = HL ' d dd dd' e d ww j 8-bit (signed) displacement added to PC. Condition code select: 000 = NZ (non zero), 010 = NC (non carry), 100 = LZ* (logical zero), 110 = P (sign plus), MSB of a 16-bit constant. 16-bit constant. 8-bit constant or LSB of a 16-bit constant. 001 = Z (zero), 011 = C (carry), 101 = LO (logical one), 111 = M (sign minus) f f m mn n m mn n r, g Byte register select: 000 = B, 001 = C, g, g' 010 = D, 011 = E, 100 = H, 101 = L, 111 = A ww ss Word register select (source): 00 = BC, 01 = DE, 10 = HL, 11 = SP Restart address select: 010 = 0x0020, 011 = 0x0030, 100 = 0x0040, 101 = 0x0050, 111 = 0x0070 Word register select: 00 = BC, 01 = DE, 10 = IX, 11 = SP Word register select: 00 = BC, 01 = DE, 10 = IY, 11 = SP Word register select: 00 = BC, 01 = DE, 10 = HL, 11 = AF v v xx yy zz * xx yy zz Logical zero if all four of the most significant bits of the result are 0. Logical one if any of the four most significant bits of the result are 1. 262 Rabbit 3000 Microprocessor Instruction Byte 1 Byte 2 Byte 3 ----d------d--- Byte 4 clk 5 9 9 4 2 4 5 9 9 4 2 2 4 4 4 2 5 9 9 2 4 4 4 2 7 10 10 4 2 4 4 12 2 5 9 9 4 2 2 8 12 12 4 4 2 2 5 15 15 15 A fr fr fr fr fr fr fr fr fr fr fr fr f f f fr fr fr fr f f fr fr f f f f fr f f f f f f f f r f f f I S Z V C s * * V s * * V s * * V * * V * * V * * V s * * V s * * V s * * V * * V * * V - - - - - - - - - - s * * L s * * L s * * L * * L * * L * * L * * L * * L s - * s - * s - * - * * * 0 * * 0 * * 0 - - - - s * * V s * * V s * * V * * V * * V - - b * * V b * * V b * * V - - - - * * V - - * * * * * * * * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 * * * * * * - ADC A,(HL) 10001110 ADC A,(IX+d) 11011101 10001110 ADC A,(IY+d) 11111101 10001110 ADC A,n 11001110 ----n--ADC A,r 10001-rADC HL,ss 11101101 01ss1010 ADD A,(HL) 10000110 ADD A,(IX+d) 11011101 10000110 ADD A,(IY+d) 11111101 10000110 ADD A,n 11000110 ----n--ADD A,r 10000-rADD HL,ss 00ss1001 ADD IX,xx 11011101 00xx1001 ADD IY,yy 11111101 00yy1001 ADD SP,d 00100111 ----d--ALTD 01110110 AND (HL) 10100110 AND (IX+d) 11011101 10100110 AND (IY+d) 11111101 10100110 AND HL,DE 11011100 AND IX,DE 11011101 11011100 AND IY,DE 11111101 11011100 AND n 11100110 ----n--AND r 10100-rBIT b,(HL) 11001011 01-b-110 BIT b,(IX+d)) 11011101 11001011 BIT b,(IY+d)) 11111101 11001011 BIT b,r 11001011 01-b--rBOOL HL 11001100 BOOL IX 11011101 11001100 BOOL IY 11111101 11001100 CALL mn 11001101 ----n--CCF 00111111 CP (HL) 10111110 CP (IX+d) 11011101 10111110 CP (IY+d) 11111101 10111110 CP n 11111110 ----n--CP r 10111-rCPL 00101111 DEC (HL) 00110101 DEC (IX+d) 11011101 00110101 DEC (IY+d) 11111101 00110101 DEC IX 11011101 00101011 DEC IY 11111101 00101011 DEC r 00-r-101 DEC ss 00ss1011 ss= 00-BC, 01-DE, 10-HL, 11-SP DJNZ j 00010000 --(j-2)EX (SP),HL 11101101 01010100 EX (SP),IX 11011101 11100011 EX (SP),IY 11111101 11100011 ----d------d--- ----d------d--- ----d------d--- 01-b-110 01-b-110 ----m--- ----d------d--- ----d------d--- fr r r r Users Manual 263 Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A I S Z V C b * b * b * * * * * * V V V V - EX AF,AF' 00001000 EX DE,HL 11101011 EX DE',HL 11100011 EX DE,HL' 01110110 11100011 EX DE',HL' 01110110 11100011 EXX 11011001 INC (HL) 00110100 INC (IX+d) 11011101 00110100 ----d--INC (IY+d) 11111101 00110100 ----d--INC IX 11011101 00100011 INC IY 11111101 00100011 INC r 00-r-100 INC ss 00ss0011 ss= 00-BC, 01-DE, 10-HL, 11-SP IOE 11011011 IOI 11010011 IPSET 0 11101101 01000110 IPSET 1 11101101 01010110 IPSET 2 11101101 01001110 IPSET 3 11101101 01011110 IPRES 11101101 01011101 JP (HL) 11101001 JP (IX) 11011101 11101001 JP (IY) 11111101 11101001 JP f,mn 11-f-010 ----n--- ----m--JP mn 11000011 ----n--- ----m--JR cc,e 001cc000 --(e-2)JR e 00011000 --(e-2)Note: If byte following op code is zero, is executed. If byte is -2 (11111110) jr LCALL xpc,mn 11001111 ----n--- ----m--LD (BC),A 00000010 LD (DE),A 00010010 LD (HL),n 00110110 ----n--LD (HL),r 01110-rLD (HL+d),HL 11011101 11110100 ----d--LD (IX+d),HL 11110100 ----d--LD (IX+d),n 11011101 00110110 ----d--LD (IX+d),r 11011101 01110-r- ----d--LD (IY+d),HL 11111101 11110100 ----d--LD (IY+d),n 11111101 00110110 ----d--LD (IY+d),r 11111101 01110-r- ----d--LD (mn),A 00110010 ----n--- ----m--LD (mn),HL 00100010 ----n--- ----m--LD (mn),IX 11011101 00100010 ----n--LD (mn),IY 11111101 00100010 ----n--LD (mn),ss 11101101 01ss0011 ----n--LD (SP+n),HL 11010100 ----n--LD (SP+n),IX 11011101 11010100 ----n--LD (SP+n),IY 11111101 11010100 ----n--- 2 2 s 2 s 4 s 4 s 2 8 f 12 f 12 f 4 4 2 fr 2 r 2 - - - 2 - - - 4 - - - 4 - - - 4 - - - 4 - - - 4 - - - 4 - - - 6 - - - 6 - - - 7 - - - 7 - - - 5 - - - 5 - - - next sequential instruction is to itself. --xpc--- 19 - - - 7 d - - - 7 d - - - 7 d - - - 6 d - - - 13 d - - - 11 d - - - ----n--11 d - - - 10 d - - - 13 d - - - ----n--11 d - - - 10 d - - - 10 d - - - 13 d - - - ----m--15 d - - - ----m--15 d - - - ----m--15 d - - - 11 - - - 13 - - - 13 - - - - 264 Rabbit 3000 Microprocessor Instruction LD A,(BC) LD A,(DE) LD A,(mn) LD A,EIR LD A,IIR LD A,XPC LD dd,(mn) LD dd',BC LD dd',DE LD dd,mn LD bc,mn LD de,mn LD hl,mn LD sp,mn LD EIR,A LD HL,(HL+d) LD HL,(IX+d) LD HL,(IY+d) LD HL,(mn) LD HL,(SP+n) LD HL,IX LD HL,IY LD IIR,A LD IX,(mn) LD IX,(SP+n) LD IX,HL LD IX,mn LD IY,(mn) LD IY,(SP+n) LD IY,HL LD IY,mn LD r,(HL) LD r,(IX+d) LD r,(IY+d) LD r,g LD r,n LD SP,HL LD SP,IX LD SP,IY LD XPC,A LDD LDDR LDI LDIR LDP (HL),HL LDP (IX),HL LDP (IY),HL LDP (mn),HL LDP (mn),IX LDP (mn),IY Byte 1 00001010 00011010 00111010 11101101 11101101 11101101 11101101 11101101 11101101 00dd0001 00000001 00010001 00100001 00110001 11101101 11011101 11100100 11111101 00101010 11000100 11011101 11111101 11101101 11011101 11011101 11011101 11011101 11111101 11111101 11111101 11111101 01-r-110 11011101 11111101 01-r---g 00-r-110 11111001 11011101 11111101 11101101 11101101 11101101 11101101 11101101 11101101 11011101 11111101 11101101 11011101 11111101 Byte 2 Byte 3 Byte 4 clk 6 6 9 A r r r I S Z V C s - - - s - - - s - - - * * s * * - ----n--- ----m--01010111 01011111 01110111 01dd1011 01dd1001 01dd0001 ----n--... ... ... ... 01000111 11100100 ----d--11100100 ----n------n--01111100 01111100 01001111 00101010 11000100 01111101 00100001 00101010 11000100 01111101 00100001 ----n--- ----m--- ----m--- 4 fr 4 fr 4 r 13 r 4 4 6 r ----d------d------m--- ----n------n------n------n------n------n--- ----m--- ----m------m--- ----m--- 01-r-110 ----d--01-r-110 ----d------n--11111001 11111001 01100111 10101000 10111000 10100000 10110000 01100100 01100100 01100100 01100101 ----n--01100101 ----n--01100101 ----n--- ----m------m------m--- 4 11 9 11 11 9 4 4 4 13 11 4 8 13 11 4 8 5 9 9 2 4 2 4 4 4 10 6+7i 10 6+7i 12 12 12 15 15 15 r r r r r r r s s s s s s r r r r r s s s d d d d - - * * * * - - Users Manual 265 Instruction LDP HL,(HL) LDP HL,(IX) LDP HL,(IY) LDP HL,(mn) LDP IX,(mn) LDP IY,(mn) LJP nbr,mn LRET MUL NEG NOP OR (HL) OR (IX+d) OR (IY+d) OR HL,DE OR IX,DE OR IY,DE OR n OR r POP IP POP IX POP IY POP zz PUSH IP PUSH IX PUSH IY PUSH zz RES b,(HL) RES b,(IX+d) RES b,(IY+d) RES b,r RET RET f RETI RL (HL) RL (IX+d) RL (IY+d) RL DE RL r RLA RLC (HL) RLC (IX+d) RLC (IY+d) RLC r RLCA RR (HL) RR (IX+d) RR (IY+d) RR DE RR HL RR IX RR IY Byte 1 11101101 11011101 11111101 11101101 11011101 11111101 11000111 11101101 11110111 11101101 00000000 10110110 11011101 11111101 11101100 11011101 11111101 11110110 10110-r11101101 11011101 11111101 11zz0001 11101101 11011101 11111101 11zz0101 11001011 11011101 11111101 11001011 11001001 11-f-000 11101101 11001011 11011101 11111101 11110011 11001011 00010111 11001011 11011101 11111101 11001011 00000111 11001011 11011101 11111101 11111011 11111100 11011101 11111101 Byte 2 01101100 01101100 01101100 01101101 01101101 01101101 ----n--01000101 01000100 Byte 3 Byte 4 clk A I S Z V C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * V L L L L L L L L L L L L L L L L L L L L L L L L * 0 0 0 0 0 0 0 0 * * * * * * * * * * * * * * * * * * ----n------n------n------m--- ----m------m------m----nbr--- 10110110 ----d--10110110 ----d--11101100 11101100 ----n--01111110 11100001 11100001 01110110 11100101 11100101 10-b-110 11001011 ----d--11001011 ----d--10-b--r- 10-b-110 10-b-110 01001101 00010110 11001011 ----d--11001011 ----d--00010-r00000110 11001011 ----d--11001011 ----d--00000-r00011110 11001011 ----d--11001011 ----d--- 00010110 00010110 00000110 00000110 00011110 00011110 11111100 11111100 10 10 10 13 13 13 10 13 12 4 fr 2 5 fr 9 fr 9 fr 2 fr 4 f 4 f 4 fr 2 fr 7 9 9 7 r 9 12 12 10 10 13 13 4 r 8 8/2 12 10 f 13 f 13 f 2 fr 4 fr 2 fr 10 f 13 f 13 f 4 fr 2 fr 10 f 13 f 13 f 2 fr 2 fr 4 f 4 f s s s d d d b b b b b b b b b 266 Rabbit 3000 Microprocessor Instruction Byte 1 Byte 2 00011-r- Byte 3 Byte 4 clk 4 2 10 13 13 4 2 8 9 9 5 4 2 4 2 10 13 13 4 10 13 13 4 10 13 13 4 10 13 13 4 5 9 9 4 2 5 9 9 4 2 10 A fr fr f f f fr fr fr fr fr fr fr fr f I S Z V C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * L L L L L V V V V V V L L L L L L L L L L L L V V V V V L L L L L * * * * * * * * * * * * * 1 * * * * * * * * * * * * * * * * * 0 0 0 0 0 - RR r 11001011 RRA 00011111 RRC (HL) 11001011 RRC (IX+d) 11011101 RRC (IY+d) 11111101 RRC r 11001011 RRCA 00001111 RST v 11-v-111 SBC (IX+d) 11011101 SBC (IY+d) 11111101 SBC A,(HL) 10011110 SBC A,n 11011110 SBC A,r 10011-rSBC HL,ss 11101101 SCF 00110111 SET b,(HL) 11001011 SET b,(IX+d) 11011101 SET b,(IY+d) 11111101 SET b,r 11001011 SLA (HL) 11001011 SLA (IX+d) 11011101 SLA (IY+d) 11111101 SLA r 11001011 SRA (HL) 11001011 SRA (IX+d) 11011101 SRA (IY+d) 11111101 SRA r 11001011 SRL (HL) 11001011 SRL (IX+d) 11011101 SRL (IY+d) 11111101 SRL r 11001011 SUB (HL) 10010110 SUB (IX+d) 11011101 SUB (IY+d) 11111101 SUB n 11010110 SUB r 10010-rXOR (HL) 10101110 XOR (IX+d) 11011101 XOR (IY+d) 11111101 XOR n 11101110 XOR r 10101-rZINTACK (interrupt) 00001110 11001011 ----d--11001011 ----d--00001-r- 00001110 00001110 b b b [v=2,3,4,5,7 only] 10011110 ----d--10011110 ----d------n--01ss0010 11-b-110 11001011 11001011 11-b--r00100110 11001011 11001011 00100-r00101110 11001011 11001011 00101-r00111110 11001011 11001011 00111-r- s s s ----d------d--- 11-b-110 11-b-110 b b b r f f f fr f f f fr f f f fr fr fr fr fr fr fr fr fr fr fr b b b b b b b b b s s s ----d------d--- 00100110 00100110 ----d------d--- 00101110 00101110 ----d------d--- 00111110 00111110 10010110 ----d--10010110 ----d------n--- 10101110 ----d--10101110 ----d------n--- s s s Users Manual 267 268 Rabbit 3000 Microprocessor APPENDIX A. THE RABBIT PROGRAMMING PORT The programming port provides a standard physical and electrical interface between a Rabbit-based system and the Dynamic C programming platform. A special interface cable and converter connects a PC serial port to the programming port. The programming port is implemented by means of a 10-pin standard 2 mm connector. (Of course the user can change the physical implementation of the connector if he so desires.) With this setup the PC can communicate with the target, reset it and reboot it. The DTR line on the PC serial interface is used to drive the target reset line, which should be drivable by an external CMOS driver. The STATUS pin is used to by the Rabbit-based target to request attention when a breakpoint is encountered in the target under test. The SMODE pins are pulled up by a +5 V/+3 V level from the interface. They should be pulled down on the board when the interface is not in use by approximately 5 k resistors to ground. The target under test provides the +5 V or +3 V to the interface cable which is used to power the RS-232 driver and receiver. PROGRAMMING PORT PIN ASSIGNMENTS (Rabbit LQFP pins are shown in parenthesis) 1. 2. 3. 4. 5. 6. 7. 8. 9. RXA (66) GND CKLKA (117) +5 V/+3 V /RESET TXA (67) n.c. STATUS (output) (4) SMODE0 (45) ~50 kW ~50 kW ~10 kW 1 3 5 7 9 2 4 6 8 10 + + + Programming Port Pin Numbers ~50 kW ~50 kW GND GND 10. SMODE1 (44) Figure A-1. Rabbit Programming Port Users Manual 269 A.1 Use of the Programming Port as a Diagnostic/Setup Port The programming port, which is already in place, can serve as a convenient communications port for field setup, diagnosis or other occasional communication need (for example, as a diagnostic port). There are several ways that the port can be automatically integrated into the users software scheme. If the purpose of the port is simply to perform a setup function, that is, write setup information to flash memory, then the controller can be reset through the programming port, followed by a cold boot to start execution of a special program dedicated to this functionality. The standard programming cable connects the programming interface to a PC programming port. The /RESET line can be asserted by manipulating DTR on the PC serial port and the STATUS line can be read by the PC as DSR on the serial port. The PC can restart the target by pulsing reset and then, after a short delay, sending a special character string at 2400 bps. To simply restart the BIOS, the string 0x80, 0x24, 0x80 can be sent. When the BIOS is started, it can tell whether the PROG connector on the programming cable is connected because the SMODE1, SMODE0 pins are sensed as high. This will cause the BIOS to think that it should enter programming mode. The Dynamic C programming mode then can have an escape message that will enable the diagnostic serial port function. Another approach to enabling the diagnostic port is to poll the serial port periodically to see if communication needs to begin or to enable the port and wait for interrupts. The SMODE pins can be used for signaling and can be detected by a poll. However, recall that the SMODE pins have a special function after reset and will inhibit normal reset behavior if not held low. The pull-up resistors on RXA and CLKA prevent spurious data reception that might take place if the pins floated. If the clocked serial mode is used, the serial port can be driven by having two toggling lines that can be driven and one line that can be sensed. This allows a conversation with a device that does not have an asynchronous serial port but that has two output signal lines and one input signal line. The line TXA (also called PC6) is zero after reset if cold boot mode is not enabled. A possible way to detect the presence of a cable on the programming port is for the cable to connect TXA to one of the SMODE pins and then test for the connection by raising PC6 and reading the SMODE pin after the cold boot mode has been disabled. A.2 Alternate Programming Port The programming port uses Serial Port A. If the user needs to use Serial Port A in an application, an alternate method of programming is possible using the same 10-pin programming port. For his own application the user should use the alternate I/O pins for port A that share pins with Parallel Port D. The TXA and RXA pins on the 10-pin programming port are then a parallel port output and parallel port input using pins 6 and 7 on Parallel Port C. Using these two ports plus the STATUS pin as an output clock, the user can create a synchronous clocked communication port using instructions to toggle the clock and data. Another Rabbit-based board can be used to translate the clocked serial signal to 270 Rabbit 3000 Microprocessor an asynchronous signal suitable for the PC. Since the target controls the clock for both send and receive, the data transmission proceeds at a rate controlled by the target board under development. This scheme does not allow for an interrupt, and it is not desirable to use up an external interrupt for this purpose. The serial port may be used, if desired, During program load because there is no conflict with the users program at compile load time. However, the users program will conflict during debugging. The nature of the transmissions during debugging is such that the user program starts at a break point or otherwise wants to get the attention of the PC. The other type of message is when the PC wants to read or write target memory while the target is running. The target toggling the clock can simply send a clocked serial message to get the attention of the PC. The intermediate communications board can accept these unsolicited messages using its clocked serial port. To prevent overrunning the receiver, the target can wait for a handshake signal on one of the SMODE lines or there can be suitable pre-arranged delays. If the PC wants attention from the target it can set a line to request attention (SMODE). The target will detect this line in the periodic interrupt routine and handle the complete message in the periodic interrupt routine. This may slow down target execution, but the interrupts will be enabled on the target while the message is read. The intermediate board could split long messages into a series of shorter messages if this is a problem. A.3 Suggested Rabbit Crystal Frequencies Table A-1 provides a list of suggested Rabbit operating frequencies. The numbers in Table A-1 are based on the following assumptions: spectrum spreader set to normal, doubler in use (52/48 duty cycle), and a combined 6 ns for clock to address and data setup times. The crystal can be half the operating frequency if the clock doubler is used up to 27 MHz. Beyond this operating clock speed, it is necessary to use an X1 crystal or an external oscillator because asymmetry in the waveform generated by the oscillator becomes a variation in the clock speed if the clock speed is doubled. Users Manual 271 Table A-1. Preliminary Crystal Frequencies, Memory Access Times, and Baud Rates Crystal Frequency (MHz) 1.8432 3.6864 7.3728 9.216 11.0592 12.9024 14.7456 18.432 22.1184 25.8048 Doubled Frequency (MHz) 3.6864 7.3728 14.7456 18.432 22.1184 25.8048 29.4912 36.864 44.2368 51.6096 Doubled Period (ns) 271 136 68 54 45 39 34 27 23 19 Access Time (ns) 522 257 124 97 79 67 57 44 35 29 Divisor for 115,200 baud 4 8 16 20 24 28 32 40 48 56 Non-Stock Crystals 20.2752 21.1968 23.04 23.9616 24.8832 26.7264 40.5504 42.3936 46.08 47.9232 49.7664 53.4528 25 24 22 21 20 19 39 37 33 32 30 27 44 46 50 52 54 58 272 Rabbit 3000 Microprocessor APPENDIX B. RABBIT 3000 REVISIONS Since its release, the Rabbit 3000 microprocessor has gone through one revision. The revision reflects bug fixes, improvements, and the introduction of new features. All Rabbit 3000 revisions are pin-compatible, and transparently replace previous versions of the chip. The Rabbit 3000 has been supplied in the following versions. 1. Original Rabbit 3000Available in two packages and identified by IL1T for the LQFP package and IZ1T for the TFBGA package. The LQFP package began shipping in March 2002, and the TFBGA package began shipping in January 2003. There were several bugs: (a) Port A decode bugThis bug is documented in TN228, Rabbit 3000 Parallel Port F Bug. The problem involves an incomplete address decode of the data output register for Parallel Port A. If Parallel Port A is used as an output or is used as the bidirectional bus for the slave port, then writing to any of the Parallel Port F registers will cause a spurious write to the Parallel Port A register. (b) LDIR/LDDR with wait statesThis bug is documented in Section 19.16. The nature of the problem is such that first iteration of LDIR/LDDR uses the correct number of wait states for both the read and the write. However, all subsequent iterations use the number of waits programmed for the memory located at the write address for both the read and the write cycles. This becomes a problem when moving a block of data from a slow memory device requiring wait states to a fast memory device requiring no wait states. (c) Interrupt after I/O with Short /CSx enabledThis bug is documented in Section 7.5. When the short chip select option is enabled, the interrupt sequence will attempt to write the return address to the stack if an interrupt takes place immediately after an internal or an external I/O instruction. The chip select will be suppressed during the write cycle, and the correct return address will not be stored on the stack. This happens only when an interrupt takes place immediately after an I/O instruction when the short chip select option is enabled. (d) IrDA bugThis bug is documented in TN236, Rabbit 3000 IrDA Bug. When configured to operate in the IrDA mode, the serial port may at times generate an extra pulse before the start bit is transmitted. This pulse may appear either before a multi-character transmission or before a single-character transmission. If the beginning of the start bit coincides with when the IrDA pulse generator output is high, there will be a spurious 1/16th-bit cell pulse on the transmit output. Users Manual 273 2. First revision (Rabbit 3000A)Available in two packages and identified by IL2T for the LQFP package and IZ2T for the TFBGA package. This version began shipping in August 2003. All the bugs in the original Rabbit 3000 were fixed. The Rabbit 3000A contains a number of new features and improvements. (a) A new mode of operation known as System/User mode was added. This mode provides a framework for separating application code from system-critical code, which helps prevent application code from crashing the entire device. System/User mode is described in detail in Appendix C. (b) The ability to write-protect 64 KB physical memory blocks was added, with the option of further protecting two of the 64 KB blocks in 4 KB segments. Attempts to write to a protected block triggers a Priority 3 write-protection interrupt. (c) Stack protection was added. Writing outside set stack boundaries triggers a Priority 3 stack violation interrupt. (d) RAM segment relocation was added. This feature allows a 1, 2, or 4 KB segment of the logical memory space to be mapped as data (or for program execution) when separate I/D space is enabled. (e) Secondary watchdog timer added. The secondary watchdog timer was added to function as a safety net for the periodic interrupt. (f) Two new opcodes were added to support multiply-and-add and multiply-andsubtract operations on large unsigned integers. These operations can be used to speed up public-key calculations. (g) Six new opcodes were added to support block-copy operations from I/O addresses to memory addresses and vice-versa. (h) The I/O address space has been expanded to 16 bits to make room for new peripherals. (i) Two new features were added to further expand the external I/O interface capabilities of the processor. First, an option was added to enable or disable the auxiliary I/O bus interface for a given I/O bank. If the auxiliary I/O bus is disabled for a given external I/O bank, the processor uses the memory bus for external I/O transactions. The second feature is the addition of an option for enabling hold time for external I/O read operations. The option shortens the read strobes by one clock cycle. (j) The low-power capability of the processor was further expanded with the addition of short chip select timing for all clock modes (except for divide-by-one mode) and for reads, writes, or both. (k) The PWM outputs can now trigger a PWM interrupt each cycle or every other/fourth/eighth cycle. In addition, the PWM output can be suppressed every other cycle, three out of every four cycles, or seven out of every eight cycles. These options were added to provide support for driving servos in addition to generating audio using the Rabbit 3000A. 274 Rabbit 3000 Microprocessor (l) The quadrature decoder hardware can be configured to use a 10-bit counter in place of the existing 8-bit counter. (m)An option was added to alternatively multiplex PWM outputs, slave chip select (/SCS), and Serial Ports E and F transmit and receive clocks on other pins. (n) The Schmitt trigger IC normally required for the low power 32.768 kHz oscillator circuit is now integrated inside the Rabbit 3000A. NOTE: Based on this modification, a new low-power oscillator circuit is recommended for use with Rabbit 3000A-based systems. Please refer to TN235, External 32.768 kHz Oscillator Circuits, for more information on the circuit. Users Manual 275 B.1 Discussion of Fixes and Improvements Table B-1 lists the bug fixes, improvements, and additions for the various revisions of the Rabbit 3000. Table B-1. Summary of Rabbit 3000 Improvements and Fixes Description Rabbit 3000 Rabbit 3000A (IL1T/IZ1T) (IL2T/IZ2T) ID Registers for version/revision identification. System/User mode. Memory protection scheme. Stack protection. RAM segment relocation. Secondary watchdog timer. Multiply-add and multiply-subtract. Variants of block move opcodes. 16-bit internal I/O address space. External I/O interface enhancements. Expanded low-power capability. PWM improvements. Quadrature decoder improvements. Integrated Schmitt trigger for 32 kHz oscillator input. Alternate output port connection for numerous peripherals. Port A decode bug fix. LDIR/LDDR with wait states bug fix. Interrupt after I/O with short /CSx enabled bug fix. IrDA bug fix. X X X X X X X X X X X X X X X X X X X X 276 Rabbit 3000 Microprocessor B.1.1 Rabbit Internal I/O Registers Table B-2 summarizes the reset state of the new I/O registers added in the Rabbit 3000A revision. Table B-3 summarizes the reset state of the existing I/O registers with new features. Table B-2. Reset State of New Rabbit 3000A I/O Registers Register Name Secondary Watchdog Timer Register RAM Segment Register Write Protect Control Register Stack Limit Control Register Stack Low Limit Register Stack High Limit Register Write Protect Low Register Write Protect High Register Write Protect Segment A Register Write Protect Segment A Low Register Write Protect Segment A High Register Write Protect Segment B Register Write Protect Segment B Low Register Write Protect Segment B High Register Real Time Clock User Enable Register Slave Port User Enable Register Parallel Port A User Enable Register Parallel Port B User Enable Register Parallel Port C User Enable Register Parallel Port D User Enable Register Parallel Port E User Enable Register Parallel Port F User Enable Register Parallel Port G User Enable Register Input Capture User Enable Register I/O Bank User Enable Register PWM User Enable Register Quad Decode User Enable Register Users Manual Mnemonic SWDTR RAMSR WPCR STKCR STKLLR STKHLR WPLR WPHR WPSAR WPSALR WPSAHR WPSBR WPSBLR WPSBHR RTUER SPUER PAUER PBUER PCUER PDUER PEUER PFUER PGUER ICUER IBUER PWUER QDUER I/O R/W Address 0x000C 0x0448 0x0440 0x0444 0x0445 0x0446 0x0460 0x0461 0x0480 0x0481 0x0482 0x0484 0x0485 0x0486 0x0300 0x0320 0x0330 0x0340 0x0350 0x0360 0x0370 0x0338 0x0348 0x0358 0x0380 0x0388 0x0390 W W W W W W W W W W W W W W W W W W W W W W W W W W W Reset 11111111 00000000 00000000 00000000 xxxxxxxx xxxxxxxx 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 277 Table B-2. Reset State of New Rabbit 3000A I/O Registers (continued) Register Name External Interrupt User Enable Register Timer A User Enable Register Timer B User Enable Register Serial Port A User Enable Register Serial Port B User Enable Register Serial Port C User Enable Register Serial Port D User Enable Register Serial Port E User Enable Register Serial Port F User Enable Register Enable Dual-Mode Register Quad Decode Count1 High Register Quad Decode Count 2 High Register Mnemonic IUER TAUER TBUER SAUER SBUER SCUER SDUER SEUER SFUER EDMR QDC1HR QDC2HR I/O R/W Address 0x0398 0x03A0 0x03B0 0x03C0 0x03D0 0x03E0 0x03F0 0x03C8 0x03D8 0x0420 0x0095 0x0097 W W W W W W W W W W R R Reset 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx 278 Rabbit 3000 Microprocessor Table B-3. Reset State of I/O Registers Modified in Rabbit 3000A Register Name Global Power Save Control Register Global Revision Register MMU Expanded Code Register Memory Timing Control Register Breakpoint/Debug Control Register I/O Bank 0 Control Register I/O Bank 1 Control Register I/O Bank 2 Control Register I/O Bank 3 Control Register I/O Bank 4 Control Register I/O Bank 5 Control Register I/O Bank 6 Control Register I/O Bank 7 Control Register PWM LSB 0 Register PWM LSB 1 Register PWM LSB 2 Register PWM LSB 3 Register Quad Decode Control Register Mnemonic GPSCR GREV MECR MTCR BDCR IB0CR IB1CR IB2CR IB3CR IB4CR IB5CR IB6CR IB7CR PWL0R PWL1R PWL2R PWL3R QDCR I/O R/W Address 0x000D 0x002F 0x0018 0x0019 0x001C 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 0x0088 0x008A 0x008C 0x008E 0x0091 W R R/W W W W W W W W W W W W W W W W Rabbit 3000 Reset 0000x000 0xx00000 xxxxx000 xxxx0000 0xxxxxxx 000000xx 000000xx 000000xx 000000xx 000000xx 000000xx 000000xx 000000xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00xx0000 Rabbit 3000A Reset 00000000 0xx00001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 xxxxx00x xxxxx00x xxxxx00x xxxxx00x 00000000 Users Manual 279 B.1.2 Peripheral and ISR Address Table B-4. Rabbit 3000 I/O Address Ranges and Interrupt Service Vectors On-Chip Peripheral System Management Memory Management Slave Port Parallel Port A Parallel Port F Parallel Port B Parallel Port G Parallel Port C Input Capture Parallel Port D Parallel Port E External I/O Control Pulse Width Modulator Quadrature Decoder External Interrupts Timer A Timer B Serial Port A (async/cks) Serial Port E (async/HDLC) Serial Port B (async/cks) Serial Port F (async/HDLC) Serial Port C (async/cks) Serial Port D (async/cks) RST 10 instruction RST 18 instruction RST 20 instruction RST 28 instruction I/O Address Range 0x00000x000F 0x00100x001F and 0x04000x04FF 0x00200x002F 0x00300x0037 0x00380x003F 0x00400x0047 0x00480x004F 0x00500x0055 0x00560x005F 0x00600x006F 0x00700x007F 0x00800x0087 0x00880x008F 0x00900x0097 0x00980x009F 0x00A00x00AF 0x00B00x00BF 0x00C00x00C7 0x00C80x00CF 0x00D00x00D7 0x00D80x00DF 0x00E00x00E7 0x00F00x00F7 n/a n/a n/a n/a ISR Starting Address {R[7:1], 0, 0x00} No interrupts {IIR[7:1], 0, 0x80} No interrupts No interrupts No interrupts No interrupts No interrupts {IIR[7:1], 1, 0xA0} No interrupts No interrupts No interrupts No interrupts {IIR[7:1], 1, 0x90} INT0 {EIR, 0x00} INT1 {EIR, 0x10} {IIR[7:1], 0, 0xA0} {IIR[7:1], 0, 0xB0} {IIR[7:1], 0, 0xC0} {IIR[7:1], 1, 0xC0} {IIR[7:1], 0, 0xD0} {IIR[7:1], 1, 0xD0} {IIR[7:1], 0, 0xE0} {IIR[7:1], 0, 0xF0} {IIR[7:1], 0, 0x20} {IIR[7:1], 0, 0x30} {IIR[7:1], 0, 0x40} {IIR[7:1], 0, 0x50} 280 Rabbit 3000 Microprocessor Table B-4. Rabbit 3000 I/O Address Ranges and Interrupt Service Vectors (continued) (continued) On-Chip Peripheral SYSCALL instruction RST 38 instruction Secondary Watchdog Stack Limit Violation Write Protection Violation System Mode Violation I/O Address Range n/a n/a 0x000C n/a n/a n/a ISR Starting Address {IIR[7:1], 0, 0x60} {IIR[7:1], 0, 0x70} {IIR[7:1], 0, 0x10} {IIR[7:1], 1, 0xB0} {IIR[7:1], 0, 0x90} {IIR[7:1], 1, 0x80} Users Manual 281 B.1.3 Revision-Level ID Register Two read-only registers are provided to allow software to identify the Rabbit microprocessor and recognize the features and capabilities of the chip. Five bits in each of these registers are unique to each version of the chip. One register identifies the CPU (GCPU), and the other register is reserved for revision identification (GREV). The CPU identification (GCPU) of all revisions of the Rabbit 3000 microprocessor is the same. Rabbit 3000 revisions are differentiated by the value in the GREV register. Table B-5 summarizes the processor identification information for the different Rabbit 3000 versions. Table B-5. Rabbit 3000 Revision Identification Information Processor Revision Rabbit 3000 Rabbit 3000A Package Identifier IL1T, IZ1T IL2T, IZ2T GCPU [4:0] 00001 00001 GREV [4:0] 00000 00001 282 Rabbit 3000 Microprocessor B.1.4 System/User Mode By default, all of the hardware is accessible by the programmer. However, if a control bit in the Enable Dual Mode Register (EDMR) is set to one, two operating modes, System and User, become available. The System mode is just like the normal operating mode, but the User mode restricts program access to the hardware and to the System mode. Individual peripherals may be enabled for User mode access in the User Enable registers listed below. When enabled for User mode access, a peripheral interrupt (if it is capable of generating an interrupt) can only be requested at interrupt priority level -2 or -1, and it is assumed that the interrupt service routine will be executed by User mode code. Note that the processor automatically enters the System mode when entering the ISR area in response to an interrupt, and the User mode must be specifically entered before continuing with the interrupt service routine. The System/User mode is discussed in great detail in Appendix C. Users Manual 283 B.1.5 Memory Protection The ability to inhibit writes to physical memory was added. The sixteen 64 KB physical memory blocks can be individually protected, and two of those blocks can additionally be subdivided and protected at a granularity of 4 KB. When a write is attempted, a new Priority 3 write-protection interrupt request is generated. The write-protection can be enabled for the User mode only or for all modes (see Appendix C for more information). WPHR = 0x85 WPLR = 0x6C WPSAR = 0x04 WPSAHR = 0x07 WPSALR = 0xCC 0x4FFFF 0xFFFFF 0x48000 0x00000 0x40000 Figure B-1. Sample Memory Protection Layout The new memory-protection registers are listed in Table B-6 through Table B-11. Table B-6. Write Protect Control Register Write Protect Control Register Bit(s) 7:1 0 0 1 write-protection in System and User modes. Value (WPCR) Description These bits are reserved and should be written with zeros. write-protection in User mode only. (Address = 0x0440) 284 Rabbit 3000 Microprocessor Table B-7. Write Protect Low Register Write Protect Low Register Bit(s) 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 1 Enable 64K write-protect for physical address 0x000000x0FFFF. Enable 64K write-protect for physical address 0x100000x1FFFF. Disable 64K write-protect for physical address 0x000000x0FFFF. Enable 64K write-protect for physical address 0x200000x2FFFF. Disable 64K write-protect for physical address 0x100000x1FFFF. Enable 64Kwrite-protect for physical address 0x300000x3FFFF. Disable 64K write-protect for physical address 0x200000x2FFFF. Enable 64K write-protect for physical address 0x400000x4FFFF. Disable 64K write-protect for physical address 0x300000x3FFFF. Enable 64K write-protect for physical address 0x500000x5FFFF. Disable 64Kwrite-protect for physical address 0x400000x4FFFF. Enable 64K write-protect for physical address 0x600000x6FFFF. Disable 64K write-protect for physical address 0x500000x5FFFF. Enable 64K write-protect for physical address 0x700000x7FFFF. Disable 64K write-protect for physical address 0x600000x6FFFF. Value 0 (WPLR) Description Disable 64K write-protect for physical address 0x700000x7FFFF. (Address = 0x0460) Users Manual 285 Table B-8. Write Protect High Register Write Protect High Register Bit(s) 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 1 Enable 64K write-protect for physical address 0x800000x8FFFF. Enable 64K write-protect for physical address 0x900000x9FFFF. Disable 64K write-protect for physical address 0x800000x8FFFF. Enable 64K write-protect for physical address 0xA00000xAFFFF. Disable 64K write-protect for physical address 0x900000x9FFFF. Enable 64K write-protect for physical address 0xB00000xBFFFF. Disable 64K write-protect for physical address 0xA00000xAFFFF. Enable 64K write-protect for physical address 0xC00000xCFFFF. Disable 64K write-protect for physical address 0xB00000xBFFFF. Enable 64K write-protect for physical address 0xD00000xDFFFF. Disable 64K write-protect for physical address 0xC00000xCFFFF. Enable 64K write-protect for physical address 0xE00000xEFFFF. Disable 64K write-protect for physical address 0xD00000xDFFFF. Enable 64K write-protect for physical address 0xF00000xFFFFF. Disable 64K write-protect for physical address 0xE00000xEFFFF. Value 0 (WPHR) Description Disable 64K write-protect for physical address 0xF00000xFFFFF. (Address = 0x0461) Table B-9. Write Protect Segment x Register Write Protect Segment x Register (WPSAR) (WPSBR) Bit(s) 7:4 3:0 Value Description These bits are reserved and should be written with all zeros. When these four bits match bits [19:16] of the physical address, write-protect that 64K range in 4K increments using WPSxLR and WPSxHR. (Address = 0x0480) (Address = 0x0484) 286 Rabbit 3000 Microprocessor Table B-10. Write Protect Segment x Low Register Write Protect Segment x Low Register (WPSALR) (WPSBLR) Bit(s) 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 1 Enable 4K write-protect for address offset 0x00000x0FFF in WP Segment x Enable 4K write-protect for address offset 0x10000x1FFF in WP Segment x Disable 4K write-protect for address offset 0x00000x0FFF in WP Segment x Enable 4K write-protect for address offset 0x20000x2FFF in WP Segment x Disable 4K write-protect for address offset 0x10000x1FFF in WP Segment x Enable 4K write-protect for address offset 0x30000x3FFF in WP Segment x Disable 4K write-protect for address offset 0x20000x2FFF in WP Segment x Enable 4K write-protect for address offset 0x40000x4FFF in WP Segment x Disable 4K write-protect for address offset 0x30000x3FFF in WP Segment x Enable 4K write-protect for address offset 0x50000x5FFF in WP Segment x Disable 4K write-protect for address offset 0x40000x4FFF in WP Segment x Enable 4K write-protect for address offset 0x60000x6FFF in WP Segment x Disable 4K write-protect for address offset 0x50000x5FFF in WP Segment x Enable 4K write-protect for address offset 0x70000x7FFF in WP Segment x Disable 4K write-protect for address offset 0x60000x6FFF in WP Segment x Value 0 Description Disable 4K write-protect for address offset 0x70000x7FFF in WP Segment x (Address = 0x0481) (Address = 0x0485) Users Manual 287 Table B-11. Write Protect Segment x High Register Write Protect Segment x High Register (WPSAHR) (WPSBHR) Bit(s) 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 1 Enable 4K write-protect for address offset 0x80000x8FFF in WP Segment x Enable 4K write-protect for address offset 0x90000x9FFF in WP Segment x Disable 4Kwrite-protect for address offset 0x80000x8FFF in WP Segment x Enable 4K write-protect for address offset 0xA0000xAFFF in WP Segment x Disable 4K write-protect for address offset 0x90000x9FFF in WP Segment x Enable 4K write-protect for address offset 0xB0000xBFFF in WP Segment x Disable 4K write-protect for address offset 0xA0000xAFFF in WP Segment x Enable 4K write-protect for address offset 0xC0000xCFFF in WP Segment x Disable 4K write-protect for address offset 0xB0000xBFFF in WP Segment x Enable 4K write-protect for address offset 0xD0000xDFFF in WP Segment x Disable 4K write-protect for address offset 0xC0000xCFFF in WP Segment x Enable 4K write-protect for address offset 0xE0000xEFFF in WP Segment x Disable 4K write-protect for address offset 0xD0000xDFFF in WP Segment x Enable 4K write-protect for address offset 0xF0000xFFFF in WP Segment x Disable 4K write-protect for address offset 0xE0000xEFFF in WP Segment x Value 0 Description Disable 4K write-protect for address offset 0xF0000xFFFF in WP Segment x (Address = 0x0482) (Address = 0x0486) 288 Rabbit 3000 Microprocessor B.1.6 Stack Protection Stack overflow and underflow can now be detected. Low and high stack limits can be set on 256-byte boundaries. When a stack-relative memory access occurs within 16 bytes of these limits (or outside of them), a new Priority 3 stack violation interrupt occurs. The 16byte buffer exists to allow stack protection even if the stack is placed against a memory segment boundary. Figure B-2 shows one possible stack layout. A 2048-byte stack is set up by setting STKHLR to 0xE0, STKLLR to 0xD8, and SP to 0xDFF0. Any stack-relative memory accesses above 0xDFEF (i.e., stack underflow) or below 0xD810 (i.e., overflow) would trigger the stack violation interrupt. TKHLR = 0xE0 0xE000 0xDFF0 0xDFEF Stack access in this region triggers an interrupt Stack access in this region is allowed 0xD810 0xD80F 0xD800 TKLLR = 0xD8 Stack access in this region triggers an interrupt Figure B-2. Simple Stack Protection Layout Users Manual 289 The stack protection registers are listed in Table B-12, Table B-13, and Table B-14. Table B-12. Stack Limit Control Register Stack Limit Control Register Bit(s) 7:1 0 0 1 Enable stack-limit checking. Value (STKCR) Description These bits are reserved and should be written with zeros. Disable stack-limit checking. (Address = 0x0444) Table B-13. Stack Low Limit Register Stack Low Limit Register Bit(s) 7:0 Value (STKLLR) Description Lower limit for stack limit checking. If a stack operation or stack-relative memory access is attempted at an address less than {STKLLR, 0x10} a stack limit violation interrupt is generated. (Address = 0x0445) Table B-14. Stack High Limit Register Stack High Limit Register Bit(s) 7:0 Value (STKHLR) Description Upper limit for stack limit checking. If a stack operation or stack-relative memory access is attempted at an address greater than {STKHLR, 0x0EF} a stack limit violation interrupt is generated. (Address = 0x0446) 290 Rabbit 3000 Microprocessor B.1.7 RAM Segment Relocation Normally when instruction/data separation is enabled, instructions are stored in flash memory and data are stored in RAM memory. This can present a problem for the Interrupt Service Routine area, which often requires run-time modification. The RAM Segment Register (RAMSR) allows a 1, 2, or 4 KB segment of the logical memory space to be mapped as data would be mapped, even for program execution. Table B-15. RAM Segment Register RAM Segment Register Bit(s) 7:2 1:0 00 01 10 11 Value (RAMSR) Description Compare value for RAM segment limit checking. Disable RAM segment limit checking. Select data-type MMU translation if PC[15:10] is equal to RAMSR[7:2]. Select data-type MMU translation if PC[15:11] is equal to RAMSR[7:3]. Select data-type MMU translation if PC[15:12] is equal to RAMSR[7:4]. (Address = 0x0448) Users Manual 291 B.1.8 Secondary Watchdog Timer The secondary watchdog timer (SWDT) is an eight-bit modulo n + 1 counter clocked by the 32.768 kHz clock. The timer is off by default, and is enabled by writing a 0x5F to the WDTCR. The secondary watchdog timer register (SWDTR) holds the time constant value. Depending on the value loaded into the SWDTR, the timer can request an interrupt anywhere from 30.5 s to 7.8 ms. If a 0x5F is written to the WDTCR prior to end of the countdown period, the timer will not request an interrupt. If the counter counts down to zero, a level-3 interrupt is generated. The SWDT is intended as a safety net for the periodic interrupt, and would normally be restarted in the service routine for the periodic interrupt. Although the hardware was intended to primarily be used by an operating system when the System/User mode is enabled, it can be used as a configurable periodic interrupt as well. Table B-16. Watchdog Timer Control RegisterUpdated Watchdog Timer Control Register Bit(s) 7:0 Value 0x5A 0x57 0x59 0x53 0x5F other (WDTCR) Description Restart the watchdog timer, with a 2-second time-out period. Restart the watchdog timer, with a 1-second time-out period. Restart the watchdog timer, with a 500 ms time-out period. Restart the watchdog timer, with a 250 ms time-out period. Restart the secondary watchdog timer. No effect on watchdog timer or secondary watchdog timer. Address = 0x0008) Table B-17. Secondary Watchdog Timer Register Secondary Watchdog Timer Register Bit(s) Value (SWDTR) Description The time constant for the secondary watchdog timer is stored. This time constant will take effect the next time that the secondary watchdog counter counts down to zero. The timer counts modulo n + 1, where n is the programmed time constant. The secondary watchdog can be disabled by writing the sequence 0x5A-0x52-0x44 to this register. (Address = 0x000C) 7:0 292 Rabbit 3000 Microprocessor B.1.9 New Opcodes Eight new opcodes were added to the Rabbit 3000A. UMA and UMS allow multiply-andadd and multiply-and-subtract operations on large integers, and were added to speed up common cryptographic math used in public-key calculations. The remaining six expand the block copy operations available, especially to and from I/O addresses (internal and external). These opcodes are listed in Table B-18. Table B-18. New Rabbit 3000 Opcodes Instruction Bytes Clks A I S Z V C Operation UMA 2 8+8i - - - - {CY:DE':(HL) = (IX) + [(IY) * DE + DE' + CY]; * BC = BC-1; IX = IX+1; IY = IY+1; HL = HL+1; repeat while BC !=0 {CY:DE:(HL) = (IX) - [(IY) * DE + DE' + CY]; * BC = BC-1; IX = IX+1; IY = IY+1; HL = HL+1; repeat while BC !=0 (DE) = (HL); BC = BC - 1; HL = HL - 1; repeat while BC != 0 (DE) = (HL); BC = BC - 1; HL = HL + 1; repeat while BC != 0 (DE) = (HL); BC = BC - 1; DE = DE - 1; HL = HL - 1; repeat while BC != 0 (DE) = (HL); BC = BC - 1; DE = DE + 1; HL = HL + 1; repeat while BC != 0 (DE) = (HL); BC = BC - 1; DE = DE - 1; repeat while BC != 0 (DE) = (HL); BC = BC - 1; DE = DE + 1; repeat while BC != 0 UMS 2 8+8i - - - - LDDSR LDISR LSDR LSIR LSDDR LSIDR 2 2 2 2 2 2 6+7i 6+7i 6+7i 6+7i 6+7i 6+7i d d s s s s - - * * * * * * B.1.9.1 New UMA/UMS Opcodes The new UMA and UMS opcodes perform the following operation: {CY:DE':(HL)} = (IX) [(IY) * DE + DE' + CY]; where HL, IX, and IY increment after each byte, repeated BC times. This fundamental operation allows the addition or subtraction of two arbitrarily-long unsigned integers after one is scaled by a single-byte value. This operation is common in many cryptographic operations. Users Manual 293 B.1.9.2 New Block Copy Opcodes The LDxR family of block move opcodes has been expanded. In the Rabbit 3000 processor, block copy operations could only be done between memory addresses, or from memory to an I/O address. In addition, the destination I/O address would increment (or decrement if using LDDR) after each byte, making the block copy opcodes effectively useless for repeated reads or writes to a peripheral (for example, a device on the external I/P bus). Six new block copy opcodes were added to the Rabbit 3000 revision. These opcodes can copy from an I/O address as well as to one, and either the source or destination address can remain fixed instead of changing after each byte. The new opcodes are described in Table B-19. Table B-19. Rabbit 3000 Revision Block Copy Opcode Effects Opcode Source Address Change + + + none none Destination Address Change + none none + + IOI/IOE Affects destination destination destination destination source source source source LDDR LDIR LDDSR LDISR LSDR LSIR LSDDR LSIDR 294 Rabbit 3000 Microprocessor B.1.10 Expanded I/O Memory Addressing In the Rabbit 3000, only the lower 8 bits of an I/O address were decoded. To provide room for new peripherals, this was expanded to 16 bits. To ensure backwards compatibility, the processor always comes up in 8-bit I/O address mode; the 16-bit I/O address mode needs to be enabled in the MMIDR register by setting bit 7 to 1. The updated MMIDR register is listed in Table B-20. NOTE: Bits 7 was always written with a zero in the original Rabbit 3000 chip. Table B-20. MMU Instruction/Data Register MMU Instruction/Data Register Bit(s) Value 0 7 1 6 0 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 1 For root access, invert A16 For root access, invert A19 before MBxCR (bank select) decision. Normal operation. For a DATASEG access: invert A16 Normal operation. For a DATASEG access, invert A19 before MBxCR (bank select) decision. Normal operation. (MMIDR) Description 8-bit internal I/O addresses (address range 0x00000x00FF). 15-bit internal I/O addresses (address range 0x00000x7FFF, required to access internal I/O addresses of 0x0100 and higher). This bit is ignored and will always return zero when read. Enable A16 and A19 inversion independent of instruction/data. Enable A16 and A19 inversion (controlled by bits 0-3) for data accesses only. This enables the instruction/data split for the separate I and D space. Normal /CS1 operation. Force /CS1 always active. This will not cause any conflicts as long as the memory using /CS1 does not also share an Output Enable or Write Enable with another memory. Normal operation. (Address = 0x010) Users Manual 295 B.1.11 External I/O Improvements Three new features have been added to the external I/O strobes: the ability to invert the strobe signal, the ability to shorten a read strobe by one clock, and the ability to direct a strobe to either the alternate I/O bus (if enabled) or the memory bus. The new control bits for the external I/O strobes are listed in Table B-21. NOTE: Bits [1:0] were always written with zero in the original Rabbit 3000 chip. Table B-21. I/O Bank x Control Register I/O Bank x Control Register (IB0CR) (IB1CR) (IB2CR) (IB3CR) (IB4CR) (IB5CR) (IB6CR) (IB7CR) Description Fifteen wait states for accesses in this bank. Seven wait states for accesses in this bank. Three wait states for accesses in this bank. One wait state for accesses in this bank. The Ix signal is an I/O chip select. The Ix signal is an I/O read strobe. The Ix signal is an I/O write strobe. The Ix signal is an I/O data (read or write) strobe. Writes are not allowed to this bank. Transactions are normal in every other way; only the write strobe is inhibited. Writes are allowed to this bank. Active-Low Ix signal. Inverted (active-High) Ix. Normal I/O Transaction timing. Shorten read strobe by one clock cycle. Transaction length remains the same. Use I/O bus if enabled. Always use memory data bus. (Address = 0x0080) (Address = 0x0081) (Address = 0x0082) (Address = 0x0083) (Address = 0x0084) (Address = 0x0085) (Address = 0x0086) (Address = 0x0087) Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 0 3 1 0 2 1 0 1 1 0 0 1 296 Rabbit 3000 Microprocessor B.1.12 Short Chip Select Timing for Writes The Rabbit 3000 provided the ability to produce shorter chip select strobes for reads when in a reduced-speed mode. A new feature has been added to produce short chip select strobes for writes as well, and can be controlled by the GPCSR register. The new control bit for the short chip selects are listed in Table B-22. NOTE: Bit 3 was always written with zero in the original Rabbit 3000 chip. Table B-22. Global Power Save Control Register Global Power Save Control Register Bit(s) 7:5 Value 000 001 010 011 100 101 110 111 0 4 1 0 3 1 2:0 000 001 010 011 100 101 110 111 Short Chip Select timing for write cycles (not available in full speed). The 32 kHz clock divider is disabled. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. 32 kHz oscillator divided by two (16.384 kHz). 32 kHz oscillator divided by four (8.192 kHz). 32 kHz oscillator divided by eight (4.096 kHz). 32 kHz oscillator divided by sixteen (2.048 kHz). Short Chip Select timing for read cycles (not available in full speed). Normal Chip Select timing for write cycles (GPSCR) Description Self-timed chip selects are disabled. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. 296 ns self-timed chip selects (192 ns best case, 457 ns worst case). 234 ns self-timed chip selects (151 ns best case, 360 ns worst case). 171 ns self-timed chip selects (111 ns best case, 264 ns worst case). 109 ns self-timed chip selects (71 ns best case, 168 ns worst case). Normal Chip Select timing for read cycles. (Address = 0x000D) Users Manual 297 B.1.12.1 Clock Select and Power Save Modes Table B-24 outlines the power save modes available in the Rabbit 3000A. The GCSR is shown in Table B-23 for reference. Table B-23. Global Control/Status Register Global Control/Status Register Bit(s) Value 00 7:6 (rd-only) 01 10 11 0 5 1 4:2 xxx 00 01 1:0 10 11 Periodic interrupts use Interrupt Priority 2. Periodic interrupts use Interrupt Priority 3. Force a periodic interrupt to be pending. See table below for decode of this field. Periodic interrupts are disabled. Periodic interrupts use Interrupt Priority 1. (GCSR) Description No reset or watchdog timer time-out since the last read. The watchdog timer timed out. These bits are cleared by a read of this register. This bit combination is not possible. Reset occurred. These bits are cleared by a read of this register. No effect on the periodic interrupt. This bit will always be read as zero. (Address = 0x00) Table B-24. Clock Select Field of GCSR Clock Select Bits 4:2 GCSR 000 001 010 011 100 CPU Clock osc/8 osc/8 osc osc/2 32 kHz or fraction Peripheral Clock osc/8 osc osc osc/2 32 kHz or fraction Main Oscillator on on on on on Power-Save CS if Enabled by GPSCR short CS option short CS option none short CS option self-timed option short CS option self-timed option short CS option short CS option short CS option 101 110 111 32 kHz or fraction osc/4 osc/6 32KHz or fraction osc/4 osc/6 off on on 298 Rabbit 3000 Microprocessor B.1.12.2 Short Chip Select Timing When short chip selects are enabled for read cycles, the chip select signals are active only for the last part of the bus cycle. Wait states are inserted between T1 and T2, so this will have no effect on the duration of the chip select signals in this mode. The timing diagrams below illustrate the actual timing for the different divided cases. In these cases the chip selects are two clock cycles (of the fast oscillator) long. T1 T2 oscillator clock ADDR Valid DATA /CSx /OEx divide -by-8 mode Figure B-3. Short Chip Select Timing: CLK/8, Read Operation Users Manual 299 T1 T2 o s c illa t o r c lo c k ADD R Valid DAT A /C S x /O E x d iv i de - by - 6 m o de Figure B-4. Short Chip Select Timing: CLK/6, Read Operation T1 T2 oscillator clock ADDR Valid DATA /CSx /OEx divide-by-4 mode Figure B-5. Short Chip Select Timing: CLK/4, Read Operation 300 Rabbit 3000 Microprocessor T1 T2 oscillato r clock ADD R Valid DATA /CSx /OEx divide -by-2 mo de Figure B-6. Short Chip Select Timing: CLK/2, Read Operation Users Manual 301 When operating from the 32 kHz oscillator, the same options are available, but the timing is somewhat different. This is illustrated in the diagrams below for the four different cases. In these case the chip selects are one clock cycle (of the 32 kHz clock) long. T1 T2 32KHz 32 kHz clock ADDR Valid DATA MEMCSxB /CSx MEMOExB /OEx 2KHz operation 2 kHz Figure B-7. Short Chip Select Timing: 2 kHz, Read Operation T1 T2 32 kHz clock ADDR Valid DATA /CSx /OEx 4 kHz operation Figure B-8. Short Chip Select Timing: 4 kHz, Read Operation 302 Rabbit 3000 Microprocessor T1 T2 32 kHz clock ADD R Valid DAT A /CSx /O Ex 8 kHz ope ratio n Figure B-9. Short Chip Select Timing: 8 kHz, Read Operation T1 T2 32 kHz clock ADD R Valid DATA /CSx /OEx 16 kHz operatio n Figure B-10. Short Chip Select Timing: 16 kHz, Read Operation Users Manual 303 T1 T2 32 kHz clock ADD R Valid DATA /CSx /OEx 32 kHz operatio n Figure B-11. Short Chip Select Timing: 32 kHz, Read Operation 304 Rabbit 3000 Microprocessor In the case of write cycles, the chip select signals are active only around the trailing edge of the write signal. Wait states are inserted between T1 and T2, and this will have no effect on the duration of the chip select signals in this mode. The timing diagrams below illustrate the actual timing for the different divided cases. In these cases the chip selects are active for two clock cycles before and two clock cycles after the trailing edge of the write signal. T1 TW A T2 oscillator clock ADDR V alid DATA /CSx /W Ex divide-by-8 m ode Figure B-12. Short Chip Select Timing: CLK/8, Write Operation Users Manual 305 T1 TWA T2 oscillator clock ADDR Valid DATA /CSx /WEx divide-by-6 mode Figure B-13. Short Chip Select Timing: CLK/6, Write Operation T1 TW A T2 o s c illa t o r c lo c k ADD R V a li d DATA /C S x /W E x d iv ide - by - 4 m o de Figure B-14. Short Chip Select Timing: CLK/4, Write Operation 306 Rabbit 3000 Microprocessor T1 TWA T2 oscillator clock ADDR Valid DATA /CSx /WEx divide-by-2 mode Figure B-15. Short Chip Select Timing: CLK/2, Write Operation Users Manual 307 The timing diagrams below illustrate the actual timing for the 32KHz cases of write cycles. In these cases the chip selects are active for one clock cycle before and one clock cycle after the trailing edge of the write signal. T1 TWA T2 32 kHz 32KHz clock ADDR Valid DATA MEMCSxB /CSx MEMWExB /WEx 2 kHz operation 2KHz operation Figure B-16. Short Chip Select Timing: 2 kHz, Write Operation T1 TW A T2 32 kHz clock ADDR V alid DATA /CSx /W Ex 4 kHz operation Figure B-17. Short Chip Select Timing: 4 kHz, Write Operation 308 Rabbit 3000 Microprocessor T1 TWA T2 32 kHz clock ADDR Valid DATA /CSx /WEx 8 kHz operation Figure B-18. Short Chip Select Timing: 8 kHz, Write Operation T1 TWA T2 32 kHz clock ADDR Valid DATA /CSx /WEx 16 kHz operation Figure B-19. Short Chip Select Timing: 16 kHz, Write Operation Users Manual 309 T1 TWA T2 32 kHz clock ADDR Valid DATA /CSx /WEx 32 kHz operation Figure B-20. Short Chip Select Timing: 32 kHz, Write Operation 310 Rabbit 3000 Microprocessor B.1.13 Pulse Width Modulator Improvements Several new features have been added to the pulse width modulator. First, a new PWM interrupt can be set up to be requested on every PWM cycle, every other cycle, every fourth cycle, or every eighth cycle. The setup for this interrupt is done in the PWL0R and PWL1R registers, listed in Table B-25 and Table B-26. Options are available to suppress the PWM output for seven-of-eight, three-of-four and one-of-two iterations of the PWM counter The one-of-eight option works nicely with R/C servos, which require a 1 ms to 2 ms pulse width and a 20 ms period. This option gives the full resolution for the pulse width while still meeting the period requirements. The one-offour and one-of-two options can be used to create more virtual PWM channels using software to multiplex the PWM outputs. There is a separate option to only generate an interrupt during the active iteration of the PWM count. The timing is shown below. iteration 0 1 2 3 4 5 6 7 1/8 output 1/4 output 1/2 output 1/8 interrupt 1/4 interrupt 1/2 interrupt Figure B-21. PWM Interrupt and Output Timing Users Manual 311 Table B-25. PWM LSB 0 Register PWM LSB 0 Register Bit(s) 7:6 5:4 Value write 00 01 10 11 3 2:1 00 01 10 11 0 0 1 Spread PWM output throughout the cycle. (PWL0R) Description The least significant two bits for the Pulse Width Modulator count are stored. Normal PWM operation. Suppress PWM output seven out of eight iterations of PWM counter. Suppress PWM output three out of four iterations of PWM counter. Suppress PWM output one out of two iterations of PWM counter. This bit is ignored and should be written with zero. Pulse Width Modulator interrupts are disabled. Pulse Width Modulator interrupts use Interrupt Priority 1. Pulse Width Modulator interrupts use Interrupt Priority 2. Pulse Width Modulator interrupts use Interrupt Priority 3. PWM output High for single block. (Address = 0x0088) Table B-26. PWM LSB 1 Register PWM LSB 1 Register Bit(s) 7:6 5:4 Value write 00 01 10 11 3 2:1 00 01 10 11 0 0 1 Spread PWM output throughout the cycle. (PWL1R) Description The least significant two bits for the Pulse Width Modulator count are stored. Normal PWM operation. Suppress PWM output seven out of eight iterations of PWM counter. Suppress PWM output three out of four iterations of PWM counter. Suppress PWM output one out of two iterations of PWM counter. This bit is ignored and should be written with zero. Normal PWM interrupt operation. Suppress PWM interrupts seven out of eight iterations of PWM counter. Suppress PWM interrupts three out of four iterations of PWM counter. Suppress PWM interrupts one out of two iterations of PWM counter. PWM output High for single block. (Address = 0x008A) 312 Rabbit 3000 Microprocessor Table B-27. PWM LSB 2 and 3 Registers PWM LSB x Register (PWL2R) (PWL3R) Bit(s) 7:6 5:4 Value write 00 01 10 11 3:1 0 0 1 Spread PWM output throughout the cycle. Description The least significant two bits for the Pulse Width Modulator count are stored. Normal PWM operation. Suppress PWM output seven out of eight iterations of PWM counter. Suppress PWM output three out of four iterations of PWM counter. Suppress PWM output one out of two iterations of PWM counter. These bits are ignored and should be written with zero. PWM output High for single block. (Address = 0x008C) (Address = 0x008E) Users Manual 313 B.1.14 Quadrature Decoder Improvements The quadrature decoder counters can now be expanded to 10 bits instead of 8 bits. This is controlled by bit 5 in QDCR, listed in Table B-28. The additional two bits can be read in the QDCxHR registers, listed in Table B-29. NOTE: Bit 5 of QDCR was always written with a zero in the original Rabbit 3000 chip. Table B-28. Quadrature Decoder Control Register Quadrature Decoder Control Register Bit(s) 7:6 Value 00 01 10 11 5 0 1 4 3:2 00 01 10 11 1:0 00 01 10 11 (QDCR) Description Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. This bit combination is reserved and should not be used. Quadrature Decoder 2 inputs from Port F bits 3 and 2. Quadrature Decoder 2 inputs from Port F bits 7 and 6. Eight bit quadrature decoder counters. Ten bit quadrature decoder counters. This bit is reserved and should be written as zero. Disable Quadrature Decoder 1 inputs. Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement. This bit combination is reserved and should not be used. Quadrature Decoder 1 inputs from Port F bits 1 and 0. Quadrature Decoder 1 inputs from Port F bits 5 and 4. Quadrature Decoder interrupts are disabled. Quadrature Decoder interrupt use Interrupt Priority 1. Quadrature Decoder interrupt use Interrupt Priority 2. Quadrature Decoder interrupt use Interrupt Priority 3. (Address = 0x0091) Table B-29. Quadrature Decoder Count High Register Quadrature Decoder Count High Register (QDC1HR) (QDC2HR) Bit(s) 7:2 1:0 Value read read Description These bits are reserved and will always read as zeros. The current value of bits 9-8 of the Quadrature Decoder counter is reported. (Address = 0x0095) (Address = 0x0097) 314 Rabbit 3000 Microprocessor I input Q input Cnt (8 bit) FF 00 01 02 03 04 05 06 07 08 07 06 05 04 03 02 01 00 FF Cnt (10 bit) 3FF 000 001 002 003 004 005 006 007 008 007 006 005 004 003 002 001 000 3FF Interrupt Figure B-22. Quadrature Decode, 8-bit and 10-bit Counter Timing Users Manual 315 B.2 Pins with Alternate Functions The Rabbit 3000A provides greater flexibility for multiplexing I/O functions to other pins. The following alternate connections were introduced in the Rabbit 3000A for these peripherals, and are indicated by an asterisk in Table 5-2. Slave port CS /ASCS: Alternate slave port chip select input Serial Ports E/F ARXE: Alternate Serial Port E receive ARCLKE: Alternate Serial Port E receive clock (HDLC) ARXF: Alternate Serial Port F receive ARCLKF: Alternate Serial Port F receive clock (HDLC) PWM outputs APWM3: Alternate PWM output, bit 3 APWM2: Alternate PWM output, bit 2 APWM1: Alternate PWM output, bit 1 APWM0: Alternate PWM output, bit 0 316 Rabbit 3000 Microprocessor APPENDIX C. SYSTEM/USER MODE The Rabbit 3000A is the first Rabbit microprocessor to incorporate a system/user mode. The purpose of the System/User mode is to provide two tiers of control in the CPU: system, which provides full access to all processor resources; and user, a more restricted mode. Table C-1 describes the essential differences between the System mode and the User mode. The System mode is essentially the same as the normal operation of the Rabbit 3000 and earlier processors. Table C-1. Differences Between System and User Modes System Mode All peripherals accessible. All processor control registers available. All interrupt priorities available. IDET opcode has no effect. No write protection when 0x00 is written to WPCR (write protection in User mode only) Easy to enter user mode (SETUSR opcode). User Mode No peripherals accessible by default. No processor control registers available. Interrupt Priority 3 not allowed. IDET opcode causes Priority 3 system mode violation interrupt. Write to protected segment causes Priority 3 write protection violation interrupt. Difficult to enter system mode (requires interrupt, SYSCALL, or RST opcode). The main intent of the System/User mode is to protect critical code (for example, code that performs remote firmware updates), data, and the current processor state (memory setup, peripheral control, etc.) from inadvertent changes by the users standard code. By removing access to the processors I/O registers and preventing memory writes to critical regions, the users code can run without the danger of locking up the processor to the point where it cannot be restarted remotely and/or new code uploaded. Users Manual 317 C.1 System/User Mode Opcodes Seven new opcodes have been added to support the System/User mode, and are listed in Table C-2. All but IDET are placed in previously empty opcode table assignments. IDET shares the value of LD E,E in the opcode table, and will perform that operation when the System/User mode is disabled, or when it is enabled and in the System mode. In addition, if the ALTD prefix appears before the opcode, LD E,E is always executed instead. The processor keeps a one-byte stack (called the SU register) that is analogous to the IP register that keeps track of the interrupt priority. Every time SETUSR is executed (to enter the User mode), or an interrupt occurs, or SYSCALL or RST is executed (to enter the System mode), the current mode is pushed onto the SU register. When a SURES is executed, the previous mode is popped off the SU register. The effects of each opcode are: The SETUSR opcode puts the processor into the User mode by pushing the correct value into the SU register. PUSH SU and POP SU push and pop the single-byte SU register on/off the SP stack. SURES pops the current processor mode off the SU register, returning it to the previous mode. IDET causes an interrupt if executed in the User mode, and does nothing in the System mode. RDMODE returns the current mode in the carry flag (0 for System mode, 1 for User mode). SYSCALL is essentially a new RST opcode, and was added to allow User mode access to the System mode without using one of the existing RST opcodes. It will put the processor into the System mode and execute code in the corresponding interrupt-vector table entry. Table C-2. New System/User Mode Opcodes Instruction Bytes 2 2 2 2 clk 4 9 7 4 A I S Z V C Operation Priv ? Yes Yes Yes Yes SETUSR PUSH SU POP SU SURES - SU = {SU[5:0], 0x01} - (SP-1) = SU; SP = SP - 1 - SU = (SP); SP = SP + 1 - SU = {SU[1:0], SU[7:2]} Performs LD E,E, but if (EDMF && SU[0]) then the System Violation interrupt flag is set; if ALTD appears before it always does LD E,E * CF = SU[0] SP = SP - 2; PC = {R,v} where v = SYSCALL offset IDET 1 2 - - - - No RDMODE SYSCALL 318 2 2 4 10 - - - - Yes No Rabbit 3000 Microprocessor C.2 System/User Mode Registers Table C-3 lists the new I/O registers added to support the System/User mode. The Enable Dual Mode Register (EDMR) is used to enable and disable the System/User mode. All other I/O registers listed in the table are User mode enable registers for each peripheral. On startup, User mode access is not allowed to all the peripherals (all writes to I/O registers for that peripheral are ignored), but can be enabled by writing to the appropriate register. Note that User mode writes to all other I/O registers are always ignored. Table C-3. System/User Mode I/O Registers Register Name Enable Dual-Mode Register Real Time Clock User Enable Register Slave Port User Enable Register Parallel Port A User Enable Register Parallel Port B User Enable Register Parallel Port C User Enable Register Parallel Port D User Enable Register Parallel Port E User Enable Register Parallel Port F User Enable Register Parallel Port G User Enable Register Input Capture User Enable Register I/O Bank User Enable Register PWM User Enable Register Quad Decode User Enable Register External Interrupt User Enable Register Timer A User Enable Register Timer B User Enable Register Serial Port A User Enable Register Serial Port B User Enable Register Serial Port C User Enable Register Serial Port D User Enable Register Serial Port E User Enable Register Serial Port F User Enable Register Mnemonic EDMR RTUER SPUER PAUER PBUER PCUER PDUER PEUER PFUER PGUER ICUER IBUER PWUER QDUER IUER TAUER TBUER SAUER SBUER SCUER SDUER SEUER SFUER I/O R/W Address 0x0420 0x0300 0x0320 0x0330 0x0340 0x0350 0x0360 0x0370 0x0338 0x0348 0x0358 0x0380 0x0388 0x0390 0x0398 0x03A0 0x03B0 0x03C0 0x3D0 0x3E0 0x3F0 0x03C8 0x3D8 W W W W W W W W W W W W W W W W W W W W W W W Reset 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Users Manual 319 The I/O banks on Port E (enabled for the User mode by IBUER) have a slightly different operation in the User mode. Disabling user access to a given I/O bank not only causes writes to the corresponding IBxCR register to be ignored in the User mode, but also inhibits the strobe associated with that I/O bank. Access to the internal I/O registers listed in Table C-4 is always denied in the User mode. Table C-4. I/O Addresses Inaccessible in User Mode Register Name Global Control/Status Register Watchdog Timer Control Register Watchdog Timer Test Register Global Clock Modulator 0 Register Global Clock Modulator 1 Register Secondary Watchdog Timer Register* Global Power Save Control Register Global Output Control Register Global Clock Double Register MMU Instruction/Data Register Stack Segment Register Data Segment Register Segment Size Register Memory Bank 0 Control Register Memory Bank 1 Control Register Memory Bank 2 Control Register Memory Bank 3 Control Register MMU Expanded Code Register Memory Timing Control Register Breakpoint/Debug Control Register User Enable registers* Memory Protection registers* * These registers are only available on the Rabbit 3000A. Mnemonic GCSR WDTCR WDTTR GCM0R GCM1R SWDTR GPSCR GOCR GCDR MMIDR STACKSEG DATASEG SEGSIZE MB0CR MB1CR MB2CR MB3CR MECR MTCR BDCR I/O Address 0x0000 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001C 0x03xx 0x04xx 320 Rabbit 3000 Microprocessor C.3 Interrupts When enabled for User mode access, a peripheral interrupt (if it is capable of generating an interrupt) can only be requested at Interrupt Priority Level -2 or -1. Interrupts (and RSTs and SYSCALL) all enter the System mode automatically. There will be times, however, that an interrupt should be handled in the User mode. The solution to this is for the System mode interrupt vector to reenter User mode before calling the User mode interrupt handler. An example of both system and user interrupt handling is shown in Figure C-1. INTERRUPT UNDER SYSTEM CONTROL ISR (system) Application code (user) Application code (user) INTERRUPT UNDER USER CONTROL ISR (system) Application ISR (user) Application code (user) Application code (user) Figure C-1. Interrupt Handing in System/User Mode Some sample code for both System mode interrupts and User mode interrupts is shown below. system_isr: ... handle interrupt ... sures ret user_isr: push su setusr ... handle interrupt ... pop su sures ret ; jumped to from interrupt vector table ; reenter previous mode ; jumped to from interrupt vector table ; preserve current SU stack ; enter user mode ; restore previous SU stack ; reenter previous mode Users Manual 321 C.3.1 Peripheral Interrupt Prioritization Most interrupts can be programmed to occur at any of three priority levels, but several are restricted to Level 3 (the highest priority) only. The interrupts restricted to Level 3 are system mode violation, stack limit violation, write protection violation, and the secondary watchdog. In addition, any interrupt assigned to User mode is prevented (by hardware) from requesting a Level 3 interrupt. If a user-assigned interrupt is programmed to occur at Level 3, the hardware will automatically modify the request to occur at Level 2. Within a given interrupt priority level, the interrupts are prioritized according to Table C-5. 322 Rabbit 3000 Microprocessor Table C-5. InterruptsPriority and Action to Clear Requests Priority Highest Interrupt Source System Mode Violation Stack Limit Violation Write Protection Violation Secondary Watchdog External 1 External 0 Periodic (2 kHz) Quadrature Decoder Timer B Timer A Input Capture PWM Slave Port Action required to clear the interrupt Automatically cleared by the interrupt acknowledge. Automatically cleared by the interrupt acknowledge. Automatically cleared by the interrupt acknowledge. Restart the Secondary Watchdog by writing to WDTCR. Automatically cleared by the interrupt acknowledge. Automatically cleared by the interrupt acknowledge. Read the status from the GCSR. Read the status from the QDSR. Read the status from the TBSR. Read the status from the TASR. Read the status from the ICCSR. Write any PWM register. Rd: Read the data from the SPD0R, SPD1R or SPD2R. Wr: Write data to the SPD0R, SPD1R, SPD2R or write a dummy byte to the SPSR. Rx: Read the data from the SEDR or SEAR. Tx: Write data to the SEDR, SEAR, SELR or write a dummy byte to the SESR. Rx: Read the data from the SFDR or SFAR. Tx: Write data to the SFDR, SFAR, SFLR or write a dummy byte to the SFSR. Rx: Read the data from the SADR or SAAR. Tx: Write data to the SADR, SAAR, SALR or write a dummy byte to the SASR. Rx: Read the data from the SBDR or SBAR. Tx: Write data to the SBDR, SBAR, SBLR or write a dummy byte to the SBSR. Rx: Read the data from the SCDR or SCAR. Tx: Write data to the SCDR, SCAR, SCLR or write a dummy byte to the SCSR. Rx: Read the data from the SDDR or SDAR. Tx: Write data to the SDDR, SDAR, SDLR or write a dummy byte to the SDSR. Serial Port E Serial Port F Serial Port A Serial Port B Serial Port C Lowest Serial Port D Users Manual 323 C.4 Using the System/User Mode The System/User mode is designed to work with new features in the Rabbit 3000A (memory protection, stack protection, etc.) to provide a seamless framework for protection of critical code. However, there are many levels at which the System/User mode can be used; some examples are described here. C.4.1 Memory Protection Only At the beginning of the user program, all necessary peripherals are enabled, all peripheral interrupts to be used are set up for the User mode, critical memory regions are protected, stack limits are set, and the various system/memory/stack violation interrupts are enabled. The processor then enters the User mode and remains in the User mode for all operations (interrupts can be handled however the user desires). Obviously the critical interrupts can be handled in the System mode, but at that point the device is typically reset and the error is logged. An overview of this level of operation is shown in Figure C-2. System Mode User Mode Application code Critical Interrupts Critical interrupts Interrupts Figure C-2. System/User Mode Setup for Memory Protection Only 324 Rabbit 3000 Microprocessor C.4.2 Mixed System/User Mode Operation This mode is similar to the previous mode, but with some portions of the program written for the System modefor example, peripheral interrupts where latency is critical. By keeping the System mode code sections small, potential system crashes are still minimized. An overview of this level of operation is shown in Figure C-3. System Mode Return from interrupts User Mode Application code User-defined interrupts Critical interrupts Time-critical interrupts Critical Interrupts Figure C-3. System/User Mode Setup for Mixed Operation Users Manual 325 C.4.3 Complete Operating System This section describes a full use of the System/User modeseparating all common functions into a System mode operating system while letting the application-specific code run in the User mode.By default, the System mode handles all peripherals and interrupts, as well as high-level interfaces such as a flash file system. However, the processor will be running the application code in the User mode most of the time. The application code can request direct access to a peripheral and/or interrupt from the System mode. If allowed, the System mode can create an interrupt vector as described in Section C.3 that will execute the user code interrupt handler. When the application code wants to perform an action that is controlled by the System mode, it can request the particular action by loading the appropriate value into HL and executing SYSCALL. This requires generating a list of all the actions that the application code would want to do, assigning values to each action, and implementing a SYSCALL handler in the System mode that parses the value passed to it and calls the appropriate function. Write protection should be enabled (User mode only) for all blocks containing system code and data as well as any critical memory regions. If any critical interrupts occur (stack limit violation, system mode violation, write protection violation), the System mode handlers can perform any of a number of operations: restart the application code, signal another device, halt operation, and so on. An overview of this level of operation is shown in Figure C-4. System Mode Return from interrupts User Mode Application code User-defined interrupts Interrupt handlers Flash file system SYSCALL handler Interrupts, SYSCALL, RST Figure C-4. System/User Mode Setup for Operating System 326 Rabbit 3000 Microprocessor APPENDIX D. RABBIT 3000A INTERNAL I/O REGISTERS Table D-1 provides a list of all the Rabbit 3000A internal I/O registers. Table D-1. Rabbit 3000A Internal I/O Registers Register Name Global Control/Status Register Real Time Clock Control Register Real Time Clock Byte 0 Register Real Time Clock Byte 1 Register Real Time Clock Byte 2 Register Real Time Clock Byte 3 Register Real Time Clock Byte 4 Register Real Time Clock Byte 5 Register Watchdog Timer Control Register Watchdog Timer Test Register Global Clock Modulator 0 Register Global Clock Modulator 1 Register Secondary Watchdog Timer Register Global Power Save Control Register Global Output Control Register Global Clock Double Register Global ROM Configuration Register Global RAM Configuration Register Global CPU Configuration Register Global Revision Register MMU Instruction/Data Register Mnemonic GCSR RTCCR RTC0R RTC1R RTC2R RTC3R RTC4R RTC5R WDTCR WDTTR GCM0R GCM1R SWDTR GPSCR GOCR GCDR GROM GRAM GCPU GREV MMIDR I/O Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x002C 0x002D 0x002E 0x002F 0x0010 R/W R/W W R/W R R R R R W W W W W W W W R R R R R/W Reset 11000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 00000000 00000000 00000000 11111111 00000000 00000000 00000000 0xx00000 0xx00000 0xx00001 0xx00001 00000000 Users Manual 327 Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name Memory Bank 0 Control Register Memory Bank 1 Control Register Memory Bank 2 Control Register Memory Bank 3 Control Register MMU Expanded Code Register Memory Timing Control Register Breakpoint/Debug Control Register RAM Segment Register Write Protect Control Register Stack Limit Control Register Stack Low Limit Register Stack High Limit Register Write Protect Low Register Write Protect High Register Write Protect Segment A Register Write Protect Segment A Low Register Write Protect Segment A High Register Write Protect Segment B Register Write Protect Segment B Low Register Write Protect Segment B High Register Real Time Clock User Enable Register Slave Port User Enable Register Parallel Port A User Enable Register Parallel Port F User Enable Register Parallel Port B User Enable Register Parallel Port G User Enable Register Parallel Port C User Enable Register Input Capture User Enable Register Parallel Port D User Enable Register Parallel Port E User Enable Register Mnemonic MB0CR MB1CR MB2CR MB3CR MECR MTCR BDCR RAMSR WPCR STKCR STKLLR STKHLR WPLR WPHR WPSAR WPSALR WPSAHR WPSBR WPSBLR WPSBHR RTUER SPUER PAUER PFUER PBUER PGUER PCUER ICUER PDUER PEUER I/O Address 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001C 0x0448 0x0440 0x0444 0x0445 0x0446 0x0460 0x0461 0x0480 0x0481 0x0482 0x0484 0x0485 0x0486 0x0300 0x0320 0x0330 0x0338 0x0340 0x0348 0x0350 0x0358 0x0360 0x0370 R/W W W W W R/W W W W W W W W W W W W W W W W W W W W W W W W W W Reset 00001000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 00000000 00000000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 328 Rabbit 3000 Microprocessor Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name I/O Bank User Enable Register PWM User Enable Register Quad Decode User Enable Register External Interrupt User Enable Register Timer A User Enable Register Timer B User Enable Register Serial Port A User Enable Register Serial Port E User Enable Register Serial Port B User Enable Register Serial Port F User Enable Register Serial Port C User Enable Register Serial Port D User Enable Register Enable Dual Mode Register Slave Port Data 0 Register Slave Port Data 1 Register Slave Port Data 2 Register Slave Port Status Register Slave Port Control Register Port A Data Register Port B Data Register Port B Data Direction Register Port C Data Register Port C Function Register Port D Data Register Port D Control Register Port D Function Register Port D Drive Control Register Port D Data Direction Register Port D Bit 0 Register Port D Bit 1 Register Mnemonic IBUER PWUER QDUER IUER TAUER TBUER SAUER SEUER SBUER SFUER SCUER SDUER EDMR SPD0R SPD1R SPD2R SPSR SPCR PADR PBDR PBDDR PCDR PCFR PDDR PDCR PDFR PDDCR PDDDR PDB0R PDB1R I/O Address 0x0380 0x0388 0x0390 0x0398 0x03A0 0x03B0 0x03C0 0x03C8 0x03D0 0x03D8 0x03E0 0x03F0 0x0420 0x0020 0x0021 0x0022 0x0023 0x0024 0x0030 0x0040 0x0047 0x0050 0x0055 0x0060 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 R/W W W W W W W W W W W W W W R/W R/W R/W R R/W R/W R/W W R/W W R/W W W W W W W Reset 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 0xx00000 xxxxxxxx 00xxxxxx 11000000 x0x1x1x1 x0x0x0x0 xxxxxxxx xx00xx00 xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx Users Manual 329 Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name Port D Bit 2 Register Port D Bit 3 Register Port D Bit 4 Register Port D Bit 5 Register Port D Bit 6 Register Port D Bit 7 Register Port E Data Register Port E Control Register Port E Function Register Port E Data Direction Register Port E Bit 0 Register Port E Bit 1 Register Port E Bit 2 Register Port E Bit 3 Register Port E Bit 4 Register Port E Bit 5 Register Port E Bit 6 Register Port E Bit 7 Register Port F Data Register Port F Control Register Port F Function Register Port F Drive Control Register Port F Data Direction Register Port G Data Register Port G Control Register Port G Function Register Port G Drive Control Register Port G Data Direction Register I/O Bank 0 Control Register I/O Bank 1 Control Register Mnemonic PDB2R PDB3R PDB4R PDB5R PDB6R PDB7R PEDR PECR PEFR PEDDR PEB0R PEB1R PEB2R PEB3R PEB4R PEB5R PEB6R PEB7R PFDR PFCR PFFR PFDCR PFDDR PGDR PGCR PGFR PGDCR PGDDR IB0CR IB1CR I/O Address 0x006A 0x006B 0x006C 0x006D 0x006E 0x006F 0x0070 0x0074 0x0075 0x0077 0x0078 0x0079 0x007A 0x007B 0x007C 0x007D 0x007E 0x007F 0x0038 0x003C 0x003D 0x003E 0x003F 0x0048 0x004C 0x004D 0x004E 0x004F 0x0080 0x0081 R/W W W W W W W R/W W W W W W W W W W W W R/W W W W W R/W W W W W W W Reset xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx00xx00 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx00xx00 xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xx00xx00 xxxxxxxx xxxxxxxx 00000000 00000000 00000000 330 Rabbit 3000 Microprocessor Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name I/O Bank 2 Control Register I/O Bank 3 Control Register I/O Bank 4 Control Register I/O Bank 5 Control Register I/O Bank 6 Control Register I/O Bank 7 Control Register PWM LSB 0 Register PWM MSB 0 Register PWM LSB 1 Register PWM MSB 1 Register PWM LSB 2 Register PWM MSB 2 Register PWM LSB 3 Register PWM MSB 3 Register Input Capture Ctrl/Status Register Input Capture Control Register Input Capture Trigger 1 Register Input Capture Source 1 Register Input Capture LSB 1 Register Input Capture MSB 1 Register Input Capture Trigger 2 Register Input Capture Source 2 Register Input Capture LSB 2 Register Input Capture MSB 2 Register Quad Decode Ctrl/Status Register Quad Decode Control Register Quad Decode Count 1 Register Quad Decode Count1 High Register Quad Decode Count 2 Register Quad Decode Count 2 High Register Mnemonic IB2CR IB3CR IB4CR IB5CR IB6CR IB7CR PWL0R PWM0R PWL1R PWM1R PWL2R PWM2R PWL3R PWM3R ICCSR ICCR ICT1R ICS1R ICL1R ICM1R ICT2R ICS2R ICL2R ICM2R QDCSR QDCR QDC1R QDC1HR QDC2R QDC2HR I/O Address 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F 0x0090 0x0091 0x0094 0x0095 0x0096 0x0097 R/W W W W W W W W W W W W W W W R/W W W W R R W W R R R/W W R R R R Reset 00000000 00000000 00000000 00000000 00000000 00000000 xxxxx00x xxxxxxxx xxxxx00x xxxxxxxx xxxxx00x xxxxxxxx xxxxx00x xxxxxxxx 00000000 xxxxxx00 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Users Manual 331 Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name Interrupt 0 Control Register Interrupt 1 Control Register Timer A Control/Status Register Timer A Prescale Register Timer A Time Constant 1 Register Timer A Control Register Timer A Time Constant 2 Register Timer A Time Constant 8 Register Timer A Time Constant 3 Register Timer A Time Constant 9 Register Timer A Time Constant 4 Register Timer A Time Constant 10 Register Timer A Time Constant 5 Register Timer A Time Constant 6 Register Timer A Time Constant 7 Register Timer B Control/Status Register Timer B Control Register Timer B MSB 1 Register Timer B LSB 1 Register Timer B MSB 2 Register Timer B LSB 2 Register Timer B Count MSB Register Timer B Count LSB Register Serial Port A Data Register Serial Port A Address Register Serial Port A Long Stop Register Serial Port A Status Register Serial Port A Control Register Serial Port A Extended Register Serial Port B Data Register Mnemonic I0CR I1CR TACSR TAPR TAT1R TACR TAT2R TAT8R TAT3R TAT9R TAT4R TAT10R TAT5R TAT6R TAT7R TBCSR TBCR TBM1R TBL1R TBM2R TBL2R TBCMR TBCLR SADR SAAR SALR SASR SACR SAER SBDR I/O Address 0x0098 0x0099 0x00A0 0x00A1 0x00A3 0x00A4 0x00A5 0x00A6 0x00A7 0x00A8 0x00A9 0x00AA 0x00AB 0x00AD 0x00AF 0x00B0 0x00B1 0x00B2 0x00B3 0x00B4 0x00B5 0x00BE 0x00BF 0x00C0 0x00C1 0x00C2 0x00C3 0x00C4 0x00C5 0x00D0 R/W W W R/W W W W W W W W W W W W W R/W W W W W W R R R/W W W R W W R/W Reset xx000000 xx000000 00000000 xxxxxxx1 xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxx000 xxxx0000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx 332 Rabbit 3000 Microprocessor Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name Serial Port B Address Register Serial Port B Long Stop Register Serial Port B Status Register Serial Port B Control Register Serial Port B Extended Register Serial Port C Data Register Serial Port C Address Register Serial Port C Long Stop Register Serial Port C Status Register Serial Port C Control Register Serial Port C Extended Register Serial Port D Data Register Serial Port D Address Register Serial Port D Long Stop Register Serial Port D Status Register Serial Port D Control Register Serial Port D Extended Register Serial Port E Data Register Serial Port E Address Register Serial Port E Long Stop Register Serial Port E Status Register Serial Port E Control Register Serial Port E Extended Register Serial Port F Data Register Serial Port F Address Register Serial Port F Long Stop Register Serial Port F Status Register Serial Port F Control Register Serial Port F Extended Register Mnemonic SBAR SBLR SBSR SBCR SBER SCDR SCAR SCLR SCSR SCCR SCER SDDR SDAR SDLR SDSR SDCR SDER SEDR SEAR SELR SESR SECR SEER SFDR SFAR SFLR SFSR SFCR SFER I/O Address 0x00D1 0x00D2 0x00D3 0x00D4 0x00D5 0x00E0 0x00E1 0x00E2 0x00E3 0x00E4 0x00E5 0x00F0 0x00F1 0x00F2 0x00F3 0x00F4 0x00F5 0x00C8 0x00C9 0x00CA 0x00CB 0x00CC 0x00CD 0x00D8 0x00D9 0x00DA 0x00DB 0x00DC 0x00DD R/W W W R W W R/W W W R W W R/W W W R W W R/W W W R W W R/W W W R W W Reset xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 Users Manual 333 334 Rabbit 3000 Microprocessor NOTICE TO USERS RABBIT SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE-SUPPORT DEVICES OR SYSTEMS UNLESS A SPECIFIC WRITTEN AGREEMENT REGARDING SUCH INTENDED USE IS ENTERED INTO BETWEEN THE CUSTOMER AND RABBIT SEMICONDUCTOR PRIOR TO USE. Life-support devices or systems are devices or systems intended for surgical implantation into the body or to sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling and users manual, can be reasonably expected to result in significant injury. No complex software or hardware system is perfect. Bugs are always present in a system of any size. In order to prevent danger to life or property, it is the responsibility of the system designer to incorporate redundant protective mechanisms appropriate to the risk involved. All Rabbit Semiconductor products are 100 percent functionally tested. Additional testing may include visual quality control inspections or mechanical defects analyzer inspections. Specifications are based on characterization of tested sample units rather than testing over temperature and voltage of each unit. Rabbit Semiconductor products may qualify components to operate within a range of parameters that is different from the manufacturers recommended range. This strategy is believed to be more economical and effective. Additional testing or burn-in of an individual unit is available by special arrangement. Users Manual 335 INDEX Numerics 5 V tolerant inputs ................ 11 D design features ........................ 9 5 V tolerant inputs ............. 11 BIOS ................................. 19 clock spectrum spreader .... 18 cold boot ........................... 52 input capture channels ...... 16 instruction set ...................... 9 interrupt priorities ............... 9 memory support .................. 9 parallel I/O ........................ 13 PWM outputs .................... 17 quadrature encoder inputs . 17 separate core and I/O power pins ............................... 18 serial ports ......................... 11 slave port ..................... 14, 53 system clock ...................... 12 time/date clock .................. 12 timed output pulses ........... 49 timers ................................ 15 design standards programming port ............. 18 Dynamic C ........................ 1, 19 BIOS ............................... 237 library functions .............. 242 periodic interrupts ........... 238 power consumption ......... 241 virtual drivers .................. 238 watchdog ......................... 238 G generating pulses .................. 50 A assembly language instructions ...... 40, 41, 42, 43 reading/writing to I/O registers .............................. 242 asynchronous I/O .................. 50 I input capture ....................... 105 instructions .................... 32, 247 alphabetic order .............. 261 arithmetic and logical ops . 36 I/O instructions ................. 39 load to constant address .... 33 load to register .................. 33 load using index register ... 34 push and pop ..................... 36 register exchanges ............. 35 register-to-register move ... 35 interrupts ............. 44, 48, 72, 97 Dynamic C ...................... 238 external interrupts ............. 99 interrupt latency ................ 49 interrupt service vector addresses ....................... 72 interrupt vectors .............. 100 multiple interrupts ............. 46 on-chip peripherals . 280, 282 priorities ................ 44, 45, 97 priviligeged instructions and semaphores ................... 46 semaphores ....................... 47 serial port ........................ 179 System/User mode .......... 321 updating registers ............ 243 B BGA package mechanical dimensions ..... 60 outline ............................... 61 bootstrap operation ............. 101 C clocks ............................ 80, 209 32.768 kHz oscillator ......................... 80, 81, 209 clock doubler ....... 83, 84, 225 clock speeds .................... 227 distribution ........................ 81 low-power design ............ 210 main clock ........... 80, 91, 209 oscillator circuits ............. 209 power consumption ....................... 85, 235, 236 spectrum spreader ................. 80, 86, 212, 225 timer and clock use ......... 244 timing issues ........... 225, 226 cold boot ............................... 52 comparison Rabbit 3000 vs. Rabbit 2000 ................ 259 compiler .............................. 127 crystal frequencies .............. 271 E EMI mitigation ................... 211 PCB layout ...................... 212 spectrum spreader ........... 212 extended memory I and D space ............... 27, 28 practical considerations ..... 30 stack segment .................... 29 external bus read and write timing ........ 64 L low-power design ............... 210 low-power options ................ 87 LQFP package LAND pattern ................... 58 mechanical dimensions ..... 57 pinout ................................ 56 Users Manual 337 M memory A16, A19 inversions (/CS1 enable) .........................121 access time .......................215 access time delays ...........220 access times with clock doubler ........................221 allocation of extended code and data space .............123 breakpoint/debug controller ................................123 compiler operation ...........127 data and clock delays .......216 I and D space ...................125 I/O access time ................223 I/O read time delays ........224 I/O write time delays .......224 instruction and data space support .........................124 power consumption .........234 read and write cycles (no wait states) ..................217, 219 read time delays ...............218 write time delays .............218 memory interface ..........25, 119 battery backup .................115 SRAM ..............................115 typical connections ..........116 memory mapping ................117 memory mapping unit .....23, 24 memory protection ..............284 memory timing ....................122 memory-mapping unit .........117 Modbus ................................196 parallel ports ........................129 conflict between Port A and Port F ...................129, 141 Parallel Port A .................130 Parallel Port B .................131 Parallel Port C .................132 Parallel Port D .................133 Parallel Port E .................137 Parallel Port F ..................140 Parallel Port G .................143 pin descriptions .....................62 alternate functions .............65 pinout BGA package ....................59 LQFP package ...................56 ports Rabbit slave port .............199 slave port lines .................203 slave port registers ...........204 power consumption .......85, 229 clock ........................235, 236 Dynamic C ......................241 mechanisms .....................232 memory ...........................234 sleepy mode .............231, 233 power management .............241 power usage, standby mode 210 programming port ...............269 alternate programming port .....................................270 use as diagnostic port ......270 PWM modulator ..........103, 311 PWM outputs ..................17, 50 Q quadrature decoder ..............110 quadrature encoder inputs .....17 O opcodes ................................293 revision block effects ......294 System/User mode ...........318 open-drain outputs .................51 oscillator ..............................209 main oscillator .................209 oscillators 32.768 kHz ..........80, 81, 209 main clock .................80, 209 output pins alternate assignment ..........90 R Rabbit 3000 block diagram ......................5 comparison with Rabbit 2000 .....................................259 crystal frequencies ...........271 design features .....................9 features ................................1 list of advantages .................6 on-chip peripherals ............11 programing port ...............269 revision history ........273, 276 specifications ...................2, 4 P Parallel Port D open-drain outputs .............51 Rabbit 3000A internal I/O registers ........327 opcodes ............................293 Rabbit Semiconductor history ..................................1 Z-World support ..................1 RAM segment relocation ....291 registers .................................21 accumulators .....................22 alternate registers ..............22 BDCR ..............................123 clocked serial port status registers .......................171 default values ....................73 GCDR ................................83 GCMxR ...................213, 319 GCPU ................80, 282, 319 GCSR ................................82 GOCR ................................90 GPSCR ......................88, 297 GRAM configuration ........79 GREV ........................80, 282 GROM configuration ........79 GSCR ..............................298 I/O bank control ..............145 IBxCR 146, 152, 154, 157, 296 ICCR .......................105, 108 ICCSR .....................105, 107 ICLxR ......................105, 109 ICMxR .....................105, 109 ICSxR ......................105, 109 ICTxR ......................105, 108 index registers ...................22 internal I/O registers ........277 interrupt priority register ...22 interrupts ...........................44 MB0CR ...........................319 MBxCR ...........................120 MECR .............................122 memory bank control ......120 memory-mapping segments ...........................118 MMIDR ...........121, 124, 295 MTCR .....................122, 319 PADR ..............................130 parallel port alternate functions ...............................67 PBDDR ...........................131 PBDR ..............................131 PCDR ..............................132 PCFR ...............................132 PDBxR ............................133 PDCR ......................133, 135 PDDCR ...........................133 338 Rabbit 3000 Microprocessor PDDDR ........................... 133 PDDR ...................... 133, 135 PDFR .............................. 133 PEBxR ............................ 138 PECR ...................... 138, 139 PEDDR ........................... 138 PEDR ...................... 138, 139 PEFR ............................... 138 PFCR ....................... 140, 141 PFDCR ............................ 140 PFDDR ............................ 140 PFDR .............................. 140 PFFR ............................... 140 PGCR ...................... 143, 144 PGDCR ........................... 143 PGDDR ........................... 143 PGDR .............................. 143 PGFR .............................. 143 PWL0R ........................... 312 PWL1R ........................... 312 PWL2R, PWL3R ............ 312 PWLxR ........................... 103 PWMxR .......................... 103 PxFR ................................. 67 QDCR ............. 110, 113, 314 QDCSR ................... 110, 112 QDCxHR ........................ 314 QDCxR ................... 110, 113 Rabbit 3000A internal I/O 327 RAMSR .......................... 291 reading/writing to I/O registers ..................................... 242 revision-level ID ............. 282 RTCxR .............................. 92 SAAR .............................. 166 SACR .............................. 166 SADR .............................. 166 SAER .............................. 166 SALR .............................. 166 SASR .............................. 166 SBAR .............................. 166 SBCR .............................. 166 SBDR .............................. 166 SBER ...................... 166, 167 SBLR .............................. 166 SBSR ............................... 166 SCAR .............................. 166 SCCR .............................. 166 SCDR .............................. 166 SCER .............................. 166 SCLR .............................. 166 SCSR ............................... 166 SDAR .............................. 167 SDCR .............................. 167 SDDR .............................. 167 SDLR .............................. 167 SDSR .............................. 167 SEAR .............................. 167 SECR .............................. 167 SEDR .............................. 167 SELR ............................... 167 serial port address registers .............................. 168 serial port control registers .............. 173, 174, 175 serial port data registers .. 168 serial port extended asynchronous registers .............. 176 serial port extended registers clocked serial mode .... 177 serial port HDLC mode extended registers ........... 178 serial port HDLC mode status registers ....................... 172 serial port long stop registers .............................. 169 serial port status registers 170 SESR ............................... 167 SFAR .............................. 167 SFCR ............................... 167 SFDR .............................. 167 SFER ............................... 167 SFLR ............................... 167 SFSR ............................... 167 shadow registers .............. 243 SPCR ............... 130, 204, 205 SPDxR ............................ 204 SPSR ....................... 204, 206 stack pointer ...................... 22 status register .................... 22 STKCR ............................ 290 STKHLR ......................... 290 STKLLR ......................... 290 SWDTR .......................... 292 System/User mode .......... 319 TACR ...................... 151, 154 TACSR .................... 151, 152 TAPR ...................... 151, 154 TATxR ............................ 151 TBCLR ................... 156, 158 TBCMR .......................... 156 TBCR ...................... 156, 157 TBCSR .................... 156, 157 TBLxR .................... 156, 158 TBMxR ................... 156, 158 WDTCR .................... 93, 292 WDTTR ............................ 94 WPCR ............................. 284 WPHR ............................. 285 WPLR ............................. 284 WPSxR ........................... 286 WPxHR ........................... 287 WPxLR ........................... 286 XPC register ................ 26, 27 reset ................................. 95, 96 revision history ........... 273, 276 alternate output port connection for numerous peripherals ................................ 276 expanded low-power capability ................................. 276 external I/O interface enhancements .......................... 276 ID registers for version ... 276 integrated Schmitt trigger 276 internal I/O address space 276 interrupt after I/O with short /CSx enabled bug fix .. 276 IrDA bug fix ................... 276 LDIR/LDDR with wait states bug fix ......................... 276 memory protection .......... 276 multiply-add and multiplysubtract ....................... 276 parallel port alternate functions ............................ 316 Port A decode bug fix ..... 276 PWM improvements ....... 276 quadrature decoder improvements .......................... 276 RAM segment relocation 276 secondary watchdog timer .... 276 stack protection ............... 276 System/User mode .......... 276 variants of block move opcodes ........................... 276 Users Manual 339 S secondary watchdog timer ..292 serial ports .....................11, 161 9th bit protocols ...............196 address registers ..............168 baud rates .........................163 breaks ..............................194 clocked serial ports (Ports A D) ................................182 clocked serial timing .......185 control registers (Ports AB) ......................................173 control registers (Ports CD) ......................................174 control registers (Ports EF) ......................................175 controlling RS-485 driver and receiver ........................193 data and parity bits ..........163 data registers ....................168 dummy characters ...........193 extended asynchronous mode registers .......................176 extended registers clocked serial mode (Ports AD) .177 extra stop bits, parity .......194 HDLC mode extended registers (Ports EF) ...........178 HDLC mode status registers (Ports EF) ..................172 interrupt service routines .192 interrupts ..........................179 long stop registers ............169 master/slave protocol .......196 Modbus ............................196 periodic interrupts ...........194 Ports EF synchronous communication ...................187 receive serial data timing .181 registers ...........................164 status registers .................170 status registers clock serial ports (AD) .................171 transmit serial data timing 180 slave port .......................53, 199 applications .....................206 hardware design ..............204 messaging protocol ..........207 protocols ..........................206 R/W cycles ......................200 registers ...........................204 typical connections ..........203 sleepy mode .................231, 233 specifications DC characteristics .............68 I/O buffer sinking and sourcing limits .......................69 power consumption .........229 spectrum spreader ...........80, 86 EMI mitigation ................212 registers ...........................213 stack protection ...................289 system clock ..........................12 System/User mode ......283, 317 I/O addresses ...................320 interrupts .........................321 interrupt prioritization .322 registers ...........................319 use ...................................324 complete operating system ............................326 memory protection ......324 mixed operation ...........325 W watchdog timer ......................93 secondary watchdog timer 292 writes short chip select timing ...297 X XPC register ..........................26 T timers ...................................149 Timer A ...................150, 151 Timer B ...........................156 timing quadrature decoder ..........315 short chip select 299, 300, 301, 302, 303, 304 writes ..305, 306, 307, 308, 309, 310 340 Rabbit 3000 Microprocessor

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Purdue - ECE - 477
LCD13TW523 (X10 modulator) . LM465 X10 module (x4)4Rabbit 3000RTL8019AS4 (ethernet).5MM74C922(Keypad decoder chip) 8Button Matrix
Purdue - ECE - 11
Introduction The Extreme Digital Butler (XDB) is a home control system to be used with existing commercial X10 products to perform home automation tasks. The XDB is a stand alone system allowing a home owner to operate it either from a local keypad a
Purdue - ECE - 477
Introduction The Extreme Digital Butler (XDB) is a home control system to be used with existing commercial X10 products to perform home automation tasks. The XDB is a stand alone system allowing a home owner to operate it either from a local keypad a
Purdue - ECE - 477
For Rabbit Semiconductor Microprocessors Integrated C Development SystemUsers Manual040313 019-0125-BThis manual (or an even more up-to-date revision) is available for free download at the Z-World website: www.zworld.comiiTable of Contents
Purdue - ECE - 477
ECE 477Digital Systems Senior Design ProjectFall 2004Homework 3: Final Design Project ProposalDue: Thursday, September 16, at ClasstimeTeam Code Name: _ Agamemnon _ Group No. _6_ Team Members (#1 is Team Leader): #1: _ Adam Wiedemann _ Signa
Purdue - ECE - 477
PINOUTSRCM3000RCM3300J1 (J3 on RCM3300)GND PA7 PA5 PA3 PA1 PF3 PF1 PC0 PC2 (n.c. on RCM3300) PC4 PC6-TxA PG0 PG2 PD4 PD2 PD6 n.c. (LINK on RCM3200/RCM3300) STATUS PA6 PA4 PA2 PA0 PF2 PF0 PC1 PC3 PC5 (n.c. on RCM3300) PC7-RxA PG1 PG3 PD5 PD3 PD7 n.
Purdue - ME - 270
ME 270 EQUATIONS (You probably will not need all of these equations)u=r r,r =rT2 T1=es!A ! B = ABcos&quot;= Ax Bx + Ay B y + Az Bz A = A!uMo = r ! F , M o = Fdv = vo + act1 s = so + vot + act 2 22 v 2 = vo + 2ac (s ! so )!F = ma&amp;
Purdue - ME - 270
Name (Print)_ (Last) (First) ME 270 Fall 2005 Exam 1 October 4, 2005 Circle your instructors name/lecture time: Jones MWF (9:30) Nauman MWF (11:30) Murphy TR (12:00) Li MWF (2:30)INSTRUCTIONS Begin each problem in the space provided on the examina
Purdue - ME - 270
Purdue - ME - 274
Assignment Schedule Summer 2007 ME 274 Basic Mechanics II School of Mechanical Engineering Purdue University 11 June 31 July, 2007 Room: ME 261 PERIOD 1M 2T 3W 4Th 5F 6M 7T 8W 9Th 10F 11M 12T 13W 14Th 15F 16M 17T 18W 19Th 20F DATE 6/11 6/12 6/13
Purdue - ME - 697
Course Syllabus ME 697S Continuum Mechanics Fall Semester, 2005 Instructor: Catalog Description: Eric A. Nauman (ME 187) email: enauman@purdue.edu, phone: 494-8602 The course begins with a presentation of the kinematics of continuous media and eleme
Purdue - ME - 577
ME 577/BME 595 D Human Motion Kinetics (3 credits) Engineering Elective Course Catalog Description: Study of kinetics related to human motion. Review of human anatomy and anthropometric data. Planar and three-dimensional kinematic analysis of gross
Purdue - ME - 577
Human Motion Kinetics Lower Extremities ME 577/ BME 595D POTR 262 MWF 1:30-2:20Eric A. Nauman, Ph.D. ME 373 enauman@purdue.edu (765) 494-8602Outline - Lower Extremities Anatomy - Hip, knee, and ankle Joint stability Focus on the knee Common a
Purdue - ME - 577
Human Motion Kinetics ME 577/ BME 595D POTR 262 MWF 1:30-2:20Eric A. Nauman, Ph.D. ME 373 enauman@purdue.edu (765) 494-8602Anatomy Basics We will focus on bones, joints (ligaments), and muscles in this course. Tissues: Connective tissues (bone,
Purdue - ME - 270
Name ME 270 Summer 2005 Final Exam 4 August 2005 INSTRUCTIONS Begin each problem in the space provided on the examination sheets. If additional space is required, use the yellow paper provided to you. Work on one side of each sheet only, with only o
Purdue - CE - 461
Traffic AnalysisFor Pavement Design PurposesTraffic Analysis VERY Important Factor in Pavement Design Consideration MUST be Given To: Load Magnitude Load Configuration Total Load Repetitions (Volume)Traffic Analysis BackgroundThree Proced
Purdue - CE - 563
HMA Mixture CharacterizationMixture CharacterizationMeasurement and Analysis of the response of HMA mixtures to Load, Deformation, and/or the Environment Material Properties Measured are used for Pavement Design and AnalysisMixture Character
Purdue - CE - 563
Federal Aviation Administration Flexible Pavement Design Method Part IFlexible Pavement Design Series of design curves based on the CBR design method Design curves depend on gear configuration Curves provide total pavement thickness Curves base
Purdue - CE - 461
DrainageEstimation of InflowNet Design InflowNeglectqd = q i + q g + q m - qv qd Net Design Inflow qi Surface Infiltration qg Groundwater Inflow qm Meltwater Inflow qv Seepage OutflowUse Only OneInflow Sources Surface Infiltratio
Purdue - CE - 563
CE 563Airport DesignFall 2006LectureDateDaySubject INTRODUCTION Introduction, Overview AIRPORT CONFIGURATION General Airport Layout Wind Analysis Obstruction Analysis I Obstruction Analysis II Geometric Design I LABOR DAY HOLIDAY Geometric
Purdue - CE - 461
Bases and SubbasesDefinitions Base Layer of Material Directly Below Wearing Surface Subbase Layer of Material Between Base and SubgradeRigid PavementPCC Base CourseSubgrade1Flexible PavementHMA Base Course Subbase SubgradeBase Mat
Purdue - CE - 461
Equivalent Single Axle Load CalculationsREFERENCESAASHTO Guide for Design of Pavement Structures, 1993 and Huangs Pavement Analysis and Design, 1993Traffic AnalysisWe Need a Single Design ESAL ValueAxle Load GroupsClass 1 2 3 4 5 6 7 8 9 10
Purdue - CE - 563
Federal Aviation Administration Rigid Pavement Design Method Part IRigid Pavements &quot;Portland cement concrete placed on a granular or treated subbase course that is supported on a compacted subgrade (AC 150/5320-6D, Change 3, paragraph 324).&quot;Rigi
Purdue - CE - 563
Bases and SubbasesDefinitions Base Layer of Material Directly Below Wearing Surface Subbase Layer of Material Between Base and SubgradeRigid PavementPCC Base CourseSubgradeFlexible PavementHMA Base Course Subbase SubgradeBase Materi
Purdue - CE - 563
Soil and Base StabilizationDefinition The Improvement of Pertinent Soil Engineering Properties by the Addition of Additives so that the Soil Can Effectively Serve its Function in the Construction and Life of a PavementReasons To Stabilize Use L
Purdue - CE - 331
ViscosityElastic Properties Perfectly Elastic Energy used to deform material is held within and used to restore original shape Energy Force ForceF AElastic Properties Stress is proportional to strainEE1Viscosity Moving plate caus
Purdue - CE - 461
CE 461Roadway and Pavement DesignLecture Date Day Subject INTRODUCTION Introduction, Pavement Types and Structures Design Methods, Factors Serviceability, Flexible Pavement Distress LABOR DAY HOLIDAY PCC Pavement Distress Structural Response SOILS
Purdue - CE - 563
Stresses in Flexible Pavement SystemsMulti-layered Elastic Theory Pavement behavior under wheel loads is characterized by considering it to be a homogeneous half-space subjected to a circular load of radius &quot;a&quot; and uniform pressure &quot;p&quot;Multi-laye
Purdue - CE - 563
Federal Aviation Administration Rigid Pavement Design Method Part IIIJointing PCC Pavements Temperature and moisture changes can cause volume changes and slab warping These can cause random cracking Joints are used to reduce these detrimental ef
Purdue - CE - 331
Lumber and Lumber SizesEngineering Materials IILumberRough SawnSurface Imperfections Caused by Primary SawingDressed LumberPlaned or Sanded S4S, Surface on all Four SidesLumber SizeIdentified by Nominal SizeDressed SizeSeasoned Lumber Un
Purdue - CE - 563
Federal Aviation Administration Pavement Design for Light AircraftLight Aircraft Pavements Aircraft with weights less than 30,000lbs No distinction made for critical and non-critical areas For aircraft weights less than 12,500lbs State DOT HMA
Purdue - CE - 331
Introduction to WoodEngineering Materials IIReasons for Using WoodSimplicity of Fabrication Lightness Reusability Environmental CompatibilityTree RingsTree CategoriesHardwoodDeciduous TreesSoftwoodConifersTree CellsPhysical Propertie
Purdue - CE - 563
Federal Aviation Administration Flexible Pavement Design Method Part IIAircraft DataMax. Ave. Takeoff Annual Aircraft Gear Type Departures Weight (lbs) 727-100 Dual 3,760 160,000 727-200 Dual 9,080 190,500 707-320B Dual tandem 3,050 327,000 DC-9-3
Purdue - CE - 563
Federal Aviation Administration Rigid Pavement Design Method Part IVReinforcing Steel Benefits Keeps cracks closed, thus aiding load transfer and minimizing debris infiltration Allows for increased joint spacing Bars or Mat (welded wire fabric)
Purdue - CE - 331
ViscoelasticityMaterial Response ElasticInstant deformation Deformation recovered =E SpringLoadtDeformationt to t1Material Response ViscousNot instant deformation Deformation not recovered = DashpotLoadtDeformationt to t1Page 1
Purdue - CE - 461
Structural Response Model A model that defines the response of the pavement to loading in terms of stresses, strains, and deflectionsSimply Supported BeamPdmaxL/2 L/2d maxPL3 48 EIPavement SRMs Differ in: Capabilities Complexity Mat
Purdue - CE - 331
PolymersHydrocarbons Composed of hydrogen and carbon Covalent bonding (sharing electrons)Single bondsH H- C -H HMethane (CH4) Each bond is made of two and only two electronsHydrocarbonsH H C=C H HDouble bondEthylene (C2H4)1Hydro
Purdue - CE - 461
CE 461 Roadway and Pavement DesignDr. John E. Haddock, P.E.Roadway &amp; Pavement Design Components Geometric Design (CE 562) Number of Lanes Lane Widths, Shoulders Curves (Horizontal, Vertical) Grades, Speeds, etc. All Are a Function of Traffic
Purdue - MSE - 582
Purdue - MSE - 582
MSE 595T Basic Transmission Electron Microscopy Laboratory III TEM Imaging - IPurpose The purpose of this lab is to: 1. Make fine adjustments to the microscope alignment 2. Obtain a diffraction pattern 3. Obtain an image Report Requirements No repor
Purdue - MSE - 582
MSE 595T Basic Transmission Electron Microscopy Laboratory V TEM Imaging - IIIPurpose The purpose of this lab is to: 1. Practice the overall alignment procedure for the microscope 2. Obtain lattice images from a crystal of large lattice parameter 3.
Purdue - MSE - 582
MSE 595T Basic Transmission Electron Microscopy Laboratory IV TEM Imaging - IIPurpose The purpose of this lab is to: 1. Practice the overall alignment procedure for the microscope 2. Obtain bright field (BF) and dark field (DF) images. 3. Record ima
Purdue - MSE - 582
MSE 595T Basic Transmission Electron Microscopy Laboratory II Basic TEM AlignmentPurpose The purpose of this lab is to learn the basic operation and alignment of the JEOL 2000FX transmission electron microscope. Report Requirements No report is requ
Purdue - MSE - 582
Purdue - MSE - 190
$MotorolaJob Opportunities:Materials Technology Announcements01 December 1999 Motorola Labs Announces Breakthrough in New Transistor Material that will Extend the Silicon Revolution Will Lead to Smaller, More Powerful Devices that Consume Less E
Purdue - MSE - 582
Purdue - MSE - 582
Purdue - MSE - 190
Patent Assignment for MSE 190Fall 2006Okay, here is the plan: each group will prepare ten-slide presentation to be presented during the final exam period, Tuesday December 11, 8:00 to 10:00 am in EE115 (next door to where we meet for regular clas
Purdue - MSE - 582
MSE 595T Basic Transmission Electron Microscopy Laboratory I TEM Construction and ControlsPurpose The purpose of this lab is to acquaint beginners with general TEM construction and a particular instrument in this case the JEOL 2000FX. Please refer
Purdue - MSE - 190
PURDUE UNIVERSITY School of Materials Engineering MSE 190 Fall 2006 3:30 p.m. EE117 Instructor: Kevin Trumble and Jeffrey Youngblood http:/Engineering.Purdue.edu/MSE/Resources/MSE190/ Welcome to our favorite class. This class is supposed to be a fun,
Purdue - MSE - 190
Microelectronic Packaging Quality and ReliabilityNiki Spencer BSMSE 1999, Purdue University What do you think of when you hear the word &quot;Packaging&quot;? Cardboard boxes and bubble wrap? Something that will protect whatever is inside. That is exactly wha
Purdue - MSE - 581
Purdue - MSE - 190
CONTAINER WARSGlass Steel Aluminum PlasticGlassSteel 210 300-800 $PET &lt;10 10-100PE 1 501$ 3E(GPa) (MPa)80 300* $Cost1$ 2Reusable3 piece2 piece2 pieceNATHANIEL WYETH (Dupont 1936-76)- Pop Container From Plastic? - Could Yo
Purdue - MSE - 190
Purdue - MSE - 597
Reference Textbook
Purdue - ME - 475
Lab 4: System Identification of the Servo TablePurpose1. Identify a transfer function to model the servo table 2. Demonstrate the effects of nonlinearities 3. Understand the process of system identificationIntroductionThe servo table will be us
Purdue - ME - 475
Lab 2: Advanced Analog Computer ProceduresPurposeDeveloping expertise at implementing transfer functions on an analog computer.IntroductionThis lab generalizes on the first lab in that transfer functions with widely-scaled coefficients and numer
Purdue - ME - 475
ME 475 SYLLABUSAUTOMATIC CONTROL SYSTEMSSpring Semester 2009 INSTRUCTORS: Professor Greg Shaver, ME 83 E-mail: gshaver@purdue.edu Office Hour: Tue 2:30 pm - 4:30 pmHTTPS:/ENGINEERING.PURDUE.EDU/ME475/WEBSITE:REQUIRED TEXT: Feedback Control of
Purdue - ME - 475
Lab 8: Frequency Domain Compensator DesignPurpose1. Design a compensator for the servo table that will add the 30 of phase at 55 rad/s. 2. Understand change in system response in the time domain brought about by compensation using frequency domain
Purdue - ECE - 438
Purdue - ECE - 438
EE438 Z-transform Example1EE 438 Z-transform ExampleDetermine the frequency and impulse response of the following causal system. 1 y (n) = - y (n - 2) + x (n) + x(n - 1) 2 Analysis: 1 Y ( z ) = z - 2Y ( z ) + X ( z ) + z -1 X ( z ) 2 1 Y ( z )