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101 EE Sample Final Redekopp Name: ________________________________________ Taken from Fall '02 / `03 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false FALSE b.) An 8-to-1 mux and no other logic can be used to implement any combinational logic function of 4 input variables: true / false FALSE c.) A 3-to-8 decoder along with (4) 8-input OR gates can be used to implement any combinational logic involving 3 input variables and 4 output variables: true / false TRUE d.) 3 separate 2-to-1 muxes can be used to build a single 4-to-1 mux: true / false TRUE e.) A 4-to-16 decoder with an enable can be used as a 1-to-16 demultiplexer: true / false TRUE f.) 5 flip-flops are required to implement a state machine with 5 states: true / false FALSE g.) In a state machine with Moore style outputs, a change in the external inputs can independently and immediately cause the outputs to change: true / false FALSE h.) In binary, performing X-Y can be performed by adding X to the 2's complement of Y: true / false TRUE i.) The characteristic equation of a JK Flip-flop is Q* = J Q' + K' Q : true / false TRUE j.) The passive inputs (hold state) of an active-hi set and reset SR-Latch are S=0, R=0: true / false TRUE 2.) State Machine Design (Down Counter w/ Restart): Design a synchronous state machine circuit that implements a 2-bit down counter (i.e. counts 11, 10, 01, 00, 11...). The circuit has an external input, R (RESTART), that when `1' should force the counter back to the 11 state no matter what the current state is. As long as R stays `1', the counter should stay in the 11 state. The circuit should also have one output Z. Z=1 when in the 00 state and Z = 0 otherwise. Let us use 4 states: S3 (initial state on reset) S2 S1 S0 The count should be 112 = 310 The count should be 102 = 210 The count should be 012 = 110 The count should be 002 = 010 a.) Complete the state diagram below by filling in all necessary transitions and the values of Z. On Reset (power on) R=0 R=0 R=0 S3 Z=0 R=1 S2 Z= S1 Z= S0 Z= R=1 R=1 b.) What is the minimum number of flip-flops required to implement this state machine? 2 Flip Flops c.) Complete the state transition/output table given below. (Note: We have provided the state assignment already). We have ordered the states in such a way to use gray code ordering, so take care when translating your state diagram to the transition/output table. Current State R=0 State S0 S1 S3 S2 Q1Q0 00 01 11 10 State S3 S0 S2 S1 Q1*Q0* 11 00 10 01 State S3 S3 S3 S3 Next State R=1 Q1*Q0* 11 11 11 11 Z 1 0 0 0 Output d.) Assume we will implement our circuit using D Flip-Flops. Use the K-Maps below to find minimal expressions for D1, D0, and Z. D1 Map R Q1Q0 00 01 11 10 0 1 Q1Q0 00 01 11 10 D0 Map R 0 1 Q0 0 1 Z Map Q1 0 1 0 1 2 3 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 Z = Q1'Q0' D1 = X + Q1'Q0' + Q1Q0 D0 = X + Q0' e.) Show how to implement the initial state (power-on/reset state) by connecting the PRE (PRESET) and CLR inputs of the FF's appropriately. Assume the signal /RESET is available to you. You do not need to implement the next-state or output-function logic. /RESET D0 D PRE Q Q Q0 /Q0 CLR 1 /RESET D1 D PRE Q Q Q1 /Q1 CLR 1 CLK f.) Using your design above draw the waveform for the sequence of states that the machine will go through and what the output will be for the given input sequence of X. Remember you are using positive edge-triggered devices. CLK /RESET R Q0 Q1 Z 3.) Sequential Circuit Analysis: For the Mealy-style state machine below, find the state diagram that it is implementing. Show all your work, including the intermediate steps you took to arrive at your solution. You do not need to concern yourself with which state we start in on reset. You may use the table provided below: X F D CK Q Q Q0 D CK Q Q Q1 CLK Area for equations: D0 = X D1 = X xor Q0 Q0* = X Q1* = X xor Q0 F = X+Q1 State Transition/Output Table: Current State State SA SB SC SD Q1, Q0 0 0 0 1 1 0 1 1 State SA SC SA SC X=0 Q1* Q0* 0 0 1 0 0 0 1 0 Next State / Output X=1 F 0 0 1 State 1 SD SB SD SB Q1* 1 0 1 0 Q0* 1 1 1 1 F 1 1 1 1 State Diagram: X=0/F=1 X=0/F=0 SA SC SB X=1/ F=1 X=0/ F=0 X=1/F=1 X=0/F=1 X=1/F=1 SD X=1/F=1 4.) Implement the following function using (2) 2-to-4 decoders. a.) Cascade the individual decoders to build a 3-to-8 decoder. You may use an inverter b.) Then use a 3-input NAND to implement the function G. G = X ,Y ,Z (2,5,6) /D0 2-to-4 Decoder Z Y X A B (msb) /E /D1 /D2 /D3 G /D0 2-to-4 Decoder Z Y A B (msb) /E /D1 /D2 /D3 5.) Examine the cross-connected gate pair at the bottom of the page and answer the following questions. a.) Label the inputs however you like and state what the passive input values are. S of HA is just XOR of the 2 inputs. Thus, passive input values are 0 for the X input of HA and 1 for the input of AND gate. Thus S is active hi and R is active lo. b.) State whether it is a valid memory cell (bistable element) and why. Answer for part b:____ This is NOT a valid bistable. It cannot SET. When Input to the is 1,1 which should be the set case, the AND gate passes Q which feeds back to the XOR and since S = 1, the XOR gate inverts Q to Q' and does not FORCE Q=1. 1,0 is NOT the Set case because it will output a 1 on the top input, 0 on the bottom which violates our notion that both outputs are equal (Q and Q as opposed to Q and Q'). Really, 1,0 is opposite of the hold case and thus always the illegal case. S X Half Adder Y S Cout Q Q /R S 0 0 1 1 /R 0 1 0 1 Q 0 Q X X Q 0 Q X X Case Reset Hold illegal toggling 6.) We need to create a circuit to perform the following conditional operation: if(x >= 10) then z = x + y; else z = x y; end if; x+y, x >= 10 or put another way... z = x-y, otherwise X, Y, and Z are all unsigned 4-bit numbers You can assume that X > Y so that Z will never be negative. Don't worry about overflow when performing X+Y. To implement this design you will use the following: (1) 4-bit adder 74LS85 4-bit comparator (see logic diagram on the next page) A few other logic gates a.) Finish the design below. Your inputs should be clearly labeled X3 X0 , Y3 Y0, and your output should be labeled Z3 Z0. You may use temporary variable labels rather than wires to connect your devices. b.) When you have completed your design, go back annotate your design with the test case of X=9, Y=5 and show the intermediate outputs and the final output Z. X0 X1 X2 X3 0 1 0 1 0 0 1 A0 A1 A2 A3 B0 B1 B2 B3 IA<B IA>B IA=B O A=B 74LS85 O A>B O A<B Cin X0 X1 X2 X3 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 Z0 Z1 Z2 Z3 Y0 Y1 Y2 Y3 4-bit S2 Adder S3 Cout 7.) During your summer vacation Internet music company, MP3 Worldwide, hires you for selling MP3 players. Apart from the hourly salary they offer you a performance bonus of $1 for each MP3 player you sell for the week. Assume you can only sell between 0 and 99 MP3 players a week (never more than 99). If you sell 75 or more MP3 players in a week you get an additional bonus of $25. So if you sold 10 MP3 players in a week you would get a $10 bonus. If you sold 90 MP3 players you would get a $115 bonus (90 + 25). Build a circuit to calculate the bonus. The input is a 2-digit BCD number, X, for how many MP3 players you've sold. Your output should be a 3-digit BCD number, Y, though the maximum value of the hundred's digit is 1 (i.e. at most you can receive a $124 bonus since you can only sell 99 units). input: X = X80X40X20X10 X8X4X2X1 output: Y = 000Y100 Y80Y40Y20Y10 Y8Y4Y2Y1 a.) Using only (2) 4-bit 74LS85 comparators, produce a 1 bit output, S, to detect whether the number of MP3 players you sold is 75 or more. (i.e. strictly greater than 74) X1 X2 X4 X8 0 0 1 0 0 0 1 A0 A1 A2 A3 B0 B1 B2 B3 IA<B IA>B IA=B O A=B 74LS85 O A>B O A<B X 10 X 20 X 40 X 80 1 1 1 0 A0 A1 A2 A3 B0 B1 B2 B3 IA<B IA>B IA=B O A=B 74LS85 O A>B X >= 75 (S) O A<B b.) Using your output, S, from part a, and 2 BCD adders, produce the output Y. 0 0 S 0 X 80 X 40 X 20 X 10 B8 B4 B2 B1 0 S 0 S X8 X4 X2 X1 B8 B4 B2 B1 A8 A4 A2 A1 Cout A8 A4 A2 A1 Cout 4-bit BCD Adder S8 S4 S2 S1 Cin 4-bit BCD Adder S8 S4 S2 S1 Cin 0 Y 100 Y 80 Y 40 Y 20 Y 10 Y8 Y4 Y2 Y1

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