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3 Pages

### AppendixAUnit8_4Sol

Course: EE 101, Fall 2007
School: USC
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Word Count: 286

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Unit 8.4. 4 Bistables, Latches, and Flip-Flops 1. Examine the proposed bistable circuit below. Determine whether it is a valid bistable or not. If so, write out the function table, replacing the X and Y labels with the appropriate Set and Reset inputs. If it is not a valid bistable, indicate which operations (set, reset, remember) it cannot perform. 1 I0 Y I1 S Q X Y This is a valid bistable because it can...

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Unit 8.4. 4 Bistables, Latches, and Flip-Flops 1. Examine the proposed bistable circuit below. Determine whether it is a valid bistable or not. If so, write out the function table, replacing the X and Y labels with the appropriate Set and Reset inputs. If it is not a valid bistable, indicate which operations (set, reset, remember) it cannot perform. 1 I0 Y I1 S Q X Y This is a valid bistable because it can set, reset, and remember as shown in the table. We start by finding the hold case which is the input values that allow Q to feedback through the circuit. The hold case would be 1,1. From there we can activate one input at a time to find whether the output can be set and reset. X=S Y=R Q* 0 0 1 illegal 0 1 1 Set 1 0 0 Resest 1 1 Q Hold/Remember 2. Design a D-Latch ONLY using NAND gates (no inverters or any other gates.) The circuit has been started for you. D CP Q' Q 347 3. Complete the following waveform for a positive edge-triggered SR-FF CLK S R Q Q 4. Complete the following waveforms for negative edge-triggered D Flip-Flops. X D CK Q Q D1 /D1 Z D CK Q Q D2 /D2 CLK CLK X D1 D2 Z 348 5. Complete the following waveform for the JK-FF design shown below. Note: The clock inputs of the last two FF's are not connected to CLK but to the outputs of the previous FF. After completing the waveform, go back and think about what this circuit is doing assuming Q2,Q1,Q0 form a 3-bit unsigned number. 1 CLK 1 Q0 J CK K Q Q 1 1 Q1 J CK K Q Q 1 1 Q2 J CK K Q Q The circuit if counting (i.e. Q2Q1Q0 = {000, 001, 010, 011...}). 349
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