UMHE-http://atlas.physics.lsa.umich.edu/docushare
CSM-4 UMHE-05-1 & Final CSM Design Manual
Design of the Chamber Service Module & Prototype 4(Rev E-) University of Michigan February 22, 2007
J. Chapman, P. Binchi, R. Ball, T. Dai, & J. Gregory
Final CSM Design & Development at UoM
OVERVIEW OF PROGRAM
The CSM-0 (a prototype CSM) is documented in specifications1 on the University of Michigan ATLAS web server Docushare. It was developed as a first step toward the design of a production muon front-end readout multiplexer, initialization controller, timing distributor, and calibration controller. Documents on the DocuShare server are linked via ATLAS Electronics > MDT Electronics and are called CSM-0 Development and Users Manual and CSM-0 Design Internals Document. The general characteristic of the design has not changed and is specified in numerous ATLAS muon publications as the near chamber part of the NIMROD2. The work to design the CSM began with simulations of the dataflow and were reported in the LEB99 meeting in Snowmass3 and are available on the Docushare server. The simulations were performed in VerilogHDL. A similar VerilogHDL description of the AMT-34 will when a similar description of the ROD5 is complete, provide a tool for continuously evaluating the design as it matures. The prototype CSM-0 synthesized from the original VerilogHDL code will serve as an active test fixture for the design. This prototype was built as a 6U VME module containing the CSM unit, a JTAG interface, an LHC clock emulation, and a VME readable output FIFO. Since the timing and control functions of the LHC, the TTCrx6 chip and its associated driver components, were not available in the test envi-
1. http://atlas.physics.lsa.umich.edu/docushare/default.htm 2. http://umaxp1.physics.lsa.umich.edu/~chapman/atlas/nimrod.ps 3. Proceedings of the LEB99 conference at Snowmass (1999) 4. http://atlas.kek.jp/%7earaiy/amt1/index.html 5. http://www.nikhef.nl/pub/departments/et/atlas)mdt/index.html 6. http://www.cern.ch/Atlas/GROUPS/FRONTEND/Ttc1.htm
Overview of Program
ronments, these functions are designed into a separate Xilinx called the TTCem circuit. This additional Xilinx is required to accept the external trigger, to provide the EVID and BCID, and to synchronize the trigger with the free running clock that generates the simulated LHC crossing intervals. The differences between the CSM-0 and the final CSM unit mounted on chambers are significant but the two units have a one to one correspondence. The final on-chamber version is simpler in that it does not need to perform event building. Since the ROD must form events from 6+ CSM output streams, there is no need to do this job twice. The on-chamber CSM is therefore expected to do simple time-division multiplexing of data from the 18 TDCs. With this scheme the TDC from which any particular unit of data originates is determined from the word position in the time sequence. If no data is available from a specific TDC, an idle position-holder is sent. The full event building version of the CSM-0 can be thought of as a CSM/ROD pair that handles only one chamber in contrast to the input ROD module (called an MROD) where the event building takes place. Thus, the on-chamber CSM does not have a trigger ID FIFO, a deep input FIFO, or a word count FIFO. It has an optical output encoder and driver to send 32-bit words to the MROD module which accepts its output and the output from other CSM modules. For compatibility with the CSM-0, the CSM-4 can be configured to do event building in exactly the same format as done by the CSM-0. In this mode the CSM-4 prepares an output record exactly in the format of the CSM-0 but transmits this data to the optical output link. When no data is being sent, optical idle codes are sent. This version can be used with a simple receiver/recorder package developed as a Linux data recorder only. The hardware of the Linux package was developed at CERN and can be either based on the S32PCI64 PCI card with a GOLA receiver board for a single chamber readout or with a 4 channel Filar card for readout of up to 4 chambers. This software is documented separately and available on the Docushare server at Michigan. As an alternate to the GOLA/Filar option a Linux based event builder in software is available. This option uses the time division version of the CSM for compatibility with the MROD and performs the MROD tasks in software. Output in this version is compatible with the MROD but data rates possible are far short of that demanded of the MROD. The overall flow of data from the chamber wires up through the readout drive is represented in Figure 1 on page 2. In the final MDT system the Readout Driver will be the MROD. In test systems tit can be a single Linux processor with Filar cards. The simulation performed for the CSM/ROD contained the 18 TDC inputs each with their own serial data and clock. It described the output flow of data along the channel destined for the ROD. Event data units were collected from the TDCs by the CSM and transmitted in turn to the ROD modules. Data is transmitted from the CSM as 32-bit units serialized and sent on a single fiber. The 32-bit data units are either TDC headers, trailers, time digitizations, or various control words. The primary task of the CSM, called the CSM-4, is time-division multiplexing. Data from each TDC is sent as requested by the level 1 trigger when the front-end link from the individual TDC becomes free, i.e., when data from all previous triggers are sent. Individual events are separated by header and trailer words. These header and trailer words are selectively enabled for transmission in the TDC. At least trailer words are required to indicate the end of event. The simulation assumes that both headers and trailers are sent for redundancy. In time division multiplexing mode all the 32-bit data words sent along the optical fiber to the ROD are sent
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Overview of Program
with odd parity. This parity is placed in the TDC source field (bits 27-24) of each word. The specific bit assignments are given below. For words received from the TDCs, one of these bits represents bad parity seen for the word during the TDC to CSM-4 transmission.
FIGURE 1.
The Position of the CMS in the muon data flow. Chamber Service Module ReadOut Driver
Mezzanine Card
ASD/TDC
CSM
18/CSM 6/ROD
Event Builder
MROD or Linux ROD
In Faraday cage
1 per chamber
1 ROD Card/TgrTower
The time-division CSM collects data from each of 18 individual TDCs into individual FIFOs, polls for data available in these 18 FIFOs, and if present simply forwards the TDC data to the ROD module in the time slot specified for that TDC. The time position in the output stream defines the source of the data. As a means to guarantee that the time positions are synchronized between the sending CSM and the receiving ROD module, a spacer word is sent as the 19th data unit each cycle. To insure synchronization of the sending and receiving clock, 2 optical link idle words (not to be confused with the idle word used to flag no data from an individual TDC) are sent following the spacer word. The basic flow of information is illustrated in Figure 2 on page 2.
FIGURE 2.
Serial data flow and event transmission by the CSM
TDC TDC
10 11 10 10 9
10 9 9 8
9 8
18 TDCs maximum
10 TDC TDC 9
Trailer Spacer Word
9 9
9 8
8
8
7 8
7
Data
Header
Spacer Word
0
Idle Words
1
2
3
4
5
6
13 14 15 16 17
Time Multiplexed TDC Data Words
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CSM
Design Specifications
DESIGN SPECIFICATIONS
Module Subsections
The CSM will have six subsections. Figure 3 on page 5 illustrates these blocks, the JTAG initialization, the trigger timing and control, the optical transmitter, the serial to parallel receivers, the multiplexer, and the environment monitor. The list below further defines the content of these blocks.
1. The JTAG initialization block communicates to an external controller. This controller can be any unit which adheres to the JTAG standard that does not use the pause state during instruction or data shifting. The CERN designs for the TTCrx and GOL chips do not function correctly with JTAG tap controllers that use continuous clocks and enter pause states. Opto-isolation circuits provide for local ground separation from the external JTAG controller. Thus the external controller must supply its own power and ground to the CSM unit. 2. A second subsection contains the TTCrx chip and its optical receiver. It contains the reset functions, the EVID and BCID registers, the phase adjustments for the 40MHz clock, the decoding of the LVL1 trigger, and the calibration functions. The CSM makes standard use of the TTC system and requires no special interconnections. Since the CSM is configured as a simple time division multiplexer, it does not use the BCID and EVID registers when configured as a time division multiplexer. 3. The optical transmitter is based on the CERN-designed radiation-hard GOL chip and along with an Advanced Laser Systems VCSEL diode. The GOL unit accepts 32-bit words at up to 40Mhz for transmission along an optical fiber. The original design of the CSM assumed that 32-bit words at 25MHz was the maximum rate at which data needed to be sent. When data words are received at 40MHz from all TDCs (along with the spacer/idle words), the CSM can operate with an output transmitter at 25Mhz. An alternate option permits the CSM to transmit 32-bit data at 40MHz. This can be accommodated by the GOL and VCSEL if needed. At the MROD the 32-bit words are collected, the spacer word checked, the TDC empty words removed, and the actual TDC data stored. The optical transmission idle words do not appear at the receiver output. They serve only as synchronization characters. 4.
Input from the TDCs arrives as a serial bit stream that is assembled into 32-bit words under the control of a sequence that seeks a start bit, assembles 32 data bits, tests a parity bit, and outputs the 32-bit data word with an accompanying data available bit. Since the entering data from the TDC arrives with arbitrary phase with respect to the local copy of the serial AMT output clock, a phase sampling circuit must be activated during the initialization to select the appropriate phase for sampling the incoming data. After this sample period the bit clock from the TDCs can be disabled to reduce EM noise and the mezzanine card power associated with generation of this clock. The AMT output clock rate can be selected to be 40MHz or 80MHz. The original design planned for use of the 40MHz rate. However, when the pair mode of the ASD-AMT chain was found to have difficulties when narrow noise pulses, the 80MHz option has been adopted and verified to function successfully.
5. An input multiplexer subsection polls for data from the Serial to Parallel circuit at the AMT output clock rate, transmits found data to 18 individual FIFOs, one for each TDC. Once the data is stored the data available bit is reset. This section include
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Design Specifications
input buffer overflow control which is necessary when 80MHz input operation is enabled. To avoid critical data loss the CSM selectively ignores incoming data when the input buffers are in danger of overflow. Since input words from the AMT are of varying importance, a hierarchy of word types is defined. Header and trailers are designated as critical, leading edges and errors as next, and trailing edges and mask words as the lowest priority. Two buffer capacity thresholds are defined. When data words in the buffer exceed the lower threshold, no additional trailing edges or mask words are accepted. When the higher threshold is exceeded no leading edges or error words are accepted. If the thresholds are set properly, headers and trailers will never overflow the buffers at the trigger rates permitted. To inform the MROD of any deletions, two flags are sent with the event trailer. Bits 25 and 24 of the words sent to the MROD accept these two flags. In normal words these bits are set to zero. In the trailer word from an AMT, bit 24 flags the rejection of one or more leading edges or error words and bit 25 flags the rejection of one or more trailing edges or mask words. These two bits originally contained the TDC number which is both redundant (the time division position specifies the TDC) and limited to 4 bits with 18 AMTs permitted.
6. A second polling multiplexer scans the individual TDC FIFOs for data and if found sends the 32-bit data unit to the optical transmitter. If no data is present in the FIFO for the polled TDC, an empty TDC flag word is transmitted for the TDC. This section was designed for 25MHz operation but with the change to accept data from the AMT at 80MHz, operation of this polling multiplexer at 40MHz is anticipated but must still be checked. 7.
At the conclusion of the 18 step TDC poll, a spacer word is inserted to insure time step synchronization between the CSM and the MROD. This word contains a special code, Dnnnnnnn, in hex. Two optical link idle code words follow the spacer word. These insure link synchronization and do not appear as words to the MROD.
8. The TDC data words and their parity bits are modified so as to include parity information both for the received parity from the TDC and to define independently the outgoing parity. Since the TDC identifier field (4-bits) of the TDC word is redundant, given that the data source is defined by the location of the word in the time sequence, part of this field is overwritten with two parity related bits. The lower two bits are used for flags as discussed in a later section. Bit 27 is set to contain a parity error flag if the incoming word from the TDC fails the parity test done within the CSM. Bit 26 of the outgoing TDC word is set so that the parity of the outgoing word is odd (including the Bit 27 error flag). 9. The final subsection provides for voltage and temperature monitoring. The cable from each mezzanine card provides a connection to its analog voltage regulator output, its digital voltage regulator output, and to an on-board temperature sensor. These 18 x 3 lines plus similar lines from the CSM regulators and temperature sensor, are routed to a 64 channel analog multiplexer and ADC. The 64-channel ADC is a direct copy of the ELMB version fabricated on the back side of the CSM. The
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Design Specifications
The Block Diagram
FIGURE 3.
The Block Diagram. The Opto-isolated JTAG connection is provided by the ELMB in addition to the analog multiplexer for voltage and temperature sensing. Several different sources of the JTAG have been implemented for testing as well.
Tubes
TTC Fibre Clk, L1A, Calib
TTC
TTCvi Central Control
CSM Hedgehog Mezzanine
40 Serial to Parallel JTAG ELMB Mux TTCrx Mux Xtmr
100 Mbyte/s
MROD
Gigabit Ethernet
To ROB
Opto-isolated copper JTAG
18 Mezzanine Cards Maximum
Monitor
ELMB
CAN Bus
64 ADCs
Not on CSM-1
Serial to Parallel
The TDC resets to an idle state from which it sends no data. The reset can be derived from the TTCrx and also received by the CSM via JTAG. This reset erases any previous activity on the input lines from the TDC. After a reset, the phase of the incoming data from the TDCs must be sensed. This is done using the 4 phases of the serial clock provided by the Xilinx Digital Clock Manager, DCM. This unit includes a DLL for clock locking and also provides 0, 90 180, and 270 degree versions of the clock. To perform the needed sampling of the phase of each TDCs arriving data bits, an automatic selection of the best choice between the 4 phases is made. The clock phase is chosen so that the data changes between 180 and 270 degree versions of the chosen clock phase. When the sampling circuit stores its choice (after sampling over 2-3 cycles), normal data sensing can begin. At this point the individual clocks from each of the TDCs can be disabled saving power and potential clock noise pickup at the mezzanine card. In normal operation, the start bit is sensed, 32 data bits are assembled into a shift register, parity is tested, and a stop bit is demanded for each TDC data word. Parity is tested and an error bit is saved for reporting to the MROD. At this time the data ready flag is set indicating that the 32-bit output register plus a parity flag contains data. This register cannot change more than once every 36 bit times since the data stream contains a start bit, 32 data bits, parity bit, and 2 stop bits.
Input Accumulation
The 32-bit data words arrive from each TDC based on the data present in that particular TDC and the availability of its output sequencer. Therefore, although all TDCs send data for a given EVID before processing the next, data from a given TDC does not have a well defined timing relationship to data for the same EVID from other TDCs. The CSM is designed to be a simple time division multiplexer and is not responsible for event building. Thus, it can simply transmit the assembled 32-bit words to the MROD in the next available time slot for the particular TDC. At the 40MHz serial clock rate data
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Design Specifications
arrives at a maximum rate of 1.143 MBits/s from each TDC. One word from each channel is transmitted each 21 word cycle. Any rate of serial transmission on the fiber greater than 97 MBytes/s will not require any buffering within the CSM. This data rate can easily be handled by the GOL sending 32-bit words at 25MHz or greater. For operation with a serial input clock at 80MHz, the situation is such that twice this rate would be required to assure that no data is lost. Since the GOL and VCSEL are certified to run only up to 40MHz, a possibility of data loss exist even at the highest rate possible. To prevent the loss of critical sequencing information, a buffer control scheme is included that will selectively delete trailing edges and mask words at one threshold and leading edges and error words at a higher threshold always leaving room for heders and trailers. When deletions occur the MROD is informed on an event by event basis by providing two flags in the event trailer word when words are deleted in these two classes. The AMT word count is not changed when these deletions occur providing the MROD with a second indication that deletions occurred. Note, it is possible that only the higher threshold flag is set since deletion flags are only set when a word of their respective class is deleted. If no low threshold word type appears in the data stream no deletion can occur even if the buffer is filled above its threshold.
Multiplexer
It is expected that both header and trailer words will be enabled in the TDC. These header and trailer words each contain the EVID. Since the CSM does no test beyond parity checking, these words are processed the same as any other data words from the TDC. Data words can be sent to the MROD whenever the link is up and the currently polled TDC has data available. The link will be unavailable from a reset until resynchronization is established. The CSM will send data only when the link is active and must therefore, be resynchronized whenever the link goes down. The amount of data lost will generally be significant since resynchronization requires many clock cycles. The loss of synchronization is sensed at the MROD, were a reset will be initiated. This reset will probably need to set the CSM and TDC to idle over JTAG, disable triggers being sent from the CSM to the TDCs, resynchronize the link, and reestablish triggers. Lost data for the interval required to do this resynchronization needs to be flagged at the MROD where the BCID and EVID for triggers is available. Information defining the last event fully transmitted to the MROD is available in the EVID/BCID values within the data. A reset and resynchronization for any reason will require EVID/BCID resynchronization between units that have not lost data and have advanced their EVID. BCID resynchronization will take place every turn of the LHC machine. If triggers are initiated only after a complete turn, synchronization of BCID is assured.
Fibre Protocol
The output from the CSM is in 32-bit data units, either TDC data words, empty TDC codes for TDCs that have no data, spacer words, or link idle codes. These words are to be sent to a fiber encoder/driver. The low power CERN GOL chip can accept 32-bit words at rates up to 40MHz. This is well above the 25MHz required to remain ahead of the data arriving from the TDCs at 40MHz serial input rate. The choice of the 25MHz transmission clock, was based on the expectation of 40MHz serial rate. With an 80MHz serial input rate we expect to operate the output link at its highest speed, 40MHz. The code in the CSM-4 is currently arranged to send no data to the GOL until the first trigger
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Design Specifications
is seen and to not send data for time division cycles (19 word groups) when no data is available from any TDC.
Data Word Formats
The data words from the TDC are described in the AMT-3 document7 and summarized in Table 1 on page 7. Note that the header and trailer words from the TDC provide the EVID and the BCID words. The location of these bits permits a check of the data arrival consistency as described above. The TDC data words also contain an error bit that indicates when data has been missed. The data miss bit is to be interpreted as a flag that data was lost between the time of the last data unit without a flag set for a given TDC and the data units with flags for that TDC. The CSM defines two additional IDs, one for the TDC empty word and one for the spacer word. The IDs for these words are tentatively
TABLE 1.
TDC Data Word IDs and contents
Word Contents Depends on ID Type
2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0
ID 31-28 1010 1100 0010 0011 0100 0110 0111 0111
TDC TDC TDC TDC TDC TDC TDC TDC 0000 0001 Channel Channel
EVID EVID Mask Flags T E Width Unused Coarse Time
BCID Word Count
Fine Time Fine Time Errors BCID R L1 Occupancy
Coarse Time
defined in Table 2 on page 7. In the time division multiplexing scheme each TDC word is sent in a time slot defined in terms of the spacer word position. Following the spacer word, TDC unit 0 data is sent or if no data is available, an TDC empty word is sent. The next time slot contains TDC unit 1 data if any is available. This process is described in a note by Thei Wijnen8 on the NIKHEF web page. The TDC field in Table 1 on page 7 is
TABLE 2.
CSM IDs for TDC empty (0000) and Spacer word (1101)
Word Contents Depends on ID Type
2 7 0 0 2 6 1 0 2 5 0 0 2 4 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 0 0 1 1 1 0 9 8 7 6 5 4 3 2 1 0
ID 31-28 0000 1101
replaced by the 4-bit field [Bit 27 - 24] composed of [a TDC parity error flag (bit 27), a force odd parity bit (bit 26), and a 2-bit buffer control flag (bits 25 and 24)], where TDC
7. http://atlas.kek.jp/%7earaiy/amt1/index.html 8. http://...lookup Thei Wijnen note on the data stream for TDM
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Design Specifications
parity error flag = 1 if the parity of the received TDC word was not correct and where the force odd parity bit is set to make the overall 32-bit word odd parity. The 2-bit buffer control flag is only sent with an AMT trailer (in other words the bits are 00) with bit 25 indicating deletion of one or more trailing edges or mask words and bit 24 indicating the deletion of one or more leading edges or error words. A special set of formats exist for the CSM-4 when operating in event building mode. In this mode the CSM-4 generates output comparable to that of the CSM-0. These special outputs are defined in Table 3 on page 8. There are CSM headers and trailers defined, wire encoding for TDC 16 and 17, and a set of error conditions that flag incomplete events, events with one or more parity errors in transmission from one or more TDC, and the conditions that caused the error. The wire encoding used in the CSM-0 is also used here. See the CSM-0 Users manual9 for details of this encoding.
TABLE 3.
Special CSM-4 Output Word Formats in Event Builder Mode
Word Contents Depends on ID Type
2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0
ID 31-28
CSM-4 event builder output formats defined to date 0101 0101 0101 0101 0101 1010 1100 0011 0100 1001 1011 1101 0000 0010
TDC TDC Wire Number Wire Number EVID EVID EVID Error Code EVID EVID EVID T E Width Coarse Time Coarse Time BCID Word Count Word Count Abnormal TDC Word Count BCID Word Count Fine Time Fine Time
a
b
a. This subID flags an abnormal event termination which is preceded by the error word with subID zero. b. This CSM sub-type is a pad word, and appears only when event buffers are padded to a multiple of 64(256) words. These follow the CSM trailer (sub-type 1101 or 1011), and the Word Count does not include them in the total.
For the CSM-4 event builder, the error words beginning with ID and subID 0x0101 and 0x0 the meanings of the remaining bits are given in Table 4 on page 8 below.
TABLE 4.
Flag Bits for CSM-4 Event Builder Errors
Error or Flag Bit Posn
23 22 21 20
Abort was due to missing header/trailer (hdr_trl_abort) Abort was due to missing header (miss_hdr_abort) Abort was due to dpram over threshold Abort was due to a timeout waiting for data
9. http://atlas.physics.lsa.umich.edu/docushare/dscgi/ds.py/View/Collection-207
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The CSM Module Specifications
TABLE 4.
Flag Bits for CSM-4 Event Builder Errors
Error or Flag Bit Posn
19 18 17-0
Flag -- BCID matching is disabled Flag -- EVID matching is disable Flags for AMTs with both good and complete data
THE CSM MODULE SPECIFICATIONS
Component Details
The TTCrx
The TTCrx has the following functions: The TTCrx receives fibre data from the central timing and control logic, regenerates the 40MHz LHC clock, receives the commands, and presents these commands including the LVL1 trigger to external logic. It maintains counters for EVID and BCID that are presented to external pins along with the LVL1 accept and other commands. It provides for independent phase adjustments of two copies of the 40MHz clock. It provides for calibration pulses coordinated with LVL1 triggers appropriately delayed from the calibration timing.
The timing and calibration role of the TTC system is illustrated in Figure 4 on page 10. In this figure, the role of the TTCrx for timing and calibration pulsing is shown. In addition, the role of the JTAG in establishing the parameters for the test calibration within the CSM and mezzanine cards is illustrated. The TTCrx provides two clock outputs each with its own phase adjustment down to the 104ps least count. One of these phases will be adjusted for gating of commands from the TTCrx including the LVL1 accepts and resets. The second phase will be used to initiate the calibration pulse, permitting adjustable timing to the TDCs in 104ps steps. The CSM-4 acts in response to a subset of both long and short format TTC commands. The only short format command to which it responds, besides the EVID and BCID resets, is that which initiates a calibration trigger sequence for the attached mezzanine boards. This command has user bits 3 and 6 set on, and all other bits set off or ignored (010010xx). The two least significant bits are ignored as they correspond to the EVID and BCID clear strobes. A document specifically concerned with calibration10 is available.
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The CSM Module Specifications
Three Individually Addressed Commands (IAC), or long format commands, initiate CSM-4 activity. These are detailed in Table 5 on page 9 below, and are discussed at length in Reference on page 10.
TABLE 5.
Individually Addressed Commands recognized by the CSM-4
Data Bits
xxx Strobe Duration Strobe Duration Initiate TTC reset Set the duration of the calibration strobe to the given number of 25ns clock tics Set the duration of the calibration strobe, as above, and initiate the strobe itself.
SubAddress 1 2 3
Action
The three commands detailed in Table 5 on page 10 are external TTC commands, i.e., they are relayed to the circuitry attached to the external busses and lines of the TTCrx. Each TTCrx also responds to several internal commands, sometimes with detectable external actions. In particular, the CSM-4 monitors for the response to the internal ERDUMP and CRDUMP commands, which result in the external presentation by the TTCrx of the contents of 10 of its 20 8-bit registers. This content is latched by the CSM4 and included in the JTAG bit-stream shifted out of the chip. See the section on JTAG programming in this manual for more details.
FIGURE 4.
The Role of the TTCrx and JTAG Systems for Calibration. Calibration parameters are established via JTAG from the DCS system followed by TTCvi commands as needed to generate the signal injection and to trigger a level 1 accept for acquisition of the data.
L1A Set orbit pulse time Crossing synchronized pulse
1 2
TTCvi Mk II
L1A N ticks delay
TTCrx
CSM
pulse JTAG setup
DCS
Setup data for pulse on JTAG lines to CSM
ASD
The Serial to Parallel Units
In the CSM-0 the serial to parallel conversion of data from the TDCs was done in three small Xilinx FPGAs, each processing 6 channels of TDC data. This same arrangement could be implemented in the final CSM. However, the availability of more logic and higher pin counts in newer FPGAs makes it possible to place all channels in a large chip along with logic for the multiplexer. The presence of DLL clock circuits with multiple, phase outputs further aids this process by enabling incoming data sensing at the phase appropriate channel by channel. The serial to parallel circuits implement the logic to:
10.CSM-4 Calibration Triggers, http://atlas.physics.lsa.umich.edu/docushare/dscgi/ds.py/View/ Collection-214
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The CSM Module Specifications
Autosense the individual TDC data streams and select the appropriate 1of 4 possible clock phase to sample the arriving data. Disable the TDC clock after sampling through the JTAG programming of the AMT-3. Reset to a quiescent state expecting a logic true start bit as the first data element from each TDC. After a start bit is received, begin assembly of the next 32-bits into a register. Compute and test the parity of the 32-bit string, setting an error flag if a fault is seen. Transfer the 32-bits to a holding register upon receipt of the stop bit, set a data ready flag indicating data present, and return to the quiescent state. Reset the data ready flag upon receipt of an acknowledge signal from the polling multiplexer.
The JTAG Interface
The JTAG signals connect to the CSM at a programmable PROM, and then to the FPGA, passing next to the GOL chip, and finally to the TTCrx. From there it returns to the FPGA on user handled pins. The JTAG chain is distributed to the mezzanine cards as defined by the enable bits for individual TDCs. Connection of the JTAG bus to the mezzanine cards is totally controlled in the FPGA code and can be modified as required. The Virtex-II series of Xilinx chips used for the CSM implementation support numerous I/O levels and standards which include LVDS and differential PECL. The chips powerup and initialize to an active TAP (JTAG) control for downloading configuration data. To provide external control of this bootstrap procedure, external circuitry must be able to force this first state for configuration to occur. The external JTAG can be provided by any commercial controller or by the DCS system. One means of forcing the first state will be to cycle the power. The TTCrx system could also generate a global reset. Careful evaluation of the startup operation must be done to insure that no frozen states exists other than through a true hardware device failure. This JTAG link will support the following functions: Initialization of the FPGA code within the Xilinx chips. Initialization of the parameters of the CSM and ASD/TDC cards Initialization of the parameters of the TTCrx. Controlling the run/reset/resynchronization of the CSM, TDC, and ASD
The Polling Multiplexer
The polling multiplexer is actually two polling multiplexers, one that scans for data ready flags from the 18 serial to parallel units and enters data found into 18 distinct FIFOs and a second that scans for FIFO data and if found places it into the time division sequence of the output optical transmitter. The polling rate of the first multiplexer is based on the 40MHz LHC clock and the rate of the second is 25MHz as set to guarantee to empty the FIFO faster than it can fill. The first multiplexer sequences through the steps: Reset to polling address to TDC 0 and to idle mode (not active). If in active mode, examine the data ready flag for the currently addressed TDC.
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The CSM Module Specifications
If data is available, send it to the FIFO for the addressed channel and reset the flag. Increment the TDC addressed and loop.
The second multiplexer has 21 steps. Eighteen of these steps are associated with the 18 FIFOs that hold data from the individual TDC. One, 18, defines the state when the spacer word is to be transmitted. The remaining two correspond to optical fiber idle words. The sequence through the steps: Reset the polling to address 18 and to idle mode (not active). If the polling multiplexer address is 18 output a TDM spacer word to the GOL chip. If the multiplexer address is 19 or 20 send a Gigabit Ethernet idle code. If the address is 0-17, test the FIFO for data in the addressed channel. If no data is present in the FIFO, send a TDC empty word. If data is available for FIFO (TDC) addressed, send an acknowledge to the FIFO to declare that the word has been taken and send the word to the GOL chip. Increment the polling address modulo 21 to advance to the next step.
The Fibre Sequencer
The GOL chip accepts 32-bit data words from the polling multiplexer and a 2-bit write control that: Sends a Gigabit Ethernet idle, if the 2-bit control is 00. The 32-bit data is ignored. Sends the 32-bit data presented to the GOL, if the control is 01. Sends an Extend code, if the control is 10. Sends a transmit error code, if the control is 11.
The DCS Analog Monitor
The 64-channel analog monitor is a direct copy of the 64-channel ELMB multiplexer designed by the DCS group and is assembled on the CSM to monitor the voltages and temperatures of the mezzanine cards and of the CSM itself. It is powered by the CSM 3.3 volts via a switched capacitor regulator that outputs 5 volts for the unit. Connections to the ELMB processor are optical isolated using the same components as used for the ELMB multiplexer that monitors chamber conditions. The location of the monitor on the CSM is chosen to minimize the interchange of signals between the CSM and the DCS circuitry. Only 5 opto-isolated signals are needed to provide JTAG to the CSM. In addition, a second set of 8 I/O lines from the ELMB processor will be extended to the CSM and opto-isolated. The extension provides for monitoring 64 differential signals or 128 connections. Of these 57 differential signals are anticipated, 3 from each mezzanine card and 3 from the CSM. Figure 5 on page 13 illustrates the relationship of the DCS to the CSM mounted portions of the DCS.
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Final CSM Design & Development at UoM
The CSM Module Specifications
FIGURE 5.
Relationship of the DCS elements on the CSM to the DCS System
DCS Motherboard CAN CAN Power signals ELMB Power
T sensors
64 Channel ADC CAN interface + micro controllers SPI
regulator
2 2
Credit Card B field meter
CAN driver
ELMB
57 Analog Channels CSM Power
5
CSM 64 Channel Mux/ADC SPI
8
CSM SPI Digital I/O
CSM JTAG
CSM Interconnects
Figure 6 on page 13 shows the layout of the CSM. An arrangement with all passive components on a motherboard whose role is to provide attachment to the 18 mezzanine cards via their 40-pin connectors.
FIGURE 6.
The Layout and Interconnection of the CSM
TTC Receiver CSM Multiplexer
Gigibit Ethernet to MROD ELMB JTAG & SPI Note: For the small chambers these headers are not needed and board can be shorter.
140 Pin Interconnect
ELMB Mux
Cross Plate
18 connectors (40 pin) Blue at near end, Red at far
Note: ELMB Mux is copy of 64 channel DCS mux
These signals must be routed to various subsections according to the list below. Mezzanine to CSM Motherboard x 18 max 8 JTAG (LVDS), 8 Data/CLK (LVDS) = 16 lines 8 Analog PWR, 8 Digital PWR, 6 Sense, 2 Calibration = 24 40 lines total
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The CSM Module Specifications
CSM to CSM Motherboard - 3 x 140 pins = 420 pins 8 JTAG (LVDS), 10 Data/CLK (LVDS) x 18 mezzanine cards = 324 lines 6 Sense, 8 Digital PWR, 8 ELMB PWR = 22 lines ELMB Mux to CSM Motherboard 6 Sense x 18 Mezzanine cards, 6 Sense x 1 CSM = 114 lines 5 JTAG I/O, 5 ELMB SPI, & 3 Spares = 13 lines
The Layout, seen as from above, is shown in Figure 7 on page 14. Note that for chambers not requiring more than 12 TDCs, that the motherboard can be reduced in size to the area required by the active components. This will entail the design of 2 different motherboards but affords the option of a short unit for small chambers. Need new picture of real CSM-4
GOL optical output
TTC optical input 5Volt power
Standoff
18 Mezzanine I/Os on 40-pin ribbons 9 on each side in 2 rows (near seen)
DCS connection for JTAG & 8-bit I/O communication Alternate JTAG via Jumpers Mounting plate
FIGURE 7.
The CSM-4 and Motherboard.
Pseudo-pair Mode
Pseudo pair mode is designed to take leading and trailing edges into pairs in the same format that was defined for the AMT-3. The implementation of this pair mode is straight forward in the pipelined operation of the CSM-4 with some exceptions that must be handled. Since the 32 deep input FIFOs of the CSM can fill if dataflow from the AMT-3 arrives at 80MHz, sensing of overflow conditions is required. The number of words present in these FIFOs is known so actions can be taken dependent on the remaining space in the 32 words. We propose two thresholds, the first set when AMT mask and trailing edge words are to be discarded and the second when AMT leading edge and error words are discarded. In addition, we propose to define two flags in TDC to indicate that words in the event have been discarded. Bit (24) flags the removal of trailing edge trailer (ID=0011 and T=0) and mask words (ID=0010) and Bit (25) flags the removal of leading edge (ID=0011 and T=1) and error words (ID=0110 or 0111). Four slots in the 32 word FIFOs will always be reserved for headers and trailers.
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The CSM Module Specifications
When operating in pseudo pair mode, the first of two consecutive leading edges will be deleted. This deletion will not be flagged as a data loss (no bit 25 flag will be set). Correspondingly, if the first edge to arrive is a trailing edge, it will not be sent and no data loss flag will be set. Also, if a leading edges is stored awaiting a trailing edge that does not arrive before the event trailer, the leading edge will be lost and no data deleted flag will be set in the event trailer. The above referenced thresholds for deletion will be in effect at all times. These thresholds are programmable via JTAG? In addition, a non-pair mode will be implemented where AMT data is not pair associated but output as it arrives. In this case all AMT data will be sent unmodified except for the overflow prevention based on the two thresholds just described. To convert the two words of ID=0011 (the first with a T=1 leading edge and the second with T=0 trailing edge) into a single word of ID=0100, the leading edge must be stored awaiting the arrival of the trailing edge. Some special cases deserve attention:
1. 2.
When there are 2 leading edges in sequence When a trailing edge is first seen within the match window of the AMT
3. Where a leading edge has been received but no trailing edge falls within the match window
The special case of two leading edges in sequence is thought to come from the narrow pulses that confuse the AMT-3 pair matching circuits. For the purposes of CSM-4 "pseudo pair" mode this case can be handled by simply ignoring the first leading edge. The data representing leading edges are stored and a flag set to indicate that the edge is present. If a second leading edge arrives without an intervening trailing edge, the second leading edge simply overwrites the first. This is the result desired since the first leading edge is thought to be due to a narrow pulse whose trailing edge is lost. A trailing edge arriving first implies that its leading edge was outside the match window and thus lost to digitization. Since the match window is designed to cover the full drift time expected for real hits from the detector, this trailing edge has no meaning for the current trigger and can be discarded. The "pseudo pair" mode logic of the CSM-4 will reset the leading edge flags for all channels when a TDC header (ID=1010) is seen. A trailing edge seen on a given channel before any leading edge from that channel is received and flagged will be discarded. A stored leading edge for which no trailing edge is seen before a TDC trailer (ID=1100) is seen, will also be discarded. This happens automatically in that the leading edge would be processed at the arrival of its corresponding trailing edge. Since all flags representing stored leading edges are cleared at the arrival of a TDC header no use of the leftover leading edge will be made. All word IDs will be passed without modification if the buffer space is available for the data type according to the thresholds set. Headers and trailers will be stored (pass into the buffer) if any buffer space is available. All word types will be stored (passed into the buffer) if the buffer word count is below its programmed discard threshold.
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The CSM Module Specifications
Pair mode as implemented in the CSM-4 should mimic that coded into the AMT. The AMT-3 provides 3 bits of width resolution, this same programming should be incorporated into the "Pseudo Pair" mode of the CSM-4. The 3 bits of width resolution determine which 8 bits of width data (calculated as 17 bits of trailing edge time minus leading edge time) are to be loaded into the output. The default precision (0) sends the lower 8 bits of the width (7-0) to the output. A width precision of 7 sends bits 14-7 of the width calculation to the output. To provide diagnostics on the CSM-4 preparation of "pseudo pair" mode data, two debug parameter fields of the CSM-4 are defined. One single bit (debug) selects a mode where the CSM-4 sends data for diagnostic checks of the "pseudo pair" mode itself. In this mode, the leading edge data is passed unchanged along with a modified form of pair data. The pair data in this case will include the calculated width but with the trailing edge time in place of the leading edge time as in normal pair mode. With this data, software can calculate the width for comparison to that provided by the CSM since the leading edge time has been sent along with modified pair word that contains the trailing edge time. Another debug option is provided where edges are sent rather than calculated pseudo pairs for events (or hits) satisfying a prescale count. The prescale is selected with 2 bits in the CSM-4 status register (ps). The scaling will be 816 (ps=0), 4016 (ps=1), 20016 (ps=2), and 1000 16(ps=3). The two diagnostic modes are not simultaneously useful. Prescale can be used with pair mode or non-pair mode. However, when use with non-pair mode all events are sent as edges so the prescaled event selection will not be unique in any way. Diagnostic "pseudo pair" mode where leading edges are sent and the pair word has trailing edge times should only be used with pair mode. In summary, selection between all edges (pair mode off) and pair mode (pair mode on) is controlled by one bit of the CSM-4 JTAG register. If operating in pair mode, a diagnostic mode (established by one bit in the JTAG setup) provides for leading edges to be sent followed by a modified pair mode output (width and trailing time). A 2-bit JTAG register field controls a prescale fraction of the EVID range for which event data is sent as edges rather than in pair mode. If the JTAG bit for pair mode selection is off, this prescale has no effect since all events will be sent as edges. Two additional JTAG register fields of 4-bits define the low and high thresholds for deletion of AMT error words and AMT data words. These 4 bit thresholds are prepended to a zero bit to match the buffer depth of 32. Hence a threshold programmed to 1100 (12) is interpreted as 11000 (24) when applied to the 32 words of the input FIFO.
Implementation details
The sequence of steps in non-pair mode are: Upon receipt of an AMT-3 TDC event header If the buffer has any free location, pass the header to the output stream and reset the data deleted flags. Upon receipt of a leading edge
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Final CSM Design & Development at UoM
The CSM Module Specifications
1. If the buffer word count is below high threshold, pass the leading edge to the output stream. 2.
If the buffer word count is above the high threshold, discard the data and set high threshold data deleted flag. Upon receipt of a trailing edge
1. If the buffer word count is below the low threshold, pass the trailing edge to the output stream. 2. If the buffer count is above low threshold, discard the word and set the low threshold data deleted flag. Upon receipt of AMT-3 TDC trailer
Pass the AMT trailer and the state of the high and low data deleted flags. The sequence of steps in pair mode for non-debug operation are: Upon receipt of an AMT-3 event header,
1. 2. 3.
Reset the leading edge found flags (24). Reset the word count to 1 for this AMT.
Pass the TDC header and reset the data deleted flags. Upon receipt of a leading edge, Store the leading edge in RAM indexed by10-bits (AMT+channel). Set leading edge found flag (1-bit) for the particular10-bit (AMT+channel). Upon receipt of a trailing edge, If no leading edge is stored, discard the trailing edge.
1. 2.
1. 2.
If a leading edge is stored and the buffer word count is above high threshold, set the high threshold data deleted flag, discard the trailing edge, andreset the leading edge stored flag.
3. If a leading edge is stored and the buffer word count is below the high threshold, calculate the pair mode data,increment the word count for this TDC-channel, reset the leading edge stored flag, and pass the pair data to the output. Upon receipt of AMT-3 event trailer 1. 2. 3.
Clear leading edge flag Count event trailer for this AMT
Forward event trailer to RAM with stored count Upon receipt of other words, If the buffer word count for this word type is above threshold, discard the word.
1.
2. If the buffer word count for this word type is below threshold, pass the word to the output, and increment the word count for this TDC-channel.
The sequence of steps in pair mode with prescale set If event number masked with modulo prescale = 0
1.
Run as non-pair mode above
Run as pair mode above
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The CSM Module Specifications
The sequence of steps in pair mode with debug bit set Upon receipt of an AMT-3 event header Reset the leading edge found flags (24)
2.
Reset the word count to 1 for this AMT
3. Pass the event header, data deleted, and error flags to RAM for polling multiplexer, reset the error and data deleted flag, and count the word Upon receipt of a leading edge 1. 2.
Store in RAM indexed (10-bits) by AMT-channel Set leading edge flag (1-bit) for the 10-bit AMT-channel
3. If the buffer word count is below high threshold, pass the leading edge, data, and error deleted flags to RAM for polling multiplexer, reset the data and error deleted flags, and increment the count of word sent 4. If the buffer word count is above high threshold, discard the data and set data deleted flag Upon receipt of a trailing edge
If no leading edge is stored "Discard trailing edge (i.e. do not forward) If a leading edge is stored If buffer word count is above high threshold
1.
set data deleted flag If buffer word count is below high threshold Calculate the pair mode data using trailing edge time Count word forwarded for this AMT Clear leading edge flag
2. 3. 4.
5. Forward data and delete flags to RAM for polling multiplexer and reset delete flags Upon receipt of AMT-3 event trailer 1. 2.
Clear leading edge flags Count event trailer for this AMT
3. Forward event trailer , data deleted, and error flags to RAM with prepared word count
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Final CSM Design & Development at UoM
The CSM-4 Prototype Development
THE CSM-4 PROTOTYPE DEVELOPMENT
Design Elements
The CSM-4 has as it goal the rapid design of a module more closely aligned with the final CSM than is the CSM-0. It presumes an early version of the MROD and the use of fiber connections to the trigger, timing, and control and to the data acquisition flow. The fiber interconnect more realistically represents the clock noise, data noise, and grounding environment of the final configuration. The only justification for the intermediate design of a second prototype is expediency. The goal is to have a fiber connected design that can reside on chamber using the same interconnect motherboard, TTC system, and the opto-isolated JTAG connection anticipated in the final CSM. The items to be included in the CSM but not present in the CSM-4, are the analog multiplexer for voltage and temperature sensing, and the final TTC system with calibration programming. The connections to do calibration will be in place in the CSM resident FPGA, but perhaps not from the TTCvi programming. The TTC system is described on the CERN web pages at CERN11 where the TTCvi Mark I is described. The specifics of the CSM-4 are: The main multiplexing task of the CSM-4 has been compressed from 4 FPGAs into one using a scheme of clock phase sampling to remove the need for many independent clock networks, using a large fine pitch ball grid array chip, and using a LVDS compatible FPGA from Xilinx, the XC2V1000FPBG456. Prototype testing of the optical fiber output to the MROD will be done using the CERN GOL chip and the Infineon V23818-K305-L57. The final design will likely use a simple laser diode in place of the transceiver since the input channel is unused in the CSM to MROD link. The CSM-4 requires clocking and event triggering. For the CSM-4 design the Trigger, Timing, and Control will be based on the CERN developed TTC system. Our transition from the internal simulation of the trigger and timing to the externally generated functions implies and integration of the CERN chip into the module and the software integration of the TTCvi module into our environment. We plan to use the Mark I version of the TTCvi initially and switch to the Mark II version in 2003. The initialization of the ASD/TDC mezzanine cards is done via JTAG protocol which in the case of the CSM-0 is built into the VME functions of the CSM-0 module. In the CSM-4 no VME connections is available. The CSM-0 will use an optoisolated JTAG function as will the final CSM. However, the final CSM will have a DCS connection and a CAN bus interface to provide the programming for the JTAG. To make progress toward this final goal, the opto-isolated JTAG will be driven from a commercial module. The CSM will interconnect to the ASD/TDC modules via shielded ribbon cables that leave the Faraday cages and converge at the spacer plate of the MDT. At this location they will attach to a passive interconnect on which the active CSM will reside. To make use of the current CSM-0 with the new interconnect board, a MiniAdapter board has been constructed with the same circuit design as the adapter currently in use with the CSM-0, but designed to attach to the passive interconnect. Following use with the CSM-0, a simple replacement of this new adapter with the CSM-4 will convert a chamber from CSM-0 readout to the MROD readout via the CSM-4.
11. TTC system web pages, http://ttc.web.cern.ch/TTC/intro.html
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JTAG Programming
The CSM-4 will not contain the analog multiplexer nor will it interact with the DCS system initially. The CSM-4 will not contain any Single Bit Upset detection or correction code. Since this code is firmware, it is anticipated that work on this code will follow the certification of the design in the first half of 2003.
JTAG PROGRAMMING
CSM-4 JTAG
The CSM-4 has a JTAG string which is a composite of several bit strings for the TTCrx register initial values, the CSM module RW parameters, the AMT RO parity error flags, the TTC RO status, and the CSM module RO status. These strings are defined in the CSM VerilogHDL code and can be modified rather easily. The current sizes of the JTAG elements are represented in Table 6 on page 20 along with the overall order of these strings in the JTAG sequence.
TABLE 6.
JTAG String Lengths & Position
# bits
80 72 160 18 28
String Name TTCrx_init_len CSM_parm_len TTC_readback_len AMT_parity_err_len CSM_status_len
Bit posn
278 206 46 28 0
The entire JTAG string can be read or written. Individual sections can also be read and written. The subsections that can be separately accessed are defined in Table 7 on page 20. The individual subsections are accessed with different values of the 6-bit instruction register. In this table the designation RW implies the register is loaded with the outgoing string and the RO designation implies that the register is read back but that the outgoing JTAG string is ignored. Of course, for the read only bits in the full register, the outgoing JTAG string is always ignored.
TABLE 7.
CSM JTAG Instructions
Length 358 358 160 18 28 18 Read-Write Instruction
Register Subsection
FULL JTAG String FULL JTAG String
TTC Readback AMT Parity Errors CSM Status Flags AMT Phase Sampling Errors
RW RO RO RO RO RO
000011 110001 110010 110011 110100 110101
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JTAG Programming
TABLE 7.
CSM JTAG Instructions
Length 152 152 72 72 32 206 Read-Write Instruction
Register Subsection All Configuration Bits All Configuration Bits CSM Parameters CSM Parameters CSM Version Date Read only Bits
RO RW RO RW RO RO
110110 110111 111000 111001 111010 111011
The subsections of the JTAG string are shown in Figure 8 on page 21. 80 TTCinit
RW bits
72 CSM parm
160 TTC readback
18 AMT parity
RO bits
28 CSM status
FIGURE 8.
Position of Control and Status Strings in JTAG
If the full JTAG string is sent, the order must be obeyed with the CSM status bits exiting the CSM first and new values sent low order bit first. The individual bit positions for the subsections are shown in Table 6 on page 20 where the length of the read-write section is the sum of the first two, 152, and the length of the read-only section is the sum of the last three, 206. The TTCrx string is defined in the TTCrx manual12. In the CSM, this string is loaded via JTAG and presented to the TTCrx chip following a reset signal. This reset initiates the timing sequence for loading the TTCrx from PROM with the FPGA taking the role of the PROM. The CSM parameter string of 72 bits provides RW control for the CSM, the GOL, and TTCrx as shown in Table 8 on page 21. The CSM status bits are RO and represent the version number of the CSM code, the state of various DLL lock lines, and a few error flags.
TABLE 8.
CSM JTAG Control Bit Definitions
Field Bit posn
0 18 19 20 27 28
Length
18 1 1 7 1 3
TDC enable low bit Include mezzanine cards in JTAG flags low CSM enable trigger bit Mezzanine command delay pipe length low 80mhz operation bit Pair width resolution low
12.Timing receiver ASIC (TTCrx) Reference Manual, http://ttc.web.cern.ch/TTC/intro.html
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JTAG Programming
TABLE 8.
CSM JTAG Control Bit Definitions
Field Bit posn
31 32 33 34 35 36 37 38 39 40 41 42 43 44 49 50 51 52 56 57 58 59 60 61 64 68
Length
1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 4 1 1 1 1 1 3 4 4
CSM make pairs bit Pair debug bit Spare bit 0 Suppress idle cycle bit (TDM only) Include sync status bit (TDM only) GOLdiff bit GOL ld0 bit GOL ld1 bit GOL pll bit GOL laser bit GOL negative edge selection bit GOL mode selection bit Enable GOL tdi bit MaxAMTconnect low Spare bit 1 Enable TTC tdi bit TTC use prom bit CSM next state low CSM command bit CSM BCID no match bit (event builder only) CSM EVID no match bit (event builder only) CSM send all AMT types bit (event builder only) CSM no header or trailers bit (event builder only) Pair prescale mode low Ram trailing edge threshold low Ram leading edge threshold low
The TTCrx readback bits hold the contents of the 20 I2C addressed 8-bit registers of the TTCrx. Two fpga build versions are possible. In the default version, one I2C register is read every 400ms, covering all 20 registers. In the second version, only the first ten regTABLE 9.
TTCrx Readback Register
Field bit posn
0 80
TTCrx registers 9 to 0 TTCrx registers 19 to 10 (I2C access only)
isters are available. These 10 registers are accessed passively via the ERDump and CRDump commands of the TTCrx. (See Table 9 on page 22) The CSM status register
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Final CSM Design & Development at UoM
JTAG Programming
bits reflect this difference, with the first column describing the ERDump/CRDump situation, and the second describing the I2C situation. (See Table 10 on page 17) The ERDump/CRDump version will eventually be phased out. The AMT parity error bits are cleared when data acquisition is enabled and accumulated from the parity error calculation for each data word separately for each of the AMT chips (each mezzanine card). A stop and restart of the data acquisition begins another set of 18 accumulated OR bits.
TABLE 10.
AMT Parity Error Flags
Field bit posn
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
TDC 0 Flag TDC 1 Flag TDC 2 Flag TDC 3 Flag TDC 4 Flag TDC 5 Flag TDC 6 Flag TDC 7 Flag TDC 8 Flag TDC 9 Flag TDC 10 Flag TDC 11 Flag TDC 12 Flag TDC 13 Flag TDC 14 Flag TDC 15 Flag TDC 16 Flag TDC 17 Flag
The CSM status register bit definitions are indicated in Table 11 on page 23 using the same convention as provided in the parameters file. In this case the bits are RO with the data sent via the JTAG output stream being ignored.
TABLE 11.
CSM Status Register Bit Definitions
Field Position
0 12 13 14 15 16
Length
12 1 1 1 1 1
CSM version number low GOL ready bit TTC ready bit LHC clock locked bit XMT internal clock lock bit (FPGA) XMT external clock lock bit (GOL)
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JTAG Programming
TABLE 11.
CSM Status Register Bit Definitions
Field Position
17 18 19 23 24 25 26 27
Length
1 1 4 1 1 1 1 1
Unused OR (for fooling synthesizer) TTC prom load error flag CSM state low Sample phase error bit I2C Operation Failure TTC I2C compare error TTC dump compare error bit CSM error bit
If the Suppress Idle Cycle bit is turned on in the CSM JTAG Control Bit sequence, then any 21 word ...