ADC0820
22 Pages

ADC0820

Course: ENGR 1160, Fall 2009

School: Pittsburgh

Word Count: 4671

Rating:

Document Preview

ADC0820 8-Bit High Speed P Compatible A/D Converter with Track/Hold Function June 1999 ADC0820 8-Bit High Speed P Compatible A/D Converter with Track/Hold Function General Description By using a half-flash conversion technique, the 8-bit ADC0820 CMOS A/D offers a 1.5 s conversion time and dissipates only 75 mW of power. The half-flash technique consists of 32 comparators, a most significant 4-bit ADC and a least...

Unformatted Document Excerpt
Coursehero >> Pennsylvania >> Pittsburgh >> ENGR 1160

Course Hero has millions of student submitted documents similar to the one
below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.

Course Hero has millions of student submitted documents similar to the one below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.

8-Bit ADC0820 High Speed P Compatible A/D Converter with Track/Hold Function June 1999 ADC0820 8-Bit High Speed P Compatible A/D Converter with Track/Hold Function General Description By using a half-flash conversion technique, the 8-bit ADC0820 CMOS A/D offers a 1.5 s conversion time and dissipates only 75 mW of power. The half-flash technique consists of 32 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC. The input to the ADC0820 is tracked and held by the input sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV/s. For ease of interface to microprocessors, the ADC0820 has been designed to appear as a memory location or I/O port without the need for external interfacing logic. Features n n n n n n n n n 8 Bits 2.5 s Max (RD Mode) n n n n n n Built-in track-and-hold function No missing codes No external clocking Single supply 5 VDC Easy interface to all microprocessors, or operates stand-alone Latched STRI-STATE output Logic inputs and outputs meet both MOS and T2L voltage level specifications Operates ratiometrically or with any reference value equal to or less than VCC 0V to 5V analog input voltage range with single 5V supply No zero or full-scale adjust required Overflow output available for cascading 0.3" standard width 20-pin DIP 20-pin molded chip carrier package 20-pin small outline package 20-pin shrink small outline package (SSOP) Key Specifications j Resolution j Conversion Time j Low Power j Total Unadjusted 1.5 s Max (WR-RD Mode) 75 mW Max Error 12 LSB and 1 LSB Connection and Functional Diagrams Dual-In-Line, Small Outline and SSOP Packages Molded Chip Carrier Package DS005501-1 DS005501-33 Top View 2001 National Semiconductor Corporation DS005501 www.national.com ADC0820 Connection and Functional Diagrams (Continued) DS005501-2 FIGURE 1. Ordering Information Part Number ADC0820BCV ADC0820BCWM ADC0820BCN ADC0820CCJ ADC0820CCWM ADC0820CIWM ADC0820CCN Total Unadjusted Error V20A Molded Chip Carrier Package Temperature Range 0C to +70C 0C to +70C 0C to +70C 40C to +85C 0C to +70C 40C to +85C 0C to +70C M20B Wide Body Small Outline N20A Molded DIP J20A Cerdip M20B Wide Body Small Outline M20B Wide Body Small Outline N20A Molded DIP 12 LSB 1 LSB www.national.com 2 ADC0820 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Logic Control Inputs Voltage at Other Inputs and Output Storage Temperature Range Package Dissipation at TA = 25C Input Current at Any Pin (Note 5) Package Input Current (Note 5) ESD Susceptability (Note 9) Lead Temp. (Soldering, 10 sec.) Dual-In-Line Package (plastic) 10V 0.2V to VCC +0.2V 0.2V to VCC +0.2V 65C to +150C 875 mW 1 mA 4 mA 1200V 260C Dual-In-Line Package (ceramic) Surface Mount Package Vapor Phase (60 sec.) Infrared (15 sec.) 300C 215C 220C Operating Ratings (Notes 1, 2) TMINTATMAX 40CTA+85C 40CTA+85C 0CTA70C 0CTA70C 0CTA70C 4.5V to 8V Temperature Range ADC0820CCJ ADC0820CIWM ADC0820BCN, ADC0820CCN ADC0820BCV ADC0820BCWM, ADC0820CCWM VCC Range Converter Characteristics The following specifications apply for RD mode (pin 7=0), VCC =5V, VREF(+)=5V,and VREF()=GND unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA =Tj =25C. Parameter Conditions ADC0820CCJ Typ (Note 6) Resolution Total Unadjusted Error (Note 3) Minimum Reference Resistance Maximum Reference Resistance Maximum VREF(+) Input Voltage Minimum VREF() Input Voltage Minimum VREF(+) Input Voltage Maximum VREF() Input Voltage Maximum VIN Input Voltage Minimum VIN Input Voltage Maximum Analog Input Leakage Current Power Supply Sensitivity CS =VCC VIN =VCC VIN =GND VCC =5V 5% 3 3 0.3 0.3 3 3 A A LSB GND0.1 GND0.1 GND0.1 V VCC+0.1 VCC+0.1 VCC+0.1 V VREF(+) VREF(+) VREF(+) V VREF() VREF() VREF() V GND GND GND V VCC VCC VCC V 2.3 6 2.3 5.3 6 k ADC0820BCN, BCWM ADC0820CCJ ADC0820CCN, CCWM, CIWM, ADC0820CCMSA 2.3 1.00 2.3 Tested Limit (Note 7) 8 Design Limit (Note 8) ADC0820BCN, ADC0820CCN ADC0820BCV, ADC0820BCWM ADC0820CCWM, ADC0820CIWM Typ (Note 6) Tested Limit (Note 7) 8 Design Limit (Note 8) 8 Bits LSB LSB LSB LSB k Limit Units 1 2 1 1 1 1.2 1 2 1 1 1/16 14 1/16 1 4 1 4 3 www.national.com ADC0820 DC Electrical Characteristics The following specifications apply for VCC =5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA =TJ =25C. Parameter Conditions ADC0820CCJ Typ (Note 6) VIN(1), Logical 1 Input Voltage VIN(0), Logical 0 Input Voltage IIN(1), Logical 1 Input Current IIN(0), Logical 0 Input Current VOUT(1), Logical 1 Output Voltage VIN(1) =5V; WR VIN(1) =5V; Mode VIN(0) =0V; CS , RD , WR , Mode VCC =4.75V, IOUT =360 A; DB0DB7, OFL , INT VCC =4.75V, IOUT =10 A; DB0DB7, OFL , INT VOUT(0), Logical 0 Output Voltage IOUT, TRI-STATE Output Current ISOURCE, Output Source Current ISINK, Output Sink Current ICC, Supply Current VCC =4.75V, IOUT =1.6 mA; DB0DB7, OFL , INT , RDY VOUT =5V; DB0DB7, RDY VOUT =0V; DB0DB7, RDY VOUT =0V; DB0DB7, OFL INT VOUT =5V; DB0DB7, OFL , INT , RDY CS =WR =RD =0 7.5 15 7.5 13 15 mA 0.1 0.1 12 9 14 3 3 6 4.0 7 0.1 0.1 12 9 14 0.3 0.3 7.2 5.3 8.4 3 3 6 4.0 7 A A mA mA mA 0.4 0.34 0.4 V 4.5 4.6 4.5 V 2.4 2.8 2.4 V VCC =4.75V VCC =5.25V CS , WR , RD Mode CS , WR , RD Mode VIN(1) =5V; CS , RD 0.005 0.1 50 0.005 Tested Limit (Note 7) 2.0 3.5 0.8 1.5 1 3 200 1 0.005 0.1 50 0.005 0.3 170 Design Limit (Note 8) ADC0820BCN, ADC0820CCN ADC0820BCV, ADC0820BCWM ADC0820CCWM, ADC0820CIWM Typ (Note 6) Tested Limit (Note 7) 2.0 3.5 0.8 1.5 Design Limit (Note 8) 2.0 3.5 0.8 1.5 1 3 200 1 V V V V A A A A Limit Units AC Electrical Characteristics The following specifications apply for VCC =5V, tr =tf =20 ns, VREF(+)=5V, VREF()=0V and TA =25C unless otherwise specified. Typ Parameter tCRD, Conversion Time for RD Mode tACC0, Access Time (Delay from Falling Edge of RD to Output Valid) tCWR-RD, Conversion Time for WR-RD Mode tWR, Write Time tRD, Read Time Min Max Min Pin 7 = VCC; tWR = 600 ns, tRD =600 ns; Figures 3, 4 Pin 7 = VCC; Figures 3, 4 (Note 4) See Graph Pin 7 = VCC; Figures 3, 4 (Note 4) See Graph tACC1, Access Time (Delay from Falling Edge of RD to Output Valid) Pin 7 = VCC, tRD < tI; Figure 3 CL =15 pF CL =100 pF 190 210 280 320 ns ns 50 600 600 ns s ns 1.52 s Conditions Pin 7 = 0, Figure 2 Pin 7 = 0, Figure 2 (Note 6) 1.6 tCRD+20 Tested Limit (Note 7) Design Limit (Note 8) 2.5 tCRD+50 s ns Units www.national.com 4 ADC0820 AC Electrical Characteristics (Continued) The following specifications apply for VCC =5V, tr =tf =20 ns, VREF(+)=5V, VREF()=0V and TA =25C unless otherwise specified. Typ Parameter tACC2, Access Time (Delay from Falling Edge of RD to Output Valid) tACC3, Access Time (Delay from Rising Edge of RDY to Output Valid) tI, Internal Comparison Time t1H, t0H, TRI-STATE Control (Delay from Rising Edge of RD to Hi-Z State) tINTL, Delay from Rising Edge of WR to Falling Edge of INT tINTH, Delay from Rising Edge of RD to Rising Edge of INT tINTHWR, Delay from Rising Edge of WR to Rising Edge of INT tRDY, Delay from CS to RDY tID, Delay from INT to Output Valid tRI, Delay from RD to INT tP, Delay from End of Conversion to Next Conversion Slew Rate, Tracking CVIN, Analog Input Capacitance COUT, Logic Output Capacitance CIN, Logic Input Capacitance Pin 7 = VCC, CL = 50 pF tRD > tI; Figure 4 tRD < tI; Figure 3 tRD+200 125 175 50 20 200 tI tRD+290 225 270 100 50 290 500 0.1 45 5 5 ns ns ns ns ns ns ns ns V/s pF pF pF Conditions Pin 7 = VCC, tRD > tI; Figure 4 CL =15 pF CL =100 pF RPULLUP = 1k and CL = 15 pF 70 90 30 120 150 ns ns ns (Note 6) Tested Limit (Note 7) Design Limit (Note 8) Units Pin 7=VCC; Figures 4, 5 CL =50 pF RL =1k, CL =10 pF 800 100 1300 200 ns ns Figures 2, 3, 4 CL =50 pFc Figure 5, CL =50 pF Figure 2, CL =50 pF, Pin 7 =0 Figure 5 Pin 7=VCC, tRD < tI Figure 3 Figures 2, 3, 4, 5 (Note 4) See Graph Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified. Note 3: Total unadjusted error includes offset, full-scale, and linearity errors. Note 4: Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. See Accuracy vs tWR and Accuracy vs tRD graphs. Note 5: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < Vor VIN > V+) the absolute value of current at that pin should be limited to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four. Note 6: Typicals are at 25C and represent most likely parametric norm. Note 7: Tested limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level). Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 9: Human body model, 100 pF discharaged through a 1.5 k resistor. 5 www.national.com ADC0820 TRI-STATE Test Circuits and Waveforms t1H DS005501-4 DS005501-3 tr =20 ns t0H DS005501-6 DS005501-5 tr =20 ns Timing Diagrams DS005501-7 Note: On power-up the state of INT can be high or low. FIGURE 2. RD Mode (Pin 7 is Low) www.national.com 6 ADC0820 Timing Diagrams (Continued) DS005501-8 FIGURE 3. WR-RD Mode (Pin 7 is High and tRD < tI) DS005501-9 FIGURE 4. WR-RD Mode (Pin 7 is High and tRD > tI) DS005501-10 FIGURE 5. WR-RD Mode (Pin 7 is High) Stand-Alone Operation 7 www.national.com ADC0820 Typical Performance Characteristics Logic Input Threshold Voltage vs Supply Voltage Conversion Time (RD Mode) vs Temperature Power Supply Current vs Temperature (not including reference ladder) DS005501-34 DS005501-35 DS005501-36 Accuracy vs tWR Accuracy vs tRD Accuracy vs tp DS005501-37 DS005501-38 DS005501-39 Accuracy vs VREF [VREF=VREF(+)-VREF(-)] tI, Internal Time Delay vs Temperature Output Current vs Temperature DS005501-40 DS005501-42 DS005501-41 www.national.com 8 ADC0820 Description of Pin Functions Pin 1 2 3 4 5 6 Name VIN DB0 DB1 DB2 DB3 WR /RDY Function Analog input; range =GNDVINVCC TRI-STATE data output bit 0 (LSB) TRI-STATE data output bit 1 TRI-STATE data output bit 2 TRI-STATE data output bit 3 WR-RD Mode WR: With CS low, the conversion is started on the falling edge of WR. Approximately 800 ns (the preset internal time out, tI) after the WR rising edge, the result of the conversion will be strobed into the output latch, provided that RD does not occur prior to this time out (see Figures 3, 4 ). RD Mode RDY: This is an open drain output (no internal pull-up device). RDY will go low after the falling edge of CS; RDY will go TRI-STATE when the result of the conversion is strobed into the output latch. It is used to simplify the interface to a microprocessor system (see Figure 2 ). 7 Mode Mode: Mode selection input it is internally tied to GND through a 50 A current source. RD Mode: When mode is low WR-RD Mode: When mode is high 8 RD WR-RD Mode With CS low, the TRI-STATE data outputs (DB0-DB7) will be activated when RD goes low (see Figure 5 ). RD can also be used to increase the speed of the converter by reading data prior to the preset internal time out (tI, 800 ns). If this is done, the data result transferred to output latch is latched after the falling edge of the RD (see Figures 3, 4 ). RD Mode With CS low, the conversion will start with RD going low, also RD will enable the TRI-STATE data outputs at the completion of the conversion. RDY going TRI-STATE and INT going low indicates the completion of the conversion (see Figure 2 ). Pin 9 Name INT WR-RD Mode Function INT going low indicates that the conversion is completed and the data result is in the output latch. INT will go low, 800 ns (the preset internal time out, tI) after the rising edge of WR (see Figure 4 ); or INT will go low after the falling edge of RD , if RD goes low prior to the 800 ns time out (see Figure 3). INT is reset by the rising edge of RD or CS (see Figures 3, 4 ). RD Mode INT going low indicates that the conversion is completed and the data result is in the output latch. INT is reset by the rising edge of RD or CS (see Figure 2 ). 10 11 12 13 14 15 16 17 18 GND VREF() VREF(+) CS DB4 DB5 DB6 DB7 OFL Ground The bottom of resistor ladder, voltage range: GNDVREF()VREF(+) (Note 5) The top of resistor ladder, voltage range: VREF()VREF(+)VCC (Note 5) CS must be low in order for the RD or WR to be recognized by the converter. TRI-STATE data output bit 4 TRI-STATE data output bit 5 TRI-STATE data output bit 6 TRI-STATE data output bit 7 (MSB) Overflow output If the analog input is higher than the VREF(+), OFL will be low at the end of conversion. It can be used to cascade 2 or more devices to have more resolution (9, 10-bit). This output is always active and does not go into TRI-STATE as DB0DB7 do. No connection Power supply voltage 19 20 NC VCC 1.0 Functional Description 1.1 GENERAL OPERATION The ADC0820 uses two 4-bit flash A/D converters to make an 8-bit measurement (Figure 1 ). Each flash ADC is made up of 15 comparators which compare the unknown input to a reference ladder to get a 4-bit result. To take a full 8-bit reading, one flash conversion is done to provide the 4 most significant data bits (via the MS flash ADC). Driven by the 4 9 MSBs, an internal DAC recreates an analog approximation of the input voltage. This analog signal is then subtracted from the input, and the difference voltage is converted by a second 4-bit flash ADC (the LS ADC), providing the 4 least significant bits of the output data word. The internal DAC is actually a subsection of the MS flash converter. This is accomplished by using the same resistor www.national.com ADC0820 1.0 Functional Description (Continued) ladder for the A/D as well as for generating the DAC signal. The DAC output is actually the tap on the resistor ladder which most closely approximates the analog input. In addition, the sampled-data comparators used in the ADC0820 provide the ability to compare the magnitudes of several analog signals simultaneously, without using input summing amplifiers. This is especially useful in the LS flash ADC, where the signal to be converted is an analog 1.2 difference. THE SAMPLED-DATA COMPARATOR Each comparator in the ADC0820 consists of a CMOS inverter with a capacitively coupled input (Figures 6, 7 ). Analog switches connect the two comparator inputs to the input capacitor (C) and also connect the inverters input and output. This device in effect now has one differential input pair. A comparison requires two cycles, one for zeroing the comparator, and another for making the comparison. In the first cycle, one input switch and the inverters feedback switch (Figure 6 ) are closed. In this interval, C is charged to the connected input (V1) less the inverters bias voltage (VB, approximately 1.2V). In the second cycle (Figure 7 ), these two switches are opened and the other (V2) inputs switch is closed. The input capacitor now subtracts its stored voltage from the second input and the difference is amplified by the inverters open loop gain. The inverters input (VB') becomes then made by connecting the second input on each capacitor and opening all of the other switches (S switches). The change in voltage at the inverters input, as a result of the change in charge on each input capacitor, will now depend on both input signal differences. DS005501-12 VO = VB V on C = V1VB CS = stray input node capacitor VB = inverter input bias voltage Zeroing Phase FIGURE 6. Sampled-Data Comparator DS005501-13 and the output will go high or low depending on the sign of VB'VB. The actual circuitry used in the ADC0820 is a simple but important expansion of the basic comparator described above. By adding a second capacitor and another set of switches to the input (Figure 8 ), the scheme can be expanded to make dual differential comparisons. In this circuit, the feedback switch and one input switch on each capacitor (Z switches) are closed in the zeroing cycle. A comparison is Compare Phase FIGURE 7. Sampled-Data Comparator DS005501-45 DS005501-14 FIGURE 8. ADC0820 Comparator (from MS Flash ADC) 1.3 ARCHITECTURE In the ADC0820, one bank of 15 comparators is used in each 4-bit flash A/D converter (Figure 12 ). The MS (most significant) flash ADC also has one additional comparator to detect input overrange. These two sets of comparators operate alternately, with one group in its zeroing cycle while the other is comparing. When a typical conversion is started, the WR line is brought low. At this instant the MS comparators go from zeroing to comparison mode (Figure 11 ). When WR is returned high www.national.com 10 after at least 600 ns, the output from the first set of comparators (the first flash) is decoded and latched. At this point the two 4-bit converters change modes and the LS (least significant) flash ADC enters its compare cycle. No less than 600 ns later, the RD line may be pulled low to latch the lower 4 data bits and finish the 8-bit conversion. When RD goes low, the flash A/Ds change state once again in preparation for the next conversion. Figure 11 also outlines how the converters interface timing relates to its analog input (VIN). In WR-RD mode, VIN is ADC0820 1.0 Functional Description (Continued) measured while WR is low. In RD mode, sampling occurs during the first 800 ns of RD. Because of the input connections to the ADC0820s LS and MS comparators, the converter has the ability to sample VIN at one instant (Section 2.4), despite the fact that two separate 4-bit conversions are being done. More specifically, when WR is low the MS flash is in compare mode (connected to VIN), and the LS flash is in zero mode (also connected to VIN). Therefore both flash ADCs sample VIN at the same time. 1.4 DIGITAL INTERFACE The ADC0820 has two basic interface modes which are selected by strapping the MODE pin high or low. RD Mode With the MODE pin grounded, the converter is set to Read mode. In this configuration, a complete conversion is done by pulling RD low until output data appears. An INT line is provided which goes low at the end of the conversion as well as a RDY output which can be used to signal a processor that the converter is busy or can also serve as a system Transfer Acknowledge signal. RD Mode (Pin 7 is Low) go low 800 ns after WRs rising edge. However, if a shorter conversion time is desired, the processor need not wait for INT and can exercise a read after only 600 ns (Figure 9 ). If this is done, INT will immediately go low and data will appear at the outputs. DS005501-17 FIGURE 9. WR-RD Mode (Pin 7 is High and tRD < tI) DS005501-18 FIGURE 10. WR-RD Mode (Pin 7 is High and tRD > tI) Stand-Alone For stand-alone operation in WR-RD mode, CS and RD can be tied low and a conversion can be started with WR. Data will be valid approximately 800 ns following WRs rising edge. WR-RD Mode (Pin 7 is High) Stand-Alone Operation DS005501-16 When in RD mode, the comparator phases are internally triggered. At the falling edge of RD, the MS flash converter goes from zero to compare mode and the LS ADCs comparators enter their zero cycle. After 800 ns, data from the MS flash is latched and the LS flash ADC enters compare mode. Following another 800 ns, the lower 4 bits are recovered. WR then RD Mode With the MODE pin tied high, the A/D will be set up for the WR-RD mode. Here, a conversion is started with the WR input; however, there are two options for reading the output data which relate to interface timing. If an interrupt driven scheme is desired, the user can wait for INT to go low before reading the conversion result (Figure 10 ). INT will typically DS005501-19 11 www.national.com ADC0820 1.0 Functional Description (Continued) DS005501-20 Note: MS means most significant LS means least significant FIGURE 11. Operating Sequence (WR-RD Mode) OTHER INTERFACE CONSIDERATIONS In order to maintain conversion accuracy, WR has a maximum width spec of 50 s. When the MS flash ADCs sampled-data comparators (Section 1.2) are in comparison mode (WR is low), the input capacitors (C, Figure 8 ) must hold their charge. Switch leakage and inverter bias current can cause errors if the comparator is left in this phase for too long. Since the MS flash ADC enters its zeroing phase at the end of a conversion (Section 1.3), a new conversion cannot be started until this phase is complete. The minimum spec for this time (tP, Figures 2, 3, 4, 5 ) is 500 ns. www.national.com 12 ADC0820 Detailed Block Diagram DS005501-15 FIGURE 12. 13 www.national.com ADC0820 2.0 Analog Considerations 2.1 REFERENCE AND INPUT The two VREF inputs of the ADC0820 are fully differential and define the zero to full-scale input range of the A to D converter. This allows the designer to easily vary the span of the analog input since this range will be equivalent to the voltage difference between VIN(+) and VIN(). By reducing VREF(VREF =VREF(+)VREF()) to less than 5V, the sensitivity of the converter can be increased (i.e., if VREF =2V then 1 LSB=7.8 mV). The input/reference arrangement also facilitates ratiometric operation and in many cases the chip power supply can be used for transducer power as well as the VREF source. This reference flexibility lets the input span not only be varied but also offset from zero. The voltage at VREF() sets the input level which produces a digital output of all zeroes. Though VIN is not itself differential, the reference design affords nearly differential-input capability for most measurement applications. Figure 13 shows some of the configurations that are possible. 2.2 INPUT CURRENT Due to the unique conversion techniques employed by the ADC0820, the analog input behaves somewhat differently than in conventional devices. The A/Ds sampled-data comparators take varying amounts of input current depending on which cycle the conversion is in. External Reference 2.5V Full-Scale The equivalent input circuit of the ADC0820 is shown in Figure 14. When a conversion starts (WR low, WR-RD mode), all input switches close, connecting VIN to thirty-one 1 pF capacitors. Although the two 4-bit flash circuits are not both in their compare cycle at the same time, VIN still sees all input capacitors at once. This is because the MS flash converter is connected to the input during its compare interval and the LS flash is connected to the input during its zeroing phase (Section 1.3). In other words, the LS ADC uses VIN as its zero-phase input. The input capacitors must charge to the input voltage through the on resistance of the analog switches (about 5 k to 10 k). In addition, about 12 pF of input stray capacitance must also be charged. For large source resistances, the analog input can be modeled as an RC network as shown in Figure 15. As RS increases, it will take longer for the input capacitance to charge. In RD mode, the input switches are closed for approximately 800 ns at the start of the conversion. In WR-RD mode, the time that the switches are closed to allow this charging is the time that WR is low. Since other factors force this time to be at least 600 ns, input time constants of 100 ns can be accommodated without special consideration. Typical total input capacitance values of 45 pF allow RS to be 1.5 k without lengthening WR to give VIN more time to settle. Power Supply as Reference Input Not Referred to GND DS005501-21 DS005501-22 DS005501-23 FIGURE 13. Analog Input Options www.national.com 14 ADC0820 2.0 Analog Considerations (Continued) 2.4 INHERENT SAMPLE-HOLD Another benefit of the ADC0820s input mechanism is its ability to measure a variety of high speed signals without the help of an external sample-and-hold. In a conventional SAR type converter, regardless of its speed, the input must remain at least 12 LSB stable throughout the conversion process if full accuracy is to be maintained. Consequently, for many high speed signals, this signal must be externally sampled, and held stationary during the conversion. Sampled-data comparators, by nature of their input switching, already accomplish this function to a large degree (Section 1.2). Although the conversion time for the ADC0820 is 1.5 s, the time through which VIN must be 12 LSB stable is much smaller. Since the MS flash ADC uses VIN as its compare input and the LS ADC uses VIN as its zero input, the ADC0820 only samples VIN when WR is low (Sections 1.3 and 2.2). Even though the two flashes are not done simultaneously, the analog signal is measured at one instant. The value of VIN approximately 100 ns after the rising edge of WR (100 ns due to internal logic prop delay) will be the measured value. Input signals with slew rates typically below 100 mV/s can be converted without error. However, because of the input time constants, and charge injection through the opened comparator input switches, faster signals may cause errors. Still, the ADC0820s loss in accuracy for a given increase in signal slope is far less than what would be witnessed in a conventional successive approximation device. An SAR type converter with a conversion time as fast as 1 s would still not be able to measure a 5V 1 kHz sine wave without the aid of an external sample-and-hold. The ADC0820, with no such help, can typically measure 5V, 7 kHz waveforms. DS005501-24 FIGURE 14. DS005501-25 FIGURE 15. 2.3 INPUT FILTERING It should be made clear that transients in the analog input signal, caused by charging current flowing into VIN, will not degrade the A/Ds performance in most cases. In effect the ADC0820 does not look at the input when these transients occur. The comparators outputs are not latched while WR is low, so at least 600 ns will be provided to charge the ADCs input capacitance. It is therefore not necessary to filter out these transients by putting an external cap on the VIN terminal. 15 www.national.com ADC0820 3.0 Typical Applications 8-Bit Resolution Configuration DS005501-26 9-Bit Resolution Configuration DS005501-27 www.national.com 16 ADC0820 3.0 Typical Applications (Continued) Telecom A/D Converter Multiple Input Channels DS005501-28 VIN =3 kHz max 4VP No track-and-hold needed Low power consumption DS005501-29 8-Bit 2-Quadrant Analog Multiplier DS005501-30 17 www.national.com ADC0820 3.0 Typical Applications (Continued) Fast Infinite Sample-and-Hold DS005501-31 www.national.com 18 ADC0820 3.0 Typical Applications (Continued) DS005501-32 Digital Waveform Recorder 19 www.national.com ADC0820 Physical Dimensions inches (millimeters) unless otherwise noted Hermetic Dual-In-Line Package (J) Order Number ADC0820CCJ NS Package Number J20A www.national.com 20 ADC0820 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) SO Package (M) Order Number ADC0820BCWM, ADC0820CCWM or ADC0820CIWM NS Package Number M20B Molded Dual-In-Line Package (N) Order Number ADC0820BCN or ADC0820CCN NS Package Number N20A 21 www.national.com ADC0820 8-Bit High Speed P Compatible A/D Converter with Track/Hold Function Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Chip Carrier Package (V) Order Number ADC0820BCV NS Package Number V20A LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Franais Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

Find millions of documents on Course Hero - Study Guides, Lecture Notes, Reference Materials, Practice Exams and more. Course Hero has millions of course specific materials providing students with the best way to expand their education.

Below is a small sample set of documents:

Pittsburgh - PRESENTATI - 1160
I/O SubsystemsI/O Subsystems Data registers hold values that are treated as data by the device, such as the data read or written from/to a disk Status registers provide information about the device's operation, such as whether the current t
Pittsburgh - PRESENTATI - 1160
Hardware AcceleratorsAccelerator Is NOT a coprocessor which interfaces directly to the CPU and executes CPU instructions Is a specially designed system that interfaces to the CPU bus (as an I/O device) Is designed to implement (and speed up) co
Pittsburgh - ENGR - 1160
Fall 2006 Lab Assignment #3 University of Pittsburgh Department of Electrical Engineering Due Sept 19 for Tuesday Lab Due Sept 20 for Wednesday LabEE/CoE 1160/2160Introduction to the SignalTap II Logic Analyzer The SignalTap II Logic Analyzer sim
Pittsburgh - ENGR - 1160
When building your NIOS processor in the SOPC Builder, check these items to ensure it is built properly: Your clock speed is set to 33.333Mhz For each peripheral item, check that the following options are selected: o NIOS Processor 32 bit Standar
Pittsburgh - ENGR - 0501
INTEGRATED CIRCUITS74F153 Dual 4-line to 1-line multiplexerProduct specification IC15 Data Handbook 1996 Jan 05Philips SemiconductorsPhilips SemiconductorsProduct specificationDual 4-line to 1-line multiplexer74F153FEATURES Non-inver
Pittsburgh - ENGR - 0501
Philips SemiconductorsProduct specificationDual D-type flip-flop74ABT74QUICK REFERENCE DATASYMBOL PARAMETER Propagation delay CPn to Qn, Qn Output to Output skew Input capacitance Total supply current VI = 0V or VCC Outputs disabled; VCC = 5
Pittsburgh - ENGR - 0501
DM74LS247 BCD to 7-Segment Decoder Driver with Open-Collector OutputsMay 1992DM74LS247 BCD to 7-Segment Decoder Driver with Open-Collector OutputsGeneral DescriptionThe LS247 has active LOW open-collector outputs guaranteed to sink 24 mA It has
Pittsburgh - ENGR - 0501
INTEGRATED CIRCUITSDATA SHEETFINAL DEVICE SPECIFICATION COMMERCIAL nr.: 74LV86 QUAD 2-INPUT EXCLUSIVE-OR GATE Rev. DateIssued by:Dev. no: LC657BV930528 T. Tieben951125960128 8 + 2 Shs.22554 Logic Products Development NIJMEGEN PHILIPS SE
Pittsburgh - ENGR - 1192
Digital Integrated CircuitsA Design PerspectiveJan M. Rabaey Anantha Chandrakasan Borivoje NikolicDesigning Sequential Logic CircuitsNovember 2002 Digital Integrated Circuits2nd Sequential CircuitsSequential LogicInputs COMBINATIONAL LOGIC C
Pittsburgh - ENGR - 2646
ECE 1673: Linear Control Systems (4 Credits, Spring 2007)Lecture 2: Mathematical FoundationJanuary 8, 2007Instructor: Zhi-Hong Mao Assistant Professor of Electrical and Computer Engineering University of Pittsburgh, Pittsburgh, PA1Lab 1 and H
Pittsburgh - ENGR - 2695
ECE 2695: Adaptive Control (3 Credits, Fall 2008)Lecture 3: System Identification (I)September 15, 2008 Instructor: Zhi-Hong Mao Assistant Professor of ECE and Bioengineering University of Pittsburgh, Pittsburgh, PA1Outline Homework 2 Review
Pittsburgh - ENGR - 1563
ECE 1563 Spring, 2009 EXPERIMENT 1, DISCRETE-TIME SYSTEMS: Exercises Prelab exercises DUE before lab on Wednesday, January 14 Exercises Report DUE before lab on Monday, January 26 Objective The purpose of this experiment is to review the properties o
Pittsburgh - ENGR - 1563
5.3866291e-001 -4.0596919e-001 6.2547037e-001 5.2908876e-001 2.7512956e+000 1.7532246e+000 1.0649893e+000 7.0723574e-001 1.0828228e+000 1.7661915e+000 3.2368499e+000 1.3268867e+000 1.8633039e+000 1.6793866e+000 1.5547576e+000 2.001630
Pittsburgh - ENGR - 1563
Model { Name &quot;agc&quot; Version 6.0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames &quot; ComputedModelVersion &quot;1.44&quot; NumModelReferences 0 NumTestPointedSignals 0 } Save
Pittsburgh - ECE - 1232
EE1232 Assignment 1(Due on 6:00 pm, January 29, 2008) You need to finish following problems: Problem 6.1-6 Problem 6.1-8 (b) and 6.1-8(c) Problem 6.1-9 Problem 6.2-5 Problem 6.2-6Solved Problems by your TA Problem 6.1-7 Half-Wave Retarder. Conside
Pittsburgh - ECE - 1232
EE1232 Assignment 4(Due on 6:00 pm, February 20th, 2008) 1. 2. 3. 4. Problem 13.3-3 Problem 13.3-4 Problem 13.4-3 Problem 13.4-6Solved Problem Problem 13.4-2N 2 n (N1 N 2 ) dN 2 dt = t + t sp sp dn n ( N N ) n 1 2 = p t sp dtProblem
Pittsburgh - ENGR - 1266
Course Notes for EE1266 Applications of fields and wavesNOTES for Antennas I This lecture covers 8.1 and 8.2 1. Short dipole antenna 2. Far-field approximation 3. Antenna radiation characteristics: Pattern, dimensions, directivity, gain, and resist
Pittsburgh - ECE - 0257
Course Notes for EE 0257 Analysis and Design of Electronic CircuitsThe small-signal analysisChapter 5: Bipolar Junction Transistors (BJTs) This lecture covers Section 5.6-5.71. Small signal analysis 2. The Hybrid- and the T-models 3. The common-
Pittsburgh - ENGR - 1266
Course Notes for EE1266 Applications of fields and wavesNOTES for Transmission Lines II This lecture covers Chapter 6.2 and 6.3 1. 2. 3. 4. Line parameters for lossless T-line Voltage reflection coefficient Standing waves Input impedance of the los
Pittsburgh - ENGR - 1266
Course Notes for EE1266 Applications of fields and wavesNOTES for Plane Waves II This lecture covers Chapter 7.3 1. Linear polarization 2. Circular polarization 3. Elliptical polarizationThe polarization of a UPW describes the shape and locus of
Pittsburgh - ENGR - 2141
Stimulus and ResponseStimulus and Response! ! ! ! ! !Simple Stimulus Verifying the Output Self-Checking Testbenches Complex Stimulus Complex Response Predicting the OutputSimple Stimulus!Verilog Example 1`timescale 1ns/1ns Module testbench
Pittsburgh - ENGR - 2141
Verification PlanVerification Plan!This is the specification for the verification effort. It gives the what am I verifying and how am I going to do it!Role of the Verification Plan! !Specifying the Verification! !Specifies the Verificati
Pittsburgh - ENGR - 2141
Introduction to OverviewWhat is functional formal verification? Model checking Sugar (basics) EDL (basics) Exercise: a simple arbiterCindy Eisner Edits by Steve Levitan &amp; Bruce Wile Formal Methods Group IBM Haifa Research Laboratory February
Pittsburgh - ENGR - 2141
Execution Flow Chart Verisity VA NotesDerived from VA by Steven Levitan Steve@ee.pitt.eduTest Phases and their MethodsInitialization Pre-Run Generation global.init() global.setup_test() global.generate_test() general preparations configuration me
Pittsburgh - EE - 1473
Lecture-16:EE1473: Digital Communication Systems Heung-no Lee2003 Heung-no LeeSpr-03University of Pittsburgh1Agenda Discussion of Midterm Term Project2003 Heung-no LeeSpr-03University of Pittsburgh2Term Project (Part I) Design
Pittsburgh - EE - 1473
Lecture-15: EE1473: Digital Communication SystemsHeung-no Lee2003 Heung-no LeeSpr-03University of Pittsburgh1Agendav Channel Coding Theorem v Sphere Packing Argument v Shannon Limit2003 Heung-no LeeSpr-03University of Pittsburgh2