120, Comp Spring 2005
1/27 Lecture
page 1
Memory, Latches, & Registers
1) 2) 3) 4)
Structured Logic Arrays Memory Arrays Transparent Latches How to save a few bucks at toll booths 5) Edge-triggered Registers
Comp 120 Spring 2005
1/27/05
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General Table Lookup Synthesis
A
AB Fn(A,B) 00 01 10 11 0 1 1 0
B
MUX Logic
Fn(A,B)
Generalizing: Remember from last lecture that, in theory, we can build any 1-output combinational logic block with multiplexers.
2N For an N-input function we need a _____ input multiplexer.
BIG Multiplexers? How about 10-input function? 20-input?
Comp 120 Spring 2005
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Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
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A Mux's Guts
Decoder
A decoder generates all possible product terms for a set of inputs
A B A B A B A B
I 00 I 01 I 10 I 11
Selector
0 1 2 3
Multiplexers can be partitioned into two sections.
Y
A DECODER that identifies the desired input,and a SELECTOR that enables that input onto the output.
Hmmm, by sharing the decoder part of the logic MUXs could be adapted to make lookup tables with any number of outputs
Comp 120 Spring 2005
1/27/05
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A New Combinational Device
D1 D2 DN k NOW, we are well on our way to building a general purpose table-lookup device. We can build a 2-dimensional ARRAY of decoders and selectors as follows ...
Comp 120 Spring 2005 1/27/05 L05 Memory 4
DECODER: k SELECT inputs, N = 2k DATA OUTPUTs. Selected Dj HIGH; all others LOW.
Have I mentioned that HIGH is a synonym for `1' and LOW means the same as `0'
Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
page 3
Shared Decoding Logic
There's an extra level of inversion that isn't necessary in the logic. However, it reduces the capacitive load on the module driving this one.
A B Cin
Decoder
These are just "DeMorgan"ized NOR gates
0
1
2
3
4
5
6
7
S
This ROM stores 16 bits in 8 words of 2 bits.
Cout
Configurable Selector
We can build a general purpose "table-lookup" device called a Read-Only Memory (ROM), from which we can implement any truth table and, thus, any combinational device Made from PREWIRED connections , and CONFIGURABLE connections that can be either connected or not connected
Comp 120 Spring 2005 1/27/05 L05 Memory 5
ROM Implementation Details
Tiny PFET with gate tied to ground = resistor pullup that makes wire "1" unless one of the NFET pulldowns is on.
A B Cin
Hardwired AND logic Programmable OR logic Advantages: - Very regular design (can be entirely automated) Problems: - Active Pull-ups (Static Power) - Long metal runs (Large Caps) - Slow
JARGON: Inputs to a ROM are called ADDRESSES. The decoder's outputs are called WORD LINES, and the outputs lines of the selector are called BIT LINES.
S
Cout
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Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
page 4
Speeding up ROMS
A B Cin
0 1 0 1
The key making ROMS go fast is to minimize the capacitances of those long wires running through the array. The best way to accomplish this is to build square arrays.
All of our NOR gates now have exactly 4 inputs
S Cout
Why NORs? Couldn't we Why NORs? Couldn't we eliminate some inverters eliminate some inverters by using NANDs? by using NANDs?
Comp 120 Spring 2005
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Logic According to ROMs
ROMs ignore the structure of combinational functions ... Size, layout, and design are independent of function Any Truth table can be "programmed" by minor reconfiguration: - Metal layer (masked ROMs) - Fuses (Field-programmable PROMs) - Charge on floating gates (EPROMs) ... etc. ROMs tend to ROMs tend to generate "glitchy" generate "glitchy" outputs. WHY? outputs. WHY?
Model: LOOK UP value of function in truth table... Inputs: "ADDRESS" of a T.T. entry ROM SIZE = # TT entries... ... for an N-input boolean function, size = 2N x #outputs __________
Comp 120 Spring 2005
1/27/05
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Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
page 5
Example: 7-sided Die
What nature can't provide... electronics can (with the same number of LEDs!). We want to construct a die with the following sides:
An array of LEDs, labeled as follows, can be used to display the outcome of the die:
T V Y W U X Z
Comp 120 Spring 2005
1/27/05
L05 Memory 9
ROM-Based Design
Truth Table for a 7-sided Die
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 T 0 0 0 0 1 1 1 1 U 0 0 1 1 1 1 1 1 V W X Y Z 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1
Once we've written out the truth table we've basically finished the design
Possible optimizations: - Eliminate redundant outputs - Addressing tricks
T V Y W
U X Z
Comp 120 Spring 2005
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Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
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A Simple ROM implementation
A B C
No output depends on this product term or WORD LINE A different set of AND gates might make this a lot simpler
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
T/Z 0 0 0 0 1 1 1 1
U/Y 0 0 1 1 1 1 1 1
V/X 0 0 0 0 0 0 1 1
W 0 1 0 1 0 1 0 1
T V Y W
U X Z
T/Z U/Y V/X W
1/27/05
That was easy but there is clearly some waste. - unused products - over-specified terms
Comp 120 Spring 2005
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Another General-Purpose Logic Device
What if the AND terms of a ROM's decoder were programmable in the same way that the OR terms are? Then we could use some of our logic minimization tricks to reduce the size of the ROM array.
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 T/Z 0 0 0 0 1 1 1 1 U/Y 0 0 1 1 1 1 1 1 V/X 0 0 0 0 0 0 1 1 W 0 1 0 1 0 1 0 1
This logic is so simple we should just build it with 2 gates!
T/Z = A U/Y = A + B V/X = AB W =C
T V Y W
U X Z
PLA Programmable Logic Array
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Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
page 7
PLA 7-sided Die implementation
"AND plane"
A B C
PLAs like ROMs support the synthesis of arbitrary logic functions using SOP implementations. However, they allow for - minimal realizations - smaller (faster) arrays
T/Z U/Y V/X W
Regular structure - automatic generation - easy design - still slower than optimized gates
T V Y W
U X Z
C AB B A
Comp 120 Spring 2005
"OR plane"
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Programmable Look-up Tables
REMEMBER, every combinational circuit can be expressed as a lookup table. As a result a ROM is a universal logic device. Unfortunately, the ROMs we've built thus far are "HARDWIRED". That is, the function that they compute is encoded by the pulldown transistors that are built the into OR-plane of the ROM. What we'd really like is a combinational gate that could be reconfigured dynamically. For this we'll need some form of storage.
WORD line
The function of a ROM is determined by the presence of a transistor at the intersection of a WORD line from the AND array with a BIT line going to the OR array
How to make a storage device?
BIT line
Comp 120 Spring 2005
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Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
page 8
Analog Storage: Using Capacitors
We've chosen to encode information using voltages and we know from physics that we can "store" a voltage as charge on a capacitor: N-channel FET serves as an access switch
word line bit line
REF To write: Drive bit line, turn on access fet, force storage cap to new voltage To read: precharge bit line, turn on access fet, detect (small) change in bit line voltage
V
Pros: compact! Cons: it leaks! refresh complex interface stable? (noise, ...)
This storage circuit is the basis for commodity DRAMs
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Comp 120 Spring 2005
Dynamic Memory
TiN top electrode (VREF)
Ta2O5 dielectric
poly word line
access FET
Comp 120 Spring 2005
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Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
page 9
A Digital Storage Element
It's also easy to build a settable DIGITAL storage element (called a latch) using a MUX using FEEDBACK:
Here's a feedback path, so it's no longer a combinational circuit.
"state" signal appears as both input and output
A D B G S
0
G D QIN QOUT Q Y 0 -- 0 0 -- 1 1 0 -1 1 -0 1 0 1
Q stable Q follows D
1
Comp 120 Spring 2005
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Looking Under the Covers
Let's take a quick look at the equivalent circuit for our MUX when the gate is LOW (the feedback path is active)
0
D G=0 Q
Q G=0 D
1
1 1
Q
Advantages: 1) Maintains remembered state for as long as power is applied. 2) State is DIGITAL Disadvantage: 1) Requires more transistors
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This storage circuit is the basis for commodity SRAMs
Comp 120 Spring 2005 1/27/05
Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
page 10
Why Does Feedback = Storage?
BIG IDEA: use positive feedback to maintain storage indefinitely. Our logic gates are built to restore marginal signal levels, so noise shouldn't be a problem! Result: a bistable storage element
VIN
VTC for inverter pair Feedback constraint: VIN = VOUT
VOUT Not affected by noise
VOUT
Three solutions: two end-points are stable middle point is unstable
VIN We'll get back to this!
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Comp 120 Spring 2005
Static D Latch
D G Positive latch
Q follows D
Q
D G
Q
Negative latch
What is the difference?
D G Q
Q stable D G
1
Q
0
"static" means latch will hold data (i.e., value of Q) while G is inactive, however long that may be.
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Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
page 11
Latch Problems
P2 G G D P1 Q
G D P1 ?
G D P1 ?
Short pulse on G: how long is enough to set the latch?
Comp 120 Spring 2005
D changes about the same time as latch closes. What value is saved?
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A DYNAMIC Discipline
Design of sequential circuits MUST guarantee that inputs to sequential devices are valid and stable during periods when they may influence state changes. This is assured with additional timing specifications. >tPULSE
G
G D
P2 G P1 Q
D
tPULSE: minimum pulse width guarantee G is active for long enough for latch to capture data tSETUP: setup time guarantee that D value has propagated through feedback path before latch closes tHOLD: hold time guarantee latch is closed and Q is stable before allowing D to change
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>tSETUP
>tHOLD
Marc Pollefeys 1/27/2005 00:42
Comp 120, Spring 2005
1/27 Lecture
page 12
Does this work yet?
"start" button "0" button "1" button Current state
ROM
64x4
unlock
Next state
3
3
Q G
D Hmm. Hard t...