addu
=?
Iout Datapath: memory 32 32 register file CLK Iaddr 32 00 CLK PC new PC calculation
16 imm s-ext 0 30 30
32
0 1
daddr ALUsrc din ALUctrl dmc
32
alu
0 1 dout data memory
2 1 5 5 5
control
tgt
pc
30
26 4
0
1
30
newpc
30
30
0 1
30
carry = 1
extend
+
Datapath: addiu
=?
Iout memory 32 32 register file CLK Iaddr 32 00 CLK PC new PC calculation
16 imm s-ext 0 30 30
32
0 1
daddr ALUsrc din ALUctrl dmc
32
alu
0 1 dout data memory
2 1 5 5 5
control
tgt
pc
30
26 4
0
1
30
newpc
30
30
0 1
30
carry = 1
extend
+
Datapath: lw
=?
Iout memory 32 32 register file CLK Iaddr 32 00 CLK PC new PC calculation
16 imm s-ext 0 30 30
32
0 1
daddr ALUsrc din ALUctrl dmc
32
alu
0 1 dout data memory
2 1 5 5 5
control
tgt
pc
30
26 4
0
1
30
newpc
30
30
0 1
30
carry = 1
extend
+
Datapath: sw
=?
Iout memory 32 32 register file CLK Iaddr 32 00 CLK PC new PC calculation
16 imm s-ext 0 30 30
32
0 1
daddr ALUsrc din ALUctrl dmc
32
alu
0 1 dout data memory
2 1 5 5 5
control
tgt
pc
30
26 4
0
1
30
newpc
30
30
0 1
30
carry = 1
extend
+
Datapath: beq
=?
Iout memory 32 32 register file CLK Iaddr 32 00 CLK PC new PC calculation
16 imm s-ext 0 30 30
32
0 1
daddr ALUsrc din ALUctrl dmc
32
alu
0 1 dout data memory
2 1 5 5 5
control
tgt
pc
30
26 4
0
1
30
newpc
30
30
0 1
30
carry = 1
extend
+
Datapath: j
=?
Iout memory 32 32 register file CLK Iaddr 32 00 CLK PC new PC calculation
16 imm s-ext 0 30 30
32
0 1
daddr ALUsrc din ALUctrl dmc
32
alu
0 1 dout data memory
2 1 5 5 5
control
tgt
pc
30
26 4
0
1
30
newpc
30
30
0 1
30
carry = 1
extend
+
Performance
IF instruction fetch
Iout memory 32
RF regfile
32 register file CLK 32
=?
ALU
WB write- back
0 daddr 1 dout
32
alu 0 1
Iaddr
32 00
2 1 5 5 5
extend
ALUsrc din
ALUctrl
MEM
CLK
PC new PC calculation
data memory
control dmc
How fast can we run the clock?
Multi-Cycle Datapath
IF instruction fetch
Iout memory 32
RF regfile
32 register file CLK 32
=?
ALU
WB write- back
0 daddr 1 dout
32
alu 0 1
Iaddr
32 00
2 1 5 5 5
extend
ALUsrc din
ALUctrl
MEM
CLK
PC new PC calculation
data memory
control dmc
Observation: we can run the clock faster by partitioning the execution into multiple stages.
Multi-Cycle Datapath
EX
CLK register file
MEM
WB
WB
CLK PC
alu 0 1
0 1
IF
RF/RD
=
Stages: instruction fetch, register execute, fetch/decode, memory, writeback.
Idea: break down single instruction execution into smaller parts, some instructions skip parts of execution.
Multi-Cycle Datapath
IF
RD
EX
MEM
WB lw $1,-4($3) add $1,$2,$3 beq $1,$2,L
PC
needs a write-enable signal
Design FSM for control
(textbook has details: sections 5.4, 5.5)
Performance
Suppose we had:
IF:
5ns,
RD:
3ns,
ALU:
6ns,
MEM:
5ns,
WB:
4ns
Single-cycle datapath cycle time: 23ns
Multi-cycle datapath:
lw:
30ns 24ns 18ns
add: beq:
Is this better? Depends on the instruction mix! (should have balanced pipeline stages)
Pipelining
Why not start executing the next instruction as soon as the rst one has been fetched?
IF
RD IF
EX RD IF
MEM EX RD
WB WB EX
lw $1,-4($3) add $1,$2,$3 beq $1,$2,L
Hardware resource conict...
Pipelining
Simple x: make all instructions take the same number of cycles.
IF
RD IF
EX RD IF
MEM EX RD
WB MEM EX WB MEM
lw $1,-4($3) add $1,$2,$3 beq $1,$2,L
WB
Each instruction takes 30ns, but we complete an instruction every 6ns (caveat: op/latch overhead).
Pipelined Datapath
EX
CLK register file
MEM
WB
WB
CLK PC
alu 0 1
0 1
IF
RF/RD
=
Introduce positive-edge triggered ip-ops between pipeline stages to hold intermediate values.
Pipelined Datapath: Control
IR1 IR2 EX
CLK register file
IR3 MEM
IR4
WB
CLK PC
alu 0 1
0 1
IF
RF/RD
=
WB
Basic idea: copy the instruction, and generate local control in each pipeline stage.
Pipelined Datapath: Timing
IF i cycle i+1 i+2 i+3 i+4 ins1 ins2 ins3 ins4 ins5
RD
EX
MEM
WB ins1 ins2 ins3 ins4 ins5
ins1 ins2 ins3 ins4 ins1 ins2 ins3 ins1 ins2 ins1
program
Instructions ow through the datapath, advancing every cycle.
Pipelined Datapath: Timing
IF IR1 RD IR2 EX MEM IR3 WB IR4
CLK
register file
alu 0
CLK
0 1
1
PC
Flops between stages: positive-edge triggered register le: negative-edge triggered
PC,
Single Instruction Execution
IF IR1 RD IR2 EX MEM IR3 WB IR4
CLK
register file
alu 0
CLK
0 1
1
PC
0x1234
CLK
Single Instruction Execution
IF IR1 X
CLK register file
RD IR2
EX
MEM IR3
WB IR4
alu
0 1
0x1234
CLK PC
0 1
CLK
Single Instruction Execution
IF IR1 RD IR2 EX MEM IR3 WB IR4
CLK
register file
alu 0
CLK PC
0 1
X
1
CLK
Single Instruction Execution
IF IR1 RD IR2 EX MEM IR3 WB IR4
CLK
register file
alu 0
CLK PC
0 1
X
1
CLK
Register le output can change!