Sci ECE/Comp 352 Digital System Fundamentals
Homework 5 Solutions - Fall 2001
Problem solutions 2000 Prentice Hall Problems are presented in the following order: Text Problems, Old Exam Problems.
1.(3-70)
module decoder_2_to_4_st(B, E, D); input [1:0] B; input E; output [3:0] D; wire [1:0] not_A; not go(not_A[0], B[0]), g1(not_A[1], B[1]); nand g2(D[0], not_A[0], not_A[1], E), g3(D[1], B[0], not_A[1], E), g4(D[2], not_A[0], B[1], E), g5(D[3], B[0],B[1], E); endmodule g5: NAND3 port map (A(0), A(1), E, D(3)); end structural_1;
2.(3-72*)
X1 X2 X3 N5 X4 N1 N2 N3 N6 N4 F
3.(3-75)
A B C D B C B D A B G F
1
Problem Solutions Homework 4
4.(3-81)
/ 4-bit Adder: Behavioral Verilog Description module adder_4_b_v(A, B, Sel, S, C4); input[3:0] A, B; input Sel; output[3:0] S; output C4; assign {C4, S} = Sel ? (A - B):(A + B); endmodule
5.(4-44)
module problem_4_44 (S, D, Y) ; input [1:0] S ; input [3:0] D ; output Y; reg Y ; // (continued in the next column) always @(S or D) begin case (S) 2'b00 : Y <= D[0] ; 2'b01 : Y <= D[1] ; 2'b10 : Y <= D[2] ; 2'b11 : Y <= D[3] ; endcase; end endmodule
6.(4-47*)
module JK_FF (J, K, CLK, Q) ; input J, K, CLK ; output Q; reg Q; // (continued in the next column) always @(negedge CLK) case (J) 0'b0: Q <= K ? 0: Q; 1'b1: Q <= K ? ~Q: 1; endcase endmodule
2
Problem Solutions Homework 3
7.(4-48) (See Errata: Delete the sentence "Use the D flip-flop ...")
module seq_circuit (DIN, CLK, RESET, DOUT) ; input DIN, CLK, RESET ; output DOUT ; reg [2:0] state, next_state, DOUT; parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011; parameter E = 3'b100, F = 3'b101, G = 3'b110, H = 3'b111; //State register process always @(posedge CLK or posedge RESET) begin if (RESET) //asynchronous RESET active High state <= A; else //use CLK rising edge state <= next_state; end //Next state function always @(DIN or state) begin case (state) A: next_state <= DIN ? C : B; B: next_state <= DIN ? E : D; C: next_state <= F; D: next_state <= G; E: next_state <= DIN ? H : G; F: next_state <= DIN ? H : G; G: next_state <= A; H: next_state <= A; endcase end //Output function always @(DIN or state) begin case (state) A: DOUT <= DIN ? 1'b0 : 1'b1; B: DOUT <= DIN ? 1'b0 : 1'b1; C: DOUT <= DIN ? 1'b1 : 1'b0; D: DOUT <= DIN ? 1'b1 : 1'b0; E: DOUT <= DIN ? 1'b0 : 1'b1; F: DOUT <= DIN ? 1'b0 : 1'b1; G: DOUT <= DIN ? 1'b1 : 1'b0; H: DOUT <= 1'b1; endcase end endmodule
State Bus key 0 1 3 4 2 5
6
7
Notice that DOUT is equal to the inverse of the input at states 0, 1, 4, and 5, while it is equal to the input at states 2, 3, and 6. For state 7, DOUT equals 1.
8.(5-3)*
1000, 0100, 1010, 1101 0110, 1011, 1101, 1110
9.(5-6) *
Shifts: A B C 0 0110 0011 0 1 1011 0001 0 2 0101 0000 1 3 0010 0000 1 4 1001 0000 0
3
Problem Solutions Homework 4
10.(5-7)
The SO output to register B must be inverted and the initial carry must be set to 1, this forms the 2's complement of the contents of register B If A < B, the final value left in the carry flip-flop will be 0. If A < B, then the result will be in 2's complement form.
11. (5-8)*
Replace each AND gate in Figure 5-6 with an AND gate with one additional input and connect this input to the following: S1 + S0 This will force the outputs of all the AND gates to zero, and, on the next clock edge, the register will be cleared if S1 is 0 and S0 is logic one. Also, replace each direct shift input with this equation: S1S0 This will stop the shift operation from interfering with the load parallel data operation.
12.(5-10)*
a) 1000, 0100, 0010, 0001, 1000 b) # States = n
13.(5-13)
Max Delay f= 1/T = = 16(2 ns) 1/32 ns = = 32 ns 31.14 MHz
14.(5-14)
a) 4 b) 6
15.(5-19)
CLK CTR 4 Count
MAX = 2 + 2 + 2 + 2 = 8 gates
CTR 4 Q0-Q3 EN Q0 Q1 Q2 Q3 CO Q4-Q7
CTR 4 EN Q0 Q1 Q2 Q3 CO Q8-Q11
CTR 4 EN Q0 Q1 Q2 Q3 CO Q12-Q15
EN Q0 Q1 Q2 Q3 CO
4
Problem Solutions Homework 3
16.(5-21)*
S E
J C K
Q0
J C K
Q1
J C K
Q2
J C K
Q3
Clock
17.(5-22)
CLK 1 CTR 4 Load Count D0 Q0 D1 Q 1 D2 Q 2 D3 Q 3 CO CLK 1 CTR 4 Load Count D0 Q0 D1 Q 1 D2 Q 2 D3 Q 3 CO
18.(5-25)
JQ8 JQ4 JQ2 JQ1 = = = = Q1Q2Q4 Q1Q2 Q1Q8 1
,
KQ8 KQ4 KQ2 KQ1
= = = =
Q1 Q1Q2 Q1 1
, , ,
19.(6-1)*
a) A = 13, D = 32 b) A = 18, D = 64 c) A = 25, D = 32 d) A = 32, D = 8
20.(6-2)
a) 215 b) 221 c) 227 d) 232
21.(6-3)*
(633)10 = (10 0111 1001)2, (2731) 10 = (0000 1010 1010 1011)2
5
Problem Solutions Homework 4
22.(6-4)*
Number of bits in array = 215 * 23 = 218 = 29 * 29 Row Decoder size = 2 9 Column Decoder size = 215 - 29 = 26 a) Row Decoder = 9 to 512, AND gates = 29 = 512 Column Decoder = 6 to 64, AND gates = 26 = 64 Total AND gates required = 512 + 64 =576 b) (21000)10 = (0101 0010 0000 1000)2, Row = 328, Column = 8
23.(6-7)
With 4-bit data, the RAM cell array is a square of 213 213. Hence number of address pins is 2 13 = 26.
24.(6-9)*
a) 32 b) 20,15 c) 5, 5to32
25.(6-10)
Replace the 64k x 8 RAMs in figure 6-13 with the following basic cell to realize a 256k x 32 RAM.
Data 0 - 7 Address 0 - 15 64K x 8 RAM
8 16 Data Address CS R/W 8 16
Data 8 - 15
Data 16 - 23
Data 23 - 31
64K x 8 RAM
Data Address CS R/W 8 16
64K x 8 RAM
Data Address CS R/W 8 16
64K x 8 RAM
Data Address CS R/W
From Read/Write From Decoder
Out Data 0 - 7
Out Data 8 - 15
Out Data 16 - 23
Out Data 23 - 31
26.+(a) (5) Draw the circuit diagram corresponding to the given Verilog description.
module prob3_5a Y); (X, input[3:0] X; output[1:0] Y; wire[3:0] N; not N1 N2 and A1 A2 or O1 (N[0], (Y[0], (N[1], (N[2], (Y[1], X[3]), N[1]); N[0], X[2]), X[1], X[0]); N[0], N[2]);
Circuit Diagram: X[0] A2 X[1] X[2] N1 X[3] N[0] N[1] O1 A1 Y[1] N[2] N2 Y[0]
endmodule
(b) (6) Draw the state diagram corre-
6
Problem Solutions Homework 3
sponding to the given Verilog description.
module prob3_5b (X, RESET, State Diagram: CLK, Z); 0/0 input CLK, RESET, X; output Z; reg[1:0] state, next_state; RESET 00* reg Z; always@(posedge CLK or posedge RESET) 1/0 1/1 begin if (RESET) 1/0 state <= 2'b00; else 0/0 state <= next_state; 01* 10 end always@(X or state) 0/0 begin //Ignore the next statement. *Also, for states 00 and 01, the output can be next_state <= 2'bxx; Z = 1'bx; shown on the state and omitted on the arcs. case (state) 2'b00: begin Z = 1'b0; if (X == 1) next_state <= 2'b01; else next_state <= 2'b00; end 2'b01: begin Z = 1'b0; if (X == 1) next_state <= 2'b01; else next_state <= 2'b10; end 2'b10: begin if (X == 1) begin next_state <= 2'b00; Z = 1'b1;
end else begin next_state <= 2'b10; Z = 1'b0; end end endcase end endmodule
7
Problem Solutions Homework 4
(c) (7) Complete the following Verilog dataflow description which is to compute: 1) the majority function M of A, B, and C, and 2) a selection function Y between A and B with C as the selection input. The majority function is 1 if two or more of A, B, and C have value 1; otherwise, it is 0. The select function is to form Y = A if C = 0 and Y = B if C = 1. module prob3-5c (A, B, C, M, Y); input A, B, C; output M, Y; assign M = A & B | A & C | B & C assign Y = C ? B : A // also, ~C & A | C & B endmodule 27.+ (a) The block diagram of a bidirectional shift register is given below. This register is controlled by a 2-bit code (SL, SR) with the operations performed listed in the table below. 7 SR In SL SR Clock Bidirectional Shift Register SHR 0 SL In
SL 0 0 1 1 SR 0 1 0 1 Operation Hold Shift Right Shift Left Not allowed (don't care)
Manually simulate the register for 8 clock cycles with the initial contents and inputs as given in the simulation table below. The results due to any given line of the table are to appear on the following line due to the positive clock edge triggering of the register. Shift Register Contents Clock Cycle 1 SL 0 SR 1 SL_In 0 SR_In 7 1 1 6 0 5 0 4 1 3 0 2 1 1 1 0 0
8
Problem Solutions Homework 3
Shift Register Contents Clock Cycle 2 3 4 5 6 7 8 SL 0 0 1 1 0 1 0 SR 0 1 0 0 1 0 1 SL_In 1 0 0 1 1 0 0 SR_In 7 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 28.+ A block diagram for a bit cell of the register given in part a) is shown below. Design the logic for the cell using a D flip-flop and sum-of-products (SOP) logic for D(i). 6 1 1 1 1 0 1 0 1 5 0 0 1 0 0 0 0 0 4 0 0 0 0 1 0 1 0 3 1 1 0 1 0 1 0 1 2 0 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0
SHR(i + 1) SL SR CLOCK SHR Bit Cell
SHR(i 1)
SHR(i) Equation: D = SL SHR(i 1) + SR SHR(i + 1) + SL SR SHR(i)
9
Problem Solutions Homework 4
Implementation: SHR(i + 1) SL SR
D
SHR(i 1)
CLOCK SHR Bit Cell SHR(i) 29.+
C
a) Three positive edge-triggered flip-flops with asynchronous clear are shown. Connect the flipflops shown to form a ripple down counter (counts 0, 7,...