of University Wisconsin - Madison
ECE/Comp Sci 352 Digital Systems Fundamentals
Charles R. Kime Section 2 Fall 2001
Logic and Computer Design Fundamentals
Lecture 5 Registers & Counters Part 2
Charles Kime 2001 Prentice Hall, Inc
Counters
Counters are sequential circuits which "count" through a specific
state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage:
Ripple Counters
S Clocks are connected to flip-flop outputs, thus not truly
synchronous
S Outputs are "delayed" for higher bits. S Resurgent because of low power consumption
Synchronous Counters
S Clocks are directly connected to the flip-flops. S Logic is used to implement the desired state sequencing.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 2
1
Counter Basics: Divide by 2
Consider the following circuit:
"1"
T Q
A
D Q Q'
B
CP
Draw Waveform A and B
CP
A
B
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 3
Divide Clock Frequency by 2
The waveforms look like a new clock with twice the period of CP (half the frequency). The flip-flops are said to "divide-by-2" since the frequency of the output waveform is 1/2 the frequency of clock CP.
"1"
T Q
A
D Q Q'
B
CP
CP
A
B
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 4
2
Ripple Counter
What happens now? (note clock change on B)
"1"
T Q
A
D Q Q'
B
CP
CP
A
Draw the waveform for B.
B
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 5
Ripple Counter (Continued)
Here's what happens:
"1"
T Q
A
D Q Q'
Note that B "divides" the frequency in A by 2 -- or doubles the period. Notice the count (B A) base 10 of: 3210321 ... What kind of counter is this? Down Counter!
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
B
CP
CP
A
1
0
1
0
1
B
1
1
0
0
1
Chapter 5 Part 2 6
3
Ripple Counter (Continued)
Now consider this (what has changed?):
"1"
T Q Q'
A
D Q Q'
B
CP
CP
A
1
0
1
0
1
Draw waveform B.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
B
Chapter 5 Part 2 7
Ripple Counter (Continued)
Here's what happens:
Note that B "divides" the frequency in A by 2 -- or doubles the period. Notice the count (B A) base 10 of: 012301 ... What type of counter is this? Up Counter! Can also use negative edgetriggering
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
"1"
T Q Q'
A
D Q Q'
B
CP
CP
A
1
0
1
0
1
B
0
1
1
0
0
Chapter 5 Part 2 8
4
Ripple Counter (Continued)
The circuits designed this way are called Ripple Counters because each edge sensitive transition (positive in the example's case) causes a change in the next flipflop's state. The changes "ripple" up the chain. That is, each transition occurs after a clock to output delay from the stage before. To see this effect in detail look at the following circuit: What is the detailed waveform behavior?
"1"
T Q T Q T Q
CP
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
A
B
C
Chapter 5 Part 2 9
Ripple Counter (Continued)
"1 "
T Q T Q T Q
CP
A
B
C
Here is the detailed waveform behavior:
CP
A
What "counts" are shown?
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
1
0
1
0
1
B
0
1
1
0
0
C
0
0
0
1
1
Chapter 5 Part 2 10
5
Ripple Counter (Continued)
Starting with A=B=C = "1", equivalent to (C,B,A) = 7 base 10, the next count will increment the count to (A,B,C) = 0 base 10. Here's what happens in fine timing detail:
The clock to output delay tPHL causes an increasing delay from clock edge for each stage transition. Thus, the count "ripples" from least to most significant bit. For n bits, total worst case delay is n tPHL.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
TpHL
CP
TpHL
A
TpHL
B
C
Chapter 5 Part 2 11
Synchronous Counters
In order to eliminate the "ripple" effect, we will use a common clock for each flip-flop and a combinatorial circuit to generate the next state. One way to generate a counter is with an Adder/Register circuit: A Here "CNT" is the
count constant: 0000 is HOLD, CNT 1111 is DOWN and 0001 is UP. Note potential logic CP simplification due to constant applied to B.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
D3 D2 D1 D0
Q3 Q2 Q1 Q0
S UM
B 4-Bit Adde r
Chapter 5 Part 2 12
6
Synchronous Counters (Continued)
A
A simple 2-bit synchronous counter can be made with two "T" Flip-Flops:
Note that the Q from the first stage enables the second stage to toggle. Does it count "up" or "down"? How do you extend this to three stages?
"1"
T Q T Q
B
CP
A
1
0
1
0
1
B
0
1
1
0
0
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 13
Synchronous Counters (Continued)
"1"
T Q T Q T Q
CP
The concept can be extended to multiple stages. For binary "UP" counters, the upper stages toggle when ALL of the lower stages are at the value "1" and the clock occurs. By "ANDing" in a count enable signal to each "T" input, we can produce a "HOLD" count signal.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 14
7
Synchronous Counters Serial Gating
S When a two-input AND gate is used for
each stage of the counter with a "ripplelike" carry, this is referred to as serial gating. S As the size of the counter increases the delay through the combinational logic increases roughly in proportion to n, the number of stages.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 15
Synchronous Counters Parallel Gating
S When a multiple-input ( >2) AND gates
are used for each stage of the counter with logic dedicated to each stage or to a group of stages, this is referred to as parallel gating. It resembles carry lookahead in an adder. S As the size of the counter increases the delay through the combinational logic increases roughly in proportion to n/m, the number of stages/the group size.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 16
8
Design: Synchronous BCD
We can use the sequential logic model to design a synchronous BCD counter with T flip-flops. Below is the State Table. Current State Next State T-FF Excitation
Q8 Q4 Q2 Q1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 Q8 Q4 Q2 Q1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 T8 T4 T2 T1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1
Chapter 5 Part 2 17
Don't care
states have been left out here.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Synchronous BCD (Continued)
Use K-Maps to minimize the next state function:
T8
0 1
Q2
3 2
T4
0 1
Q2 1 1 x
15 3 2
4
5
1 x
7
6
Q4 x Q8
4
5
7
6
Q4
x Q8
12 8
x
13
x
15 14
x
12 13 8 9
x
14
1
x
9 11
x
10
x
11
x
10
T8 = Q8Q1 + Q4Q2Q1 T4 = Q2Q1 T2 = Q8'Q1 T1 = "1" Note: Don't Cares are included here.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Q1 Q2
0
Q1 T1
2
T2 1 1 x
12 13 8 9 1
Q2 1 1
0
1 1 x
3
1 1 x
1
1 1 x
3
1 1 x
2
4
5
7
6
Q4 x Q8 1
4
5
7
6
Q4
x Q8
x
15 14
12
13
15
14
x
11
x
10
8
1
x
9 11
x
10
Q1
Q1
Chapter 5 Part 2 18
9
Synchronous BCD (Continued)
The minimized circuit:
CP
"1"
T Q Q
Q1
T Q
Q2
Q8*Q1
Q
T Q
Q4
Q2*Q1
Q
Q4*Q2*Q1
T Q
Q8
Q8*Q1
Q
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 19
Synchronous BCD (Continued)
What about Don't the Cares now?. ALL Next States are now specified!!
Current State Q8 Q4 Q2 Q1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Next State Q8 Q4 Q2 Q1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? T-FF Excitation T8 T4 T2 T1 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 0 1
Chapter 5 Part 2 20
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
10
Synchronous BCD (Continued)
Don't care states have now been specified by the logic.
Current State Q8 Q4 Q2 Q1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Next State Q8 Q4 Q2 Q1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 0 1 0
T-FF Excitation T8 T4 T2 T1 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 0 1
Chapter 5 Part 2 21
Synchronous BCD (Continued)
What does the complete state diagram look like?
2 1 0 15 14 4 13 12 5 10 11 8 7
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
3
How does the sequential
machine get into some of the states?
9
6
Chapter 5 Part 2 22
11
Counter with Parallel Load
COUNT
Common Logic
LOAD
If we replace the T flip-flop
with a JK flip-flop and some other logic, we can introduce a Hold function and a Parallel Load function.
Bas ic Cell
In
J Q
This basic cell replaces the
T-FFs from before. Note that the "T" input can be used as a normal T-FF if LOAD is low and COUNT is high. The clock, CP, and CLEAR lines are tied to all flip-flops.
Chapter 5 Part 2 23
"T"
K Q CLR
Loa d a nd Count To Othe r Ce lls
CP
CLEAR
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Counting Modulo N
The Load feature can be used to preset the counter
synchronously on command.
The Clear feature can asynchronously reset the counter to
zero. (This can lead to counts which are present only a very short time).
By detecting a "terminal" count of N-1 in a Modulo-N count
sequence, we can synchronously load in "zero" to start over.
By detecting a "terminal" count of N in a Modulo-N count
sequence, we can clear the count asynchronously to "zero" to start over.
Alternatively, we can detect the "all-ones" terminal count
and use load to preset a count of the maximum count value minus (N-1).
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 24
12
Counting Modulo 7
A synchronous 4-bit
binary counter with a synchronous load and an asynchronous clear is to be used to make a Modulo 7 counter.
"0" "0" "0" "0"
CLOCK
IN8
IN4
Q8 Q4 Q2 Q1
IN2
IN1 CP
Use the Load feature to
detect the count "6" and load in "zero". This gives a count of 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 0.... etc.
LOAD
"1"
CLEAR
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 25
Counting Modulo 7, Asyn.Clear
A synchronous 4-bit
binary counter with a synchronous load and an asynchronous clear is to be used to make a Modulo 7 counter. Use the Clear feature to detect the count "7" and clear the count to "zero". This gives a count of 0, 1, 2, 3, 4, 5, 6, 7(short)0, 1, 2, 3, 4, 5, 6, 7(short)0, etc.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
IN8 IN4 IN2 IN1
CLOCK
Q8 Q4 Q2 Q1
CP LOAD CLEAR
"0"
DON'T DO THIS! Referred to as a "suicide" counter!
Chapter 5 Part 2 26
13
Counting Modulo 7, Preset 9
A synchronous, 4-bit
binary counter with a synchronous load and an asynchronous clear is to be used to make a Modulo 7 counter.
"1" "0" "0" "1"
CLOCK
IN8 IN4 IN2 IN1 CP
Q8 Q4 Q2 Q1
Use the Load feature to
LOAD
preset the count to "9" CLEAR "1" when you detect the count "15". This gives a count of 9, 10, 11, 12, 13, 14, 15, 9, 10, 11, 12, 13, 14, 15, 0, .... etc. Sometimes the "Detect 15" is built in to the counter.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 5 Part 2 27
Timing Sequences
For digital systems, useful to generate a multi-phase
sequence of timing signals to perform different functions at different intervals. There are many ways to do this.
Here are a few that start with a clock and use a
"counter" to divide the clock into separate phases.
Counter/Decoder - connect the output of a counter to a decoder. Ring Counter - shift a single pulse down a chain of flip-flops connected as a shift register. For "N" phases, use "N" ...