LOOPING Filename="ch10.doc"
10.0 Constructs
10.1 LOOP Statement
There are three types of loops: FOR, WHILE, and LOOP-EXIT. Autologic VHDL only supports theFOR loop construct.
10.1.1 FOR Loop
Format: [label:] FOR loop_parameter IN discrete_range LOOP --sequential_statements END LOOP [label]; Sequential statements are executed once for each value in loop parameter's range. Loop parameter is implicitly declared and may not be modified within loop or used outside loop. Implicitly declared means there does not have to be a variable declaration. The discrete_range can be subrange of integer or enumeration type.
Example: PROCESS(signal_a) BEGIN label_1: FOR index IN 0 TO 7 -- index is implicitly declared LOOP ray_out(index) <= ray_in(index); END LOOP label_1; END PROCESS;
10.1.2 WHILE Loop
Format: [label]: WHILE boolean_expression LOOP -- sequential_statements END LOOP [label]; boolean_expression is evaluated before each repetition of loop.
Example: P1: PROCESS(signal_a) VARIABLE index:INTEGER:=0; BEGIN while_loop: WHILE index < 8 LOOP ray_out(index) <= ray_in(index); index:=index+1; END LOOP while_loop; END PROCESS P1;
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Loop parameter is explicitly declared and can be any scalar type. If the loop parameter index in the above example is of type real, the corresponding boolean expression would be Index < 8.0 and the increment would have to be index:=index +1.0;
10.1.3 LOOP-EXIT Construct
Format: LOOP -- sequential_statements -- including decision_to_quit END LOOP; Does not contain an iteration scheme specifying how loop terminates. A decision to leave loop must be made from within loop. Can be terminated from within by: EXIT, NEXT
10.1.4 EXIT statement
Used to break out of loops Only occurs whithin loops Format: EXIT; EXIT loop_label; EXIT WHEN boolean_expression; EXIT loop_label WHEN boolean_expression EXIT command takes effect as soon as it is executed. Statements which appear after EXIT are not executed.
Example: show_loops: PROCESS(s) VARIABLE sum,cnt:INTEGER :=0; BEGIN sum:=0; cnt:=0; first:LOOP cnt:=cnt+1; sum:=sum+cnt; EXIT WHEN sum > 100; END LOOP; second:LOOP cnt:=cnt+1; sum:=sum+cnt; IF cnt>100 THEN EXIT; END IF; END LOOP; END PROCESS show_loops; NOTE: It is necessary to reset the variable sum and cnt to zero, even if their initial value is zero. Since, the initial value is not a reset value. It occurs only the first time the loop executed. Thereafter, each time the process is entered the value of the variable will be equal to the value assigned to the variable the last time the process was exited.
10.1.5 NEXT statement
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Causes completion of one of the iterations of an enclosing loop. Format: NEXT; NEXT loop_label; NEXT WHEN boolean_expression; NEXT loop_label WHEN boolean_expression;
Example: next_xmpl: PROCESS(s) VARIABLE temp,j:INTEGER:=0; BEGIN temp:=0;j:=0; a_loop:FOR j IN 0 TO 7 LOOP j:=j+1; IF j>5 THEN NEXT a_loop; END IF; temp:=temp+1; END LOOP a_loop; END PROCESS next_xmpl; NEXT without loop label causes the next iteration of the loop it is contained in to be executed. Control still remains within the loop's iteration scheme. Loop label can refer to the label on any loop enclosing the NEXT statement. The NEXT statement causes completion of the current iteration. Statements which follow the NEXT are not executed. Control is transferred to the beginning of the loop and the next iteration is started.
Example: a four-to-sixteen decoder can easily be modeled and synthesize using the FOR loop. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PACKAGE my_intgr IS SUBTYPE my_int IS INTEGER RANGE 0 TO 1; END my_intgr; LIBRARY IEEE, ARITHMETIC; USE IEEE.STD_LOGIC_1164.ALL; USE ARITHMETIC.STD_LOGIC_ARITH.ALL; USE WORK.my_intgr.ALL; ENTITY dec4_16 IS PORT(in_array: IN ARRAY(0 TO 3) OF my_int; out_array: OUT ARRAY(0 TO 15) OF my_int); END dec4_16; ARCHITECTURE archdec4_16 OF dec4_16 IS BEGIN PROCESS(in_array) VARIABLE index: INTEGER RANGE 0 TO 15; BEGIN index :=0; FOR i IN in_array'RANGE LOOP index := index + (2**i)*in_array(i);
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END LOOP; FOR j IN 0 TO 15 LOOP out_array(j) <=0; END LOOP; out_array(index) <= 1; END PROCESS; END archdec4_16;
NOTE: the use in_array'RANGE attribute to determine the index range. in_array is an array of type integer with range 0 to 1.
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0 4_to_16 3 decoder
0 1 out_array
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10.2.1 Variable Use With Conditionals
When assigning to variables with conditional assignments, you must ensure that the variable is always assigned to, otherwise AutoLogic VHDL stops during compilation with an unsynthesizeable internal state error. AutoLogic VHDL does not build transparent latches for variables. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 16 17 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY varx IS PORT(in :IN STD_LOGIC; out : OUT STD_LOGIC); END varx; ARCHITECTURE archvarxOF varx IS BEGIN PROCESS(in) VARIABLE x:STD_LOGIC; BEGIN IF(in=`1') THEN x:=`1'; ELSIF (in=`0') THEN x:=`0'; END IF; out <=x; END PROCESS; END archvarx;
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Note x is a STD_LOGIC variable, which has nine possible values. Seven values were not accounted for. Since AutoLogic VHDL does not build transparent latches for variables. The above code cannot be synthesized 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY varx IS PORT(in :IN STD_LOGIC; out : OUT STD_LOGIC); END varx; ARCHITECTURE archvarxOF varx IS BEGIN PROCESS(in) VARIABLE x:STD_LOGIC; BEGIN IF(in=`1') THEN x:=`1'; ELSE x:=`0'; END IF; out <=x; END PROCESS; END archvarx;
NOTE x is now always defined. This code is now synthesizeable.
If replaced variable x to signal x . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY sigx IS PORT(in :IN STD_LOGIC; out : OUT STD_LOGIC); END sigx; ARCHITECTURE archsigxOF sigx IS SIGNAL x : STD_LOGIC; BEGIN PROCESS(in) BEGIN IF(in=`1') THEN x<=`1'; ELSE x<=`0'; END IF; out <=x; END PROCESS; END archvarx;
In line 17 if x is a signal, it must also appears in the process sensitivity list, otherwise the new value of x will not be assigned to out. NOTE a variable cannot appears in the process sensitivity list. The above code is still not synthesizeable.
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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY sigx IS PORT(in :IN STD_LOGIC; out : OUT STD_LOGIC); END sigx; ARCHITECTURE archvarxOF varx IS SIGNAL x : STD_LOGIC; BEGIN PROCESS(in, x) BEGIN IF(in=...