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Course: EECS 443, Fall 2009
School: E. Kentucky
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443 EECS - Digital Systems Design Spring Semester, 2009 January 15, 2009 Description Digital systems design is an introduction to design of modern digital hardware systems. Students will learn the basics of RTL design and apply these techniques to the design and implementation of computer systems components. Students will also learn basic VHDL design techniques including simulation and FPGA synthesis. In the...

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443 EECS - Digital Systems Design Spring Semester, 2009 January 15, 2009 Description Digital systems design is an introduction to design of modern digital hardware systems. Students will learn the basics of RTL design and apply these techniques to the design and implementation of computer systems components. Students will also learn basic VHDL design techniques including simulation and FPGA synthesis. In the laboratory course, students will apply techniques presented in the lecture to the design of a complex computing system. Class Time: Location: Instructor: 9:30-10:45 TR 3153 Learned Hall Dr. Perry Alexander 2022 Eaton Hall - 864-8833 136 Nichols Hall - 864-7741 palexand@eecs.ku.edu http://www.ittc.ku.edu Ofce Hours: Texts Computer Organization and Design, David Patterson and John Hennessy, Morgan Kaufmann Publishers, 2008, 4th edition. (Required) The Students Guide to VHDL, Peter Ashenden, Morgan Kaufmann Publishers, 2008, 2nd edition. (Required) 10:45-12:00 TR, 2022 Eaton Hall or by appointment Grading Semester grades will be assigned on a standard 10 point scale. I may curve nal grades at the end of the semester. However, I will never curve individual assignments or exams. If I curve and how much I curve is at my discretion. However, I will never curve up 90% and above will always be an A. Classroom tasks are divided into exams and assignments, each of which are worth 50% of your nal grade. Your Midterm Exam will be worth 20% and the Final Exam 30%. You must average 60% on your exams after any curve to pass the course. Your laboratory assignments will be worth 40% and any homework assignments will be worth 10%. Again, you must average 60% on your laboratory assignments and homework assignments to pass the course. 90-100% 80-90% 70-80% 60-70% 0-60% A B C D F Midterm Exam Final Exam Homework Lab Projects 20% 30% 10% 40% eecs 443 - digital systems design 2 Homework Homework will be due on approximately a bi-weekly basis. Unless otherwise noted, all homework is due at the beginning of the class period indicated on the web page. If the due date is a holiday and KU ofces are closed, the due date becomes the next class period. Late homework assignments are not accepted. You must turn in 70% of your assignments on time to receive a passing grade in the course. If you have a valid excuse for being late, a new due date will be assigned. Your homework assignments will be returned in your laboratory section and will be graded by the TAs. Projects Please submit your lab assignments by sending them to your TA in email. We will not accept paper listings. The TAs will extract your simulation models and run them on their computers. Please document your VHDL source les with your name and ID number. Undocumented VHDL les will result in a serious point deduction. On several occasions you will be asked to synthesize your designs to FPGAs. In such cases, you will be required to demonstrate your laboratory to your TA as well as turn in your VHDL designs. You must turn in 70% of your lab assignments on time to receive a passing grade in the course. If you have a valid excuse for being late, a new due date will be assigned. Your laboratory assignments will be returned in your laboratory section and will be graded by the TAs. Web Repository All homework assignments, exams, solutions and handouts you receive in class are linked to the EECS 443 homepage. In general, I will not distribute hard copies of labs and homework assignments in class. All documents will be published using the Adobe PDF standard. PDF readers are freely available for Windows, Linux, and MacOS on the Adobe website. http://www.ittc.ku.edu/~alex/ teaching/eecs443/ eecs 443 - digital systems design 3 Policies Generally, I am quite easy to get along with and I will help however I can. However, I do have are a few things that you should keep in mind during the class that will help us get along.1 Class Participation I do not take attendance in class, however participation in class is important to its success. Please ask questions and participate in class discussions. When assigning nal grades, borderline cases will decided be based on class participation. Grading Errors If the TAs or I have made an error in grading an exam or assignment, you have two weeks following the date the item is returned to see me about correcting the problem. After that time, your grade is set and will not be changed. I also request that you wait 24 hours after an exam is returned before coming to me with questions. Curving I may decide to curve nal scores when the quarter is over. I will never curve up, but may curve down. Specically, 90% and above will always be an A, but I may choose to lower the cutoff percentage. Whether I curve and how much I curve is at my discretion. I will never curve scores on an individual assignment, lab or exam. Email I encourage you to use email to contact me it is by far the easiest way to nd me. I am logged in when I am working and check my mail frequently. Blog The course blog is available on the website and via an RSS feed. I will post late-breaking news about projects, homework and class administration on the blog. Either subscribe, or check the website frequently. Phone Feel free to call me in my ofce at any time. I would prefer not to be called at home. Office Hours I will make every effort to be in my ofce during scheduled ofce hours. If there are exceptions, I will let you know as early as is possible. If you have a conict with my ofce hours, please make an appointment or stop by my ofce at another time. I have an open door policy, you are free to come by whenever 1 The 4 Commandments: Do not whine Do not cheat Do not disrespect the TAs Do not tell me what you dont need to know eecs 443 - digital systems design 4 you choose. If I am busy, I may ask that you come back later, but please dont hesitate to knock! My schedule is available online. Cheating Academic misconduct of any kind will automatically result in a 0 score on the homework, lab, project, or exam in question and your actions will be reported to the department chair. Your homework, exams and projects must be individually prepared unless otherwise noted. Posting your assignments to Internet discussion lists is considered academic misconduct. Sharing your solutions with others is considered academic misconduct. Turning in solutions from previous semesters is considered academic misconduct. Paying people to prepare solutions is academic misconduct. Automated mechanisms are available for checking the originality of source code. Please spend your time trying to solve assigned prob...

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