443 EECS Digital Systems Design
Homework 2 Spring 2009
RISC processing is based on the principle that a small number of highly efcient operations is more effective than many complex, special purpose instructions. Thus, we need to start thinking about how typical operations can be implemented using RISC instructions.
Exercise 1 Use the instruction set of KURM09 to implement the following two operations: 1. Load R11 with the contents of the memory location stored in R12 . (Register direct) 2. Load R11 with the contents of the memory location stored in the memory location stored R12 . (Register indirect addressing) 3. Copy the contents of the memory location stored in R11 to the memory location stored in R12 . (Memory move) 4. Copy the contents of R10 words of memory starting with the address stored in R11 to the memory location starting with R12 . (Block memory move) 5. Increment R15 by 2. (Standard increment operation) 6. Branch to the address PC + 8 if the contents of R11 are less than 0. (BLZ in many instruction sets) 7. Branch to the address PC + 8 if the contents of R11 are greater than 1. (BGT in many instruction sets) 8. Simulate a stack push by treating the contents of R12 as data to be pushed on a stack in memory whose top is pointed to by R15 . Your stack should grown down in memory. (Set up for a function call.) 9. Redo the previous problem as a subroutine. Show an example call to your subroutine. Assume that the return address for the subroutine will be stored in R14 . (Subroutine denition.) 10. Simulate a stack pop by moving the top element of a stack pointed to by R15 into R12 . On the stack-based problems, remember to update the stack pointer after all operations.
Instruction add Rs ,Rt ,Rd sub Rs ,Rt ,Rd or Rs ,Rt ,Rd and Rs ,Rt ,Rd set Rs ,Rt ,msk bra msk,o lw Rs ,Rt ,o sw Rs ,Rt ,o jmpl Rs ,Rt ,o f f
Meaning Rd := Rs + Rt Rd := Rs Rt Rd := Rs Rt Rd := Rs Rt set status msk if (msk status) = 0 pc := pc + o Rt := M ( Rs + o ) M ( Rs + o ) := Rt Rt := PC + o PC := Rs
Table 1: KURM instruction set
Exercise 1 is designed to show you the code that would be generated by a compiler for some common run-time operations and to demonstrate we that only need 1 addressing mode per operand for any instruction.
eecs 443 digital systems design
2
architecture beh of cpu is begin CPU: process M : array of word; R11,R12,R13 : word; PC : word; begin ... end process CPU; end architecture beh;
Figure 1: VHDL skeleton for a CPU process.
Exercise 2 Assume the VHDL fragment in gure 1 representing the skeleton of a simple CPU model. Using VHDL statements, dene behaviors for the following operators and memory addressing modes: (Note that you need to indicate only the VHDL needed to implement the function. You may assume that word addition and comparison functions exist. These are not necessarily instructions that are dened for KURM09.) 1. lw R11 #99 - Load R11 with the value 99. 2. lw R11 R12 - Load R11 from the address stored in R12 3. lw R11 ( R12 ) - Load R11 from the address stored in the memory location at the address in R12 4. sw R11 R13 ( R12 ) - Store R11 using register indirect addressing with an offset stored in R13 . 5. add R12 R13 R11 - Add contents of R12 and R13 storing the result in R11 6. inc R11 - Increment R11 by 1 7. mov R11 R12 - Move the contents of R11 into R12 8. push R11 R12 - Treating the address stored in R12 as the top of a stack, push the value in R11 and update R12 appropriately 9. bze R11 R12 - Jump to the ...