Organization
CS/COE Memory 1541
Memory Topics: Structure of Memory!
1. 2. 3. 4. Memory chip Memory chip structure Memory cell structure Memory module Start with high level view, then low level based on the particular memory cell structure End with how to build a memory module
1
Basic Memory Block
Address & data lines (m-bit address, w-bit data) Data is bidirectional Assert CS to select chip Assert WR to write data
WR
Address A0-Am-1
Memory Chip
Data D0-Dw-1
CS
Memory Structure
Memory cell holds one bit of information 1D or 2D array of memory cells May be stacked Each array provides one bit of data Types of memory cells SRAM - Static RAM (flip flop) DRAM - Dynamic RAM (capacitor)
2
Memory Cell
Basic RAM cell READ D flip-flop with some control D Q Flip-flop signals CLK: Active for CLK writing SELECT D: Input data Q: Output data
Data in/out
Memory Cell
To read READ=0, SELECT=1 Output driver activated To write READ=1, SELECT=1 CLK asserted Data input on D
READ D Q CLK SELECT
ENB
Data in/out
ENB
3
One and two dimensional memory units
Data bus (in/out) w bits Data bus (in/out) 1 bit
m x 2m Address decoder
r x 2r row Address decoder 2m x w Memory cells
2r x 2c Memory cells (one bit words)
m
w bits Address bus
r
c
c x 2c Column address decoder
m Address bus
Example
256K x 1 memory Memory reads/writes one bit 256K memory cells in the memory 256K = 2^18 so there are 18 address bits Total size is (256K * 1) / 8 = 32 Kbytes 64K x 4 memory Memory reads/writes four bits 64K memory cells in the memory 64K = 2^16 so there are 16 address bits Total size is (64K * 4) / 8 = 32 Kbytes
4
Specific Memory Technologies: SRAM vs. DRAM
Cell organization Cell structure Building memory chips
Static RAM
Structure Uses flip-flop structure (inverting gates) Retains value while powered on Feature Very fast but big (poor density) 6 transistors Usage Caches typically SRAMs
5
SRAM Structure
4x2 SRAM 4 2-bit words Components 2-to-4 decoder 8 1-bit cells Input & output Word lines Select row Bit lines Data input/output
D1 D0 D C E Q D C E Q
Write Enable
D C E A1 A0 D C E
Q
D C E
Q
Q
D C E
Q
D C E Q
D C E Q
Q1
Q0
Dynamic RAM
Structure Word line Uses capacitor Pass transistor Charge level indicates 0 or 1 Capacitor Leaks, requires regular refresh Features Very dense Slow compared to SRAM (5-10X slower) Usage Main memory
Bit line
6
Writing to DRAM cell
Steps Assert word line (turn the pass transistor Write on) value to bit line
If the value is 1, the capacitor will be charged If the value is 0, the capacitor will be discharged
Word line Pass transistor Capacitor Bit line
Reading DRAM cell
Steps Bit line charged 1/2 betw. low and high voltage Assert word line Value in capacitor is read out onto the bit line Bit line swings slightly to low or high Sense amp detects swing and indicates a 0 or 1 B/C charge used in detection, rewrite after read
Word line Pass transistor Capacitor Bit line
7
Basic DRAM Structure
Two level decoding Row access Column access Row access goes into decoder to select row Column access controls the mux
A10-A0
11-to2048 Row Decoder
2048x2048 array
Column Latches
MUX
D0
An implementation of a 4Mx8-bit DRAM
Data buffer (8-bits in/out)
11
11 x 2048 Row address decoder
2048 x 2048 array of cells
8 arrays
22
Address lines
11
11 x 2048 Column address decoder
8
DRAM Structure (16Mbit using 4Mx4)
RAS CAS WE OE Timing and Control
Refresh Counter
A0
Row Address Buffer
MUX
Row Decoder
Memory Array (2048x2048x4)
...
...
A10 Column Address Buffer
...
Sense Amp Column Decoder
Data Input Buffer Data Output Buffer
D0 D3
Examples of building memory chips
Build an SRAM 8x4 chip (using a 3-to-8 row decoder), Build an DRAM 8x2 chip using a row and a column decoder Build a DRAM 64x4 chip using a square array of cells, Build a DRAM 32Kx8 chip.
9
Building Memory Modules from Memory Chips
Note: Module is made ...