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homework5

Course: CS 6290, Fall 2008
School: Georgia Tech
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INSTITUTE GEORGIA OF TECHNOLOGY College of Computing CS6290/CS4290 High-Performance Computer Architecture Spring 2003 CS6290/CS4290 Homework 5 Issued: March 8, 2003 Due: April 4, 2003 Purpose: Reading: This homework introduces issues in network performance. H&P Chapter 8 [Kubi93] paper 1. Eective Bandwidth. 2. Topology. 3. Reading: [Kubi93]. (As in the syllabus) collaboration on projects and homework...

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INSTITUTE GEORGIA OF TECHNOLOGY College of Computing CS6290/CS4290 High-Performance Computer Architecture Spring 2003 CS6290/CS4290 Homework 5 Issued: March 8, 2003 Due: April 4, 2003 Purpose: Reading: This homework introduces issues in network performance. H&P Chapter 8 [Kubi93] paper 1. Eective Bandwidth. 2. Topology. 3. Reading: [Kubi93]. (As in the syllabus) collaboration on projects and homework in pairs is encouraged. If you work in a pair, turn in one write-up with the names of both collaborators. Youre welcome to discuss high-level concepts with other groups, but all homework solutions must be worked out and written up separately. Problems: Collaboration: Problem 1: Eective Bandwidth A: B: C: D: Problem 8.1 in the book. Problem 8.2 in the book. Problem 8.3 in the book. Problem 8.4 in the book. CS6290/CS4290 Spring 2003 1 March 8, 2003 Problem 2: Topology Assume you have to connect 64 nodes, each with and input and an output link. You have available 16x16 switches that each have 16 inputs and 16 outputs. Assume that the latency through a switch (or node) is one unit of time and that the bandwith of a link is one unit. A: The lowest-cost network has no switches instead you connect the 64 nodes into a ring. What is the bisection bandwidth of the network? What is the average message latency between randomly selected pairs nodes? of B: Using 16x16 switches, design a switch topology that has the minimum latency through the switches. Sketch the topology. How many switches are required? What is minimum latency? What is the bisection bandwidth of your topology? Problem 3: Reading Read the [Kubi93] paper on the Alewife message passing mechanism. A: Figure 8 shows the instruction sequence for composing and launching a message with a one-word payload of data where the data is written directly out of a register. Show the sequence for sending a message with an additional payload of 256 bytes from location foo in memory. B: Figure 8 also shows the detailed pipeline timing for launching a message: three cycles per stio plus one cycle for the ipilaunch plus two cycles of overhead. The processor runs at 33MHz; the network is byte-wide an...

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