2030 ECE 1:00pm 4 problems, 4 pages Problem 1 (2 parts, 24 points)
Computer Engineering Exam Three Solutions
Fall 2006 29 November 2006 Counters
Part A (12 points) Design a toggle cell using transparent latches and basic gates. Use an icon for the latch. Your toggle cell should have an active high toggle enable input TE, and an active low clear input -Clear, clock inputs 1 and 2, and an output Out. The -Clear signal has precedence over TE. Label all signals.
TE CLR
In Out Latch En
In Out Latch En
Out
1
2
Part B (12 points) Now combine these toggle cells to build a divide by seven counter. Your counter should have an external clear, external count enable, and three count outputs O2, O1, O0. Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the toggle cells are already connected. Your design should support multi-digit systems.
Ext CE
TE Out Clr
O0
TE Out Clr
O1
Ext Clr
TE Out Clr
O2
1
ECE 2030 1:00pm 4 problems, 4 pages Problem 2 (2 parts, 18 points)
Computer Engineering Exam Three Solutions
Fall 2006 29 November 2006 Datapath Elements
Part A (9 points) Consider the following input and output values for a shift operation. Determine the shift type and amount required to achieve the listed transformation. There are no overflows. Input Value Output Value Shift Type Shift Amount (signed decimal value) 87654321 87654321 87654321 54321876 FFFF8765 76543210 rotate arithmetic logical -12 or +20 bits +16 bits -4 bits
Part B (9 points) Consider the following input and output values for a logical operation. Determine the logical function and function code (in hexadecimal) required for the operation. X Input Y Input Output Logical Function Function Code 12345678 12345678 12345678 0F0F0F0F 0F0F0F0F 0F0F0F0F 1F3F5F7F 02040608 1D3B5977 OR AND XOR E 8 6 Memory Systems
Problem 3 (3 parts, 31 points)
Part A (10 points) Consider a 1 Gbit DRAM chip organized as 16 million addresses of 64 bit words. Assume both the DRAM cell and the DRAM chip is square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal. number of columns column decoder required (n to m) type of mux required (n to m) number of muxes required number of address lines in column number number of address lines in column offset square root (1G = 230) = 215 = 32K 15 to 32K 32K/64 = 512 to 1 mux 64 muxes 15 9
Part B (10 points) Consider a 2 Gbyte memory system with 128 addresses million of 16 byte words using 1 Gbit DRAM chips organized as 16 million addresses by 64 bit words. word address lines for memory system chips needed in one bank banks for memory system memory decoder required (n to m) DRAM chips required 27 16 bytes/word / 8 bytes/chip = 2 chips 128M / 16M = 8 banks/sys 3 to 8 2 chips/bank x 8 banks = 16 chips
2
ECE 2030 1:00pm 4 problems, 4 pages
Computer Engineering Exam Three Solutions
Fall 2006 29 November 2006
Part C (11 points) Design a 24M address x 8 bit memory system with six 8M address x 4 bit memory chips. Label all busses and indicate bit width. Assume R/W is connected and not shown here. Use a decoder if necessary. Place a star on the chip(s) that contain address 10,000.
25 ADDR 2 A23 A24 S0 S1 23 23 A22:0 ADDR D0 8M x 4 D1 D2 CS 23 D3
O0
O1 2 to 4 decoder O2 EN O3
ADDR D0 8M x 4 D1 D2 CS 23 D3 D0 D1 D2 D3 D4 D5 D6 D7
ADDR D0 8M x 4 D1 D2 CS 23 D3
ADDR D0 8M x 4 D1 D2 CS 23 D3
ADDR D0 8M x 4 D1 D2 CS 23 D3
ADDR D0 8M x 4 D1 D2 CS D3
MSEL
3
ECE 2030 1:00pm 4 problems, 4 pages Problem 4 (3 parts, 27 points)
Computer Engineering Exam Three Solutions
Fall 2006 29 November 2006 Microcode
Using the supplied datapath, write microcode fragments to accomplish the following procedures. Express all values in hexadecimal notation. Use `X' when a value is don't cared. For maximum credit, complete the description field. Recall that means XOR. Use only registers 1, 2, and 3. 4 R1 + ( R2 R3 ) - 5 Part A (15 points) R1 = . 8
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