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EECS Review 150 - Components and Design Techniques for Digital Systems Lec 04 Hardware Description Languages / Verilog 9/6/2007 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://inst.eecs.berkeley.edu/~cs150 UC Berkeley 9/6/2007 Advancing technology changes the trade-offs and design techniques 2x transistors per chip every 18 months ASIC, Programmable Logic, Microprocessor Programmable logic invests chip real-estate to reduce design time & time to market Canonical Forms, Logic Minimization, PLAs, FPGA: programmable interconnect, configurable logic blocks LUT + storage Block RAM IO Blocks UC Berkeley EECS 150, Fa07, Lec 04-HDL 2 Outline Netlists Design flow What is a HDL? Verilog Announcements Structural models Behavioral models Elements of the language Lots of examples Remember: to design is to represent How do we represent digital designs? Components Logic symbol, truth table Storage symbol, timing diagram Connections Schematics Human readable or machine readable??? 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 3 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 4 Design Flow Design Entry High-level Analysis Netlist A key data structure (or representation) in the design process is the netlist : Network List Alternative format: n1 g1.in1 n2 g1.in2 n3 g2.in1 n4 g2.in2 n5 g1.out g3.in1 n6 g2.out g3.in2 n7 g3.out g1 "and" g2 "and" g3 "or" A netlist lists components and connects them with nodes: ex: n1 n2 n3 n4 g1 g2 n5 g3 n6 n7 Technology Mapping Low-level Analysis 9/6/2007 g1 "and" n1 n2 n5 g2 "and" n3 n4 n6 g3 "or" n5 n6 n7 Netlist is needed for simulation and implementation. Could be at the transistor level, gate level, ... Could be hierarchical or flat. How do we generate a netlist? EECS 150, Fa07, Lec 04-HDL 6 UC Berkeley EECS 150, Fa07, Lec 04-HDL 5 9/6/2007 UC Berkeley Design Flow Design Entry High-level Analysis Circuit is described and represented: Graphically (Schematics) Textually (HDL) Design Flow Design Entry High-level Analysis High-level Analysis is used to verify: correct function rough: timing power cost Result of circuit specification (and compilation) is a netlist of: generic primitives - logic gates, flip-flops, or technology specific primitives LUTs/CLBs, transistors, discrete gates, or higher level library elements adders, ALUs, register files, decoders, etc. 7 9/6/2007 Common tools used are: Technology Mapping Low-level Analysis 9/6/2007 Technology Mapping Low-level Analysis UC Berkeley simulator - check functional correctness, and static timing analyzer estimates circuit delays based on timing model and delay parameters for library elements (or primitives). UC Berkeley EECS 150, Fa07, Lec 04-HDL EECS 150, Fa07, Lec 04-HDL 8 Design Flow Design Entry High-level Analysis Technology Mapping: Converts netlist to implementation technology dependent details Expands library elements, performs: partitioning, placement, routing Design Flow Design Entry High-level Analysis Netlist: used between and internally for all steps. Low-level Analysis Technology Mapping Low-level Analysis 9/6/2007 Simulation and Analysis Tools perform low-level checks with: accurate timing models, wire delay For FPGAs this step could also use the actual device. Technology Mapping Low-level Analysis 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 9 UC Berkeley EECS 150, Fa07, Lec 04-HDL 10 Design Entry Schematic entry/editing used to be the standard method in industry Used in EECS150 until recently Schematics are intuitive. They match our use of gate-level or block diagrams. Somewhat physical. They imply a physical implementation. Require a special tool (editor). Unless hierarchy is carefully designed, schematics can be confusing and difficult to follow. 9/6/2007 HDLs Basic Idea: Language constructs describe circuits with two basic forms: Structural descriptions similar to hierarchical netlist. Behavioral descriptions use higherlevel constructs (similar to conventional programming). Originally designed to help in abstraction and simulation. Structural example: Decoder(output x0,x1,x2,x3; inputs a,b) { wire abar, bbar; inv(bbar, b); inv(abar, a); nand(x0, abar, bbar); nand(x1, abar, b ); nand(x2, a, bbar); nand(x3, a, b ); } Hardware Description Languages (HDLs) are the new standard except for PC board design, where schematics are still used. 11 Now logic synthesis tools exist to automatically convert from behavioral Behavioral example: descriptions to gate netlist. Decoder(output x0,x1,x2,x3; inputs a,b) Greatly improves designer productivity. { However, this may lead you to falsely case [a b] believe that hardware design can be 00: [x0 x1 x2 x3] = 0x0; reduced to writing programs! 01: [x0 x1 x2 x3] = 0x2; 10: [x0 x1 x2 x3] = 0x4; 11: [x0 x1 x2 x3] = 0x8; endcase; 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL UC Berkeley } EECS 150, Fa07, Lec 04-HDL 12 Design Methodology Structure and Function (Behavior) of a Design Quick History of HDLs ISP (circa 1977) - research project at CMU Simulation, but no synthesis HDL Specification Abel (circa 1983) - developed by Data-I/O Targeted to programmable logic devices Not good for much more than state machines Simulation Verification: Design Behave as Required? Functional: I/O Behavior Register-Level (Architectural) Logic-Level (Gates) Transistor-Level (Electrical) Timing: Waveform Behavior Verilog (circa 1985) - developed by Gateway (now Cadence) Similar to Pascal and C, originally developed for simulation Fairly efficient and easy to write 80s Berkeley develops synthesis tools IEEE standard Similar to Ada (emphasis on re-use and maintainability) Simulation semantics visible Very general but verbose IEEE standard Synthesis Generation: Map Specification to Implementation VHDL (circa 1987) - DoD sponsored standard 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 13 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 14 Verilog Supports structural and behavioral descriptions Structural Explicit structure of the circuit How a module is composed as an interconnection of more primitive modules/components E.g., each logic gate instantiated and connected to others Verilog Introduction the module describes a component in the circuit Two ways to describe: Structural Verilog List of components and how they are connected Just like schematics, but using text A net list Behavioral Program describes input/output behavior of circuit Many structural implementations could have same behavior E.g., different implementations of one Boolean function tedious to write, hard to decode Essential without integrated design tools Behavioral Verilog Describe what a component does, not how it does it Synthesized into a circuit that has this behavior Result is only as good as the tools Build up a hierarchy of modules 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 15 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 16 Structural Model - XOR module name Structural Model: 2-to1 mux port list module xor_gate ( out, a, b ); input a, b; output out; wire abar, bbar, t1, t2; Built-in gates declarations statements Notes: //2-input multiplexor in gates comments module mux2 (in0, in1, select, out); module input in0,in1,select; port list output out; declarations wire s0,w0,w1; not (s0, select); and (w0, s0, in0), (w1, select, in1); or (out, w0, w1); endmodule // mux2 t2 in1 s0 w0 18 inverter inverter and_gate and_gate or_gate endmodule Instance name invA (abar, a); invB (bbar, b); and1 (t1, a, bbar); and2 (t2, b, abar); or1 (out, t1, t2); interconnections wire type primitive gates Instance names? List per type A and1 invA t1 or1 out B and2 invB w1 out Composition of primitive gates to form more complex module Note use of wire declaration! 9/6/2007 select in0 17 9/6/2007 By default, identifiers are wires UC Berkeley EECS 150, Fa07, Lec 04-HDL UC Berkeley EECS 150, Fa07, Lec 04-HDL Simple Behavioral Model Combinational logic Describe output as a function of inputs Note use of assign keyword: continuous assignment 2-to-1 mux behavioral description // Behavioral model of 2-to-1 // multiplexor. module mux2 (in0,in1,select,out); input in0,in1,select; output out; // reg out; always @ (in0 or in1 or select) if (select) out=in1; else out=in0; endmodule // mux2 Notes: behavioral descriptions using keyword always followed by blocking procedural assignments Target output of procedural assignments must of of type reg (not a real register) Unlike wire types where the target output of an assignment may be continuously updated, a reg type retains it value until a new value is assigned (the assigning statement is executed). Optional initial statement module and_gate (out, in1, in2); input in1, in2; Output port of a primitive must output out; be first in the list of ports assign out = in1 & in2; endmodule When is this evaluated ? Restriction does not apply to modules in general Sensitivity list 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 19 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 20 Behavioral 4-to1 mux //Does not assume that we have // defined a 2-input mux. Mixed Structural/Behavioral Model Notes: Example 4-bit ripple adder module full_addr (S, Cout, A, B, Cin ); input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin; endmodule module adder4 (S, Cout, A, B, Cin); input [3:0] A, B; input Cin; output [3:0] S; output Cout; wire C1, C2, C3; full_addr full_addr full_addr full_addr endmodule fa0 fa1 fa2 fa3 (S[0], (S[1], (S[2], (S[3], No instantiation Case construct equivalent to nested if constructs. //4-input mux behavioral description module mux4 (in0, in1, in2, in3, select, out); Definition: A structural input in0,in1,in2,in3; description is one where the input [1:0] select; function of the module is defined output out; by the instantiation and reg out; interconnection of sub-modules. always @ (in0 in1 in2 in3 select) case (select) 2 b00: out=in0; 2 b01: out=in1; 2 b10: out=in2; 2 b11: out=in3; endcase endmodule // mux4 9/6/2007 Behavior A behavioral description uses higher level language constructs and operators. Verilog allows modules to mix both behavioral constructs and sub-module instantiation. Structural C1, A[0], B[0], Cin); C2, A[1], B[1], C1); C3, A[2], B[2], C2); Cout, A[3], B[3], C3); UC Berkeley EECS 150, Fa07, Lec 04-HDL 21 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL Order of ports? 22 Announcements Office hours will be posted on schedule.php Homework 1 due tomorrow (2 pm outside 125) Homework 2 out today Feedback on labs, Lab lectures Reading: - these notes - verilog code you see in lab Verilog Help The lecture notes only cover the basics of Verilog and mostly the conceptual issues. Lab Lectures have more detail focused on lab material Textbook has examples. Bhasker book is a good tutorial. http://www.doe.carleton.ca/~shams/97350/PetervrlK.pdf pretty good The complete language specification from the IEEE is available on the class website under Refs/Links http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/verilog2.html 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 23 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 24 Verilog Data Types and Values Bits - value on a wire 0, 1 X - don t care/don t know Z - undriven, tri-state Verilog Numbers 14 - ordinary decimal number -14 - 2 s complement representation 12 b0000_0100_0110 - binary number with 12 bits (_ is ignored) 12 h046 - hexadecimal number with 12 bits Verilog values are unsigned e.g., C[4:0] = A[3:0] + B[3:0]; if A = 0110 (6) and B = 1010(-6) C = 10000 not 00000 i.e., B is zero-padded, not sign-extended Vectors of bits A[3:0] - vector of 4 bits: A[3], A[2], A[1], A[0] Treated as an unsigned integer value e.g. , A < 0 ?? Concatenating bits/vectors into a vector e.g., sign extend B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]}; B[7:0] = {3{A[3]}, A[3:0]}; Style: Use a[7:0] = b[7:0] + c; Not: a = b + c; // need to look at declaration EECS 150, Fa07, Lec 04-HDL 25 9/6/2007 UC Berkeley 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 26 Verilog Operators Verilog Variables wire Variable used simply to connect components together reg Variable that saves a value as part of a behavioral description Usually corresponds to a wire in the circuit Is NOT necessarily a register in the circuit usage: Don t confuse reg assignments with the combinational continuous assign statement! (more soon) Reg should only be used with always blocks (sequential logic, to be presented ) 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 27 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 28 Verilog Module Corresponds to a circuit component Parameter list is the list of external connections, aka ports Ports are declared input , output or inout A B Cin inout ports used on tri-state buses Port declarations imply that the variables are wires module name ports Verilog Continuous Assignment Assignment is continuously evaluated assign corresponds to a connection or a simple component with the described function Target is NEVER a reg variable Dataflow style use of Boolean operators assign A = X | (Y & ~Z); assign B[3:0] = 4'b01XX; bits can take on four values (0, 1, X, Z) variables can be n-bits wide (MSB:LSB) (~ for bit-wise, for ! logical negation) module full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin; endmodule Cout S inputs/outputs assign C[15:0] = 4'h00ff; assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin; use of arithmetic operator multiple assignment (concatenation) delay of performing computation, only used by simulator, not synthesis EECS 150, Fa07, Lec 04-HDL 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 29 9/6/2007 UC Berkeley 30 Comparator Example Comparator Example // Make a 4-bit comparator from 4 1-bit comparators module Compare4(A4, B4, Equal, Alarger, Blarger); input [3:0] A4, B4; output Equal, Alarger, Blarger; wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3; Compare1 Compare1 Compare1 Compare1 cp0(A4[0], cp1(A4[1], cp2(A4[2], cp3(A4[3], B4[0], B4[1], B4[2], B4[3], e0, e1, e2, e3, Al0, Al1, Al2, Al3, Bl0); Bl1); Bl2); Bl3); module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign Equal = (A & B) | (~A & ~B); assign Alarger = (A & ~B); assign Blarger = (~A & B); endmodule When evaluated? What is synthesized? assign Equal = (e0 & e1 & e2 assign Alarger = (Al3 | (Al2 (Al1 & e3 & (Al0 & e3 & assign Blarger = (~Alarger & endmodule 31 & e3); & e3) | e2) | e2 & e1)); ~Equal); What would be a better behavioral version? 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 32 Simple Behavioral Model - the always block always block Always waiting for a change to a trigger signal Then executes the body module and_gate (out, in1, in2); input in1, in2; output out; reg out; always @(in1 or in2) begin out = in1 & in2; end endmodule always Block A procedure that describes the function of a circuit Can contain many statements including if, for, while, case Statements in the always block are executed sequentially blocking assignment Continuous assignments <= are executed in parallel Non-blocking Not a real register!! A Verilog register Needed because of assignment in always block The entire block is executed at once But the meaning is established by sequential interpretation Simulation micro time vs macro time synthesis The final result describes the function of the circuit for current set of inputs intermediate assignments don t matter, only the final result Specifies when block is executed I.e., triggered by which signals 33 begin/end used to group statements 9/6/2007 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL UC Berkeley EECS 150, Fa07, Lec 04-HDL 34 What Verilog generates storage elements? Expressions produce combinational logic Map inputs to outputs State Example module shifter (in, A,B,C,clk); input in, clk; input A,B,C; reg A, B, C; always @ (posedge clk) begin C = B; B = A; A = in; end endmodule clk in A B C Storage elements carries same values forward in time Block interpreted sequentially, but action happens at once 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 35 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 36 State Example2 Non blocking module shifter (in, A,B,C,clk); input in, clk; input A,B,C; reg A, B, C; always @ (posedge clk) begin B <= A; A <= in; C <= B; end endmodule clk in A B C State Example2 interactive quiz module shifter (in, A,B,C,clk); input in, clk; input A,B,C; reg A, B, C; always @ (posedge clk) begin A = in; B = A; C = B; end endmodule clk in A B C Variable becomes a storage element if its value is preserved (carried forward in time) despite changes in variables the produce it. Not whether it is declared as a wire or a reg! Non-blocking: all statements interpreted in parallel Everything on the RHS evaluated, Then all assignments performed 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 37 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 38 Complete Assignments If an always block executes, and a variable is not assigned Variable keeps its old value (think implicit state!) NOT combinational logic latch is inserted (implied memory) This is usually not what you want: dangerous for the novice! Incomplete Triggers Leaving out an input trigger usually results in a sequential circuit Example: The output of this and gate depends on the input history module and_gate (out, in1, in2); input in1, in2; output out; reg out; always @(in1) begin out = in1 & in2; end endmodule What Hardware would this generate? Any variable assigned in an always block should be assigned for any (and every!) execution of the block. 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 39 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 40 Behavioral with Bit Vectors //Behavioral model of 32-bitwide 2-to-1 multiplexor. module mux32 (in0,in1,select,out); input [31:0] in0,in1; input select; Notes: output [31:0] out; inputs, outputs 32-bits wide // reg [31:0] out; always @ (in0 or in1 or select) if (select) out=in1; else out=in0; endmodule // Mux //Behavioral model of 32-bit adder. module add32 (S,A,B); input [31:0] A,B; output [31:0] S; reg [31:0] S; always @ (A or B) S = A + B; endmodule // Add 9/6/2007 Hierarchy & Bit Vectors //Assuming we have already // defined a 2-input mux (either // structurally or behaviorally, Notes: instantiation similar to primitives select is 2-bits wide named port assignment //4-input mux built from 3 2-input muxes module mux4 (in0, in1, in2, in3, select, out); input in0,in1,in2,in3; input [1:0] select; output out; wire w0,w1; mux2 m0 (.select(select[0]), .in0(in0), .in1(in1), .out(w0)), m1 (.select(select[0]), .in0(in2), .in1(in3), .out(w1)), m3 (.select(select[1]), .in0(w0), .in1(w1), .out(out)); endmodule // mux4 Which select? UC Berkeley EECS 150, Fa07, Lec 04-HDL 41 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 42 Verilog if Same syntax as C if statement Sequential meaning, action at once // Simple 4-1 mux module mux4 (sel, A, B, C, D, Y); input [1:0] sel; // 2-bit control signal input A, B, C, D; output Y; reg Y; // target of assignment always @(sel or A or B or C or D) if (sel == 2 b00) Y = A; else if (sel == 2 b01) Y = B; else if (sel == 2 b10) Y = C; else if (sel == 2 b11) Y = D; endmodule 9/6/2007 Verilog if // Simple 4-1 mux module mux4 (sel, A, B, C, D, Y); input [1:0] sel; // 2-bit control signal input A, B, C, D; output Y; reg Y; // target of assignment always @(sel or A or if (sel[0] == 0) if (sel[1] == 0) else else if (sel[1] == 0) else endmodule B or C or D) Y = A; Y = B; Y = C; Y = D; UC Berkeley EECS 150, Fa07, Lec 04-HDL 43 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 44 Verilog case Sequential execution of cases Only first case that matches is executed (no break) Default case can be used // Simple 4-1 mux module mux4 (sel, A, B, C, D, Y); input [1:0] sel; // 2-bit control signal input A, B, C, D; output Y; reg Y; // target of assignment always @(sel case (sel) 2 b00: Y 2 b01: Y 2 b10: Y 2 b11: Y endcase endmodule 9/6/2007 Verilog case Without the default case, this example would create a latch for Y! your generating hardware, not programming Assigning X to a variable means synthesis is free to assign any value // Simple binary encoder module encode (A, Y); input [7:0] A; output [2:0] Y; reg [2:0] Y; (input is 1-hot) // 8-bit input vector // 3-bit encoded output // target of assignment or A or B or C or D) = = = = A; B; C; D; Conditions tested in top to bottom order UC Berkeley EECS 150, Fa07, Lec 04-HDL 45 always @(A) case (A) 8 b00000001: Y 8 b00000010: Y 8 b00000100: Y 8 b00001000: Y 8 b00010000: Y 8 b00100000: Y 8 b01000000: Y 8 b10000000: Y default: Y endcase endmodule 9/6/2007 UC Berkeley = = = = = = = = = 0; 1; 2; 3; 4; 5; 6; 7; 3 bX; // Don t care when input is not 1-hot 46 EECS 150, Fa07, Lec 04-HDL Verilog case (cont) Cases are executed sequentially The following implements a priority encoder // Priority encoder module encode (A, Y); input [7:0] A; output [2:0] Y; reg [2:0] Y; always @(A) case (1 b1) A[0]: Y A[1]: Y A[2]: Y A[3]: Y A[4]: Y A[5]: Y A[6]: Y A[7]: Y default: Y endcase endmodule 9/6/2007 Parallel Case A priority encoder is more expensive than a simple encoder If we know the input is 1-hot, we can tell the synthesis tools parallel-case pragma says the order of cases does not matter // simple encoder module encode (A, Y); input [7:0] A; output [2:0] Y; reg [2:0] Y; always @(A) case (1 b1) A[0]: Y A[1]: Y A[2]: Y A[3]: Y A[4]: Y A[5]: Y A[6]: Y A[7]: Y default: Y endcase endmodule 47 9/6/2007 // 8-bit input vector // 3-bit encoded output // target of assignment // 8-bit input vector // 3-bit encoded output // target of assignment = = = = = = = = = 0; 1; 2; 3; 4; 5; 6; 7; 3 bX; // Don t care when input is all 0 s = = = = = = = = = // synthesis parallel-case 0; 1; 2; 3; 4; 5; 6; 7; 3 bX; // Don t care when input is all 0 s UC Berkeley EECS 150, Fa07, Lec 04-HDL UC Berkeley EECS 150, Fa07, Lec 04-HDL 48 Verilog casex Like case, but cases can include X X bits not used when evaluating the cases In other words, you don t care about those bits! casex Example // Priority encoder module encode (A, valid, Y); input [7:0] A; // 8-bit input vector output [2:0] Y; // 3-bit encoded output output valid; // Asserted when an input is not all 0 s reg [2:0] Y; // target of assignment reg valid; always @(A) begin valid = 1; casex (A) 8 bXXXXXXX1: Y = 8 bXXXXXX10: Y = 8 bXXXXX100: Y = 8 bXXXX1000: Y = 8 bXXX10000: Y = 8 bXX100000: Y = 8 bX1000000: Y = 8 b10000000: Y = default: begin valid = 0; Y = 3 bX; // end endcase end endmodule 0; 1; 2; 3; 4; 5; 6; 7; Don t care when input is all 0 s 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 49 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 50 Verilog for for is similar to C for statement is executed at compile time (like macro expansion) Result is all that matters, not how result is calculated Use in testbenches only! // simple encoder module encode (A, Y); input [7:0] A; output [2:0] Y; reg [2:0] Y; integer i; reg [7:0] test; Another Behavioral Example Computing Conway s Game of Life rule Cell with no neighbors or 4 neighbors dies; with 2-3 neighbors lives module life (neighbors, self, out); input self; input [7:0] neighbors; integers are temporary compiler variables output out; reg out; integer count; always block is executed instantaneously, integer i; if there are no delays only the final result is used always @(neighbors or self) begin count = 0; for (i = 0; i<8; i = i+1) count = count + neighbors[i]; out = 0; out = out | (count == 3); out = out | ((self == 1) & (count == 2)); end endmodule UC Berkeley EECS 150, Fa07, Lec 04-HDL 52 // 8-bit input vector // 3-bit encoded output // target of assignment // Temporary variables for program only always @(A) begin test = 8b 00000001; Y = 3 bX; for (i = 0; i < 8; i = i + 1) begin if (A == test) Y = N; test = test << 1; end end endmodule EECS 150, Fa07, Lec 04-HDL 9/6/2007 UC Berkeley 51 9/6/2007 Verilog while/repeat/forever while (expression) statement Execute statement while expression is true full-case and parallel-case // synthesis parallel_case Tells compiler that ordering of cases is not important That is, cases do not overlap e. g., state machine - can t be in multiple states Gives cheaper implementation repeat (expression) statement Execute statement a fixed number of times forever statement Execute statement forever // synthesis full_case Tells compiler that cases left out can be treated as don t cares Avoids incomplete specification and resulting latches 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 53 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 54 Sequential Logic //Parallel to Serial converter module ParToSer(LD, X, out, CLK); input [3:0] X; input LD, CLK; output out; reg out; reg [3:0] Q; Notes: assign out = Q[0]; always @ (posedge CLK) forces Q always @ (posedge CLK) register to be rewritten every simulation if (LD) Q=X; cycle. >> operator does right shift (shifts in a else Q = Q>>1; zero on the left). endmodule // mux2 module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ (posedge CLK) Q=D; EECS 150, Fa07, Lec 04-HDL 9/6/2007 endmodule // FF UC Berkeley Shifts on non-reg variables can be done with concatenation: wire [3:0] A, B; assign B = {1 b0, A[3:1]} Testbench Top-level modules written specifically to test sub-modules. Generally no ports. module testmux; reg a, b, s; wire f; reg expected; Notes: initial block similar to always except only executes once (at beginning of simulation) #n s needed to advance time $monitor - prints output mux2 myMux (.select(s), .in0(a), .in1(b), .out(f)); A variety of other system functions , similar to monitor exist for displaying output and controlling the simulation. s=0; a=0; b=1; expected=0; #10 a=1; b=0; expected=1; #10 s=1; a=0; b=1; expected=1; end initial $monitor( "select=%b in0=%b in1=%b out=%b, expected out=%b time=%d", s, a, b, f, expected, $time); 56 EECS 150, Fa07, Lec 04-HDL 9/6/2007 UC testmux endmodule // Berkeley initial begin 55 Final thoughts Verilog looks like C, but it describes hardware Multiple physical elements, Parallel activities Temporal relationships Basis for simulation and synthesis figure out the circuit you want, then figure out how to express it in Verilog Understand the elements of the language Modules, ports, wires, reg, primitive, continuous assignment, blocking statements, sensitivity lists, hierarchy Best done through experience Behavioral constructs hide a lot of the circuit details but you as the designer must still manage the structure, data-communication, parallelism, and timing of your design. 9/6/2007 UC Berkeley EECS 150, Fa07, Lec 04-HDL 57

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