Case 6. Study: Formal Verication of RISC Processors using HOL
Page Motivation Hierarchical RISC Model Deriving Formal Specications Verication Tasks Pipeline Correctness Processor Specic Denitions Experimental Results Conclusions References 6.2 6.12 6.13 6.17 6.19 6.27 6.29 6.31 6.32
1994, 2000 S. Tahar
6/7/01
6.1 (of 32)
Motivation Microprocessors containing 5M gates, doubling of frequency per generation, transistor scale by 30% per generation Conventional approaches (simulation, test) cannot guarantee complete correctness In 1994, problems with Intel Pentium and Pentium Pro microprocessors. Cost of correction about $250 M Microprocessors are used in many areas of safety-critical applications Goal: Use of formal hardware verication as a complement approach for achieving design correctness of pipelined microprocessors.
1994, 2000 S. Tahar
6/7/01
6.2 (of 32)
Hardware Verication Model-checking based verication + fully automatic restrictive and the formalism is insufcient for complex circuits Theorem-prover based verication + powerful and unrestricted interactive and usable only by experts Automation can be achieved by restricting to classes of circuits, e.g. arithmetic circuits, signal processors,...
6-tp-case-01.06