1: Page 1. Introduction The last paragraph (We believe alone.) may be removed and the followings can be placed. "The remainder of the paper describes our method and results. Sections 2 introduces background used in this paper. In section 3, our new algorithm, ExorBDS is presented. Experimental methods and results are presented in Section 4. Section 5 discusses future work and concludes the paper." 3. ExorBDS 3.1 ESOP-based Minimization The following paragraphs can be placed in the very beginning of 3.1 esop-based minimization. You may remove "ESOP consists of XORs". "Logic circuits including XOR gates have some advantages over traditional circuits with only AND and OR gates. XOR-based realization can improve the testability [1] and often reduces the circuit area [2]. AND/XOR logical expressions have been studied as the fundamentals of the XOR-based realization. There are several classes of AND/XOR expressions including ESOPs (Exclusive-or Sum of Products expressions) [3]. ESOPs are the expressions such that arbitrary product terms are combined by XORs. Among the classes of AND/XOR expressions, ESOPs are the most general one and require the fewest product terms to represent logic functions." After the above paragraph, "Although " can continue from your draft. Please remove the title "3.2 Exorcism 4". 3.3 BDS -> 3.2 BDS At the very beginning, you may add the following paragraphs just before "BDS -- [3]." "Binary Decision Diagrams (BDDs) were first proposed by Akers [4], and popularized by Bryand [5]. Due to their power to represent Boolean functions, BDDs are considered the most efficient Boolean representation known so far. The synthesis approaches based on decomposition and manipulation of BDD's have been found promising in FPGA synthesis [6]." 3.3 ExorBDS "Our new algorithm figure:" can be place here including figure 1. You may refer that we tried BDS only and Exorcism4 only, respectively, but its performance was poorer than commercial tool's EDA one. Also think about to elaborate this section since this is one of the key sections (Sections 3 & 4) to claim our great performance. 4.2 Results Is there any better name for "direct method" in your mind?
4.3 4LUT -> 4.2.1 4-LUT 4.4 Max -- -> 4.2.2 Max 4.5 Area -- -> 4.2.3 Area 5 Conclusions In second paragraph, "arithmetic circuits, and error-correcting code" -> "computer arithmetic circuits, and error detecting/correcting code" References [2]: It is published. Pp.119-138. [6]: Rosei "Rose" 1. For all parts of this paper, 4LUT may be changed into "4-LUT". 2. Benchmark circuits and format type (.blif, .pla, etc.) should be changed into italicized ones because sometimes it may cause reader to confuse to recognize them. 3. In section 1, at the very beginning, after "Field programmable gate arrays", (FPGAs) 3. In 6th line of section 3.1, "and" -> "than" 4. In the 1st line of right column, page 2, there should be "space" between "cubes" and "(product terms)" 5.
[1] T. Sasao, "Easily testable realizations for generalized Reed-Muller expansions," IEEE Tr. on Comp., vol. 46, no. 6, pp. 709-716, June 1997. [2] F. Luccio and L. Pagli, "On a new Boolean function with applications," IEEE Tr. on Comp., vol. 48, no. 3, pp. 296-310, March 1999. [3] T. Sasao, Logic synthesis and optimization, Kluwer Academic Publishers, 1998. [4] S. B. Akers, "Functional testing with BDDs," 8th Annual Conference on FaultTolerant Computing, 1978, pp. 75-82. [5] Randal E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Tr. on Comp., Vol. 35, No. 8, pp. 677-691, August 1986. [6] S. Chang, M. Marek-Sadowska, and T. Hwang, "Technology mapping for LUT FPGAs based on decomposition of BDDs," IEEE Tran. on CAD, vol. 15, no. 10, pp. 1226-1235, October, 1996. General Comments: Your first drafted paper looks great. Keep up the good work!!