Handouts
EEE308 EEE308/804 Digital Electronics III
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This is achieved by:
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This module consists of two parts Design for Test (GR) and Introduction to VHDL (DJK) The Aims of the Introduction to VHDL are :
To build on previous lectures in Digital Design (Combinatorial Logic, FSMs etc.) To introduce the concept of a Hardware Design Language (VHDL) To give examples in Modelling using VHDL To explain the top down design philosophy of the language.
Describing how examples of logic and FSMs are modelled in the language. Explaining the tools and techniques used to execute the models Giving practice in encoding a simple example and running simple tools Describing and illustrating the test bench methodology and top down design Teaching is by a mixture of conventional lectures, use of CAL material, practice, tutorial, and student directed learning.
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Outcomes
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Teaching
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At the end of the course students should know: How simple examples of logic and FSMs are modelled in the language What is meant by Behaviour and Structure in VHDL How behavioural models are executed The philosophy of top down development and test using the language
Lectures
Introduction to design using a language Fundamentals of VHDL Simple examples in VHDL
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Lectures
Top down design, combinatorial logic, simple storage devices, concurrency, Finite State machines Testbenches
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CAL (optional for Undergraduates) Further material Book: VHDL: Hardware Description and Design, Roger Lipsett, Kluwer 1989 (in library) Notes on the web
http://www.staff.ncl.ac.uk/david.kinniment/Teaching/EEE308/EEE308index.htm 4
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Practical work
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Outline of Material and Presentation Schedule (provisional)
EEE308 Course 2004, 14:00 in L3.01, Practicals in Oracle Cluster
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Tutorial sessions be given over a period of 3 weeks using the ALDEC software on PC workstations, supported by predefined example files.
Use of VHDL tools in the modelling of some simple hardware Understanding of the testbench concept in practice
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Time available for interactive use of CAL Examples
Fri 1 Oct 9:00 Fri 8 Oct 14:00 Architectures Fri 15 Oct 14:00 Fri 22 Oct 14:00 Fri 29 Oct 14:00 Fri 5 Nov 14:00 Fri 12 Nov 14:00 Fri 19 Nov 9:00 Fri 19 Nov14:00 Fri 26 Nov 14:00 Fri 3 Dec14:00 Fri 10 Dec14:00
Introductory lecture What is VHDL? Entities and Modelling and simulation Combinatorial Logic Combinatorial Logic Sequential Systems Testbenches Practical Session in use Of VHDL Practical Session in use Of VHDL Practical Session in use Of VHDL Top down Design Top down design & Revision
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EEE308/804 Handouts
MSc material (EEE804) L2.02/Oracle
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Introduction: What is Design
The aim is to reconcile
WHAT is required with HOW it is to be achieved
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Fri Oct 1 Fri 15 Oct
10:00 10:00
L2.02 MSc Introductory lecture Oracle Demonstration of how to run courseware: Combinatorial Logic Daysh Concurrency Storage and Clocks Finite State Machines Students run exercises of material given using ALDEC software
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Fri 29 Oct Fri 12 Nov Fri 19 Nov Fri 10 Dec
10:00 10:00 10:00 10:00
Oracle Oracle Oracle Oracle
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The idea of top down design is to start with the BEHAVIOUR, i.e WHAT is required, and finish with a set of real components connected together in a STRUCTURE, i.e HOW it is to be built. This is an iterative process, solving many smaller design tasks.
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The Design Process
Behaviour and Structure
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Each iterative step starts with a specification and finishes with a number of components, which then have their own specification
Decide how to partition into major components Decide what these should do and how they are connected Verify that this combination of components actually does the same as the original specification
We need to be able to understand what the design is supposed to do without worrying about how we are going to do it
This simplifies the design process
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We need a way to model the behaviour simply and then simulate the behaviour by executing the model. We need to test models, or collections of models in a known environment
A test bench
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We need to assess different design alternatives for
Performance:- simulator cost:- Component library
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Why go to the trouble of a language and CAD tools?
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The design productivity problem
Some Design Tools
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Design Capture
Graphical, language
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Design Synthesis
Logic level, Algorithmic
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Verification, Perf...