Scan Lec-19: Testing
University of Waterloo Dept of Electrical and Computer Engineering Mark Aagaard E&CE 427 Digital Systems Engineering 2001-Fall
1 Introduction
1.1 Schedule
Design Techniques Performance Analysis and Prediction Timing Analysis Functional Validation Power-Aware Design Testability catching manufacturing faults Reliability Implementation Technologies
wk-01 04 wk-05 wk-06 wk-07 wk-08 wk-09 10 wk-11 wk-12
1.2
Schedule for Lectures on Testing
Lec-16 Overview Lec-17 Fault detection and test-vector generation Lec-18 Scan testing Lec-19 Built-In Self Test
1.3
Purpose and List of Concepts
The purpose of this lecture is to connect the theory of testing and testability to the current techniques of scan testing and the IEEE Standard 1149.1 (aka JTAG).
scan testing scan chain 1
E&CE 427: 2001-Fall: Lec-19
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2 Scan Testing in General
2.1 Normal Circuit
data_in(3) another circuit #0 zeta_in(3) another circuit #1
testing procedure time to run a test boundary scan testing JTAG IEEE 1149 length of time to do a scan test hardware to do scan testing
data_in(2) circuit under test
zeta_in(2)
data_in(1)
zeta_in(1)
data_in(0)
zeta_in(0)
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2.2
Circuit with Scan Chains Added
mode0 scan_in0 mode1 scan_in1
circuit under test
scan_out0
scan_out1
2.3
Structure and Behaviour of Scan Chains
mode0 scan_in0 mode1 scan_in1
yet another circuit zeta_in(3) zeta_in(2) zeta_in(1) zeta_in(0) scan_out1
another circuit
scan chain 0
data_in(3)
data_in(2)
circuit under test
data_in(1)
data_in(0) scan_out0
scan chain 1
E&CE 427: 2001-Fall: Lec-19
2.3.1 Circuitry in Normal and Scan Mode
mode1 scan_in1 mode0 scan_in0 mode1 scan_in1
4
mode0 scan_in0
circuit under test
circuit under test
scan_out0
scan_out1
scan_out0
scan_out1
Normal Mode
Scan Mode
2.4
2.4.1
Scan in Operation
Circuit Under Test and Scan Behaviour
clk
a b y z c d
mode0 scan_out0 scan_in0 scan_out1 scan_in1 previous results0 current vector0 previous results1 current vector1 current results0 next test vector0 current results1 next test vector1
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clk mode0 scan_out0 scan_in0 a b c d y z scan_out1 scan_in1 previous results current vector1 1 = + 2 = +
__
previous results0 1
current results0 next test vector0
2 1 2 1 next vector1
2.4.2
Circuit Under Test with Scan Circuitry
mode1 scan_in1 a y b z c
mode0 scan_in0
d
scan_out0
scan_out1
E&CE 427: 2001-Fall: Lec-19
2.4.3 Start Loading Test Vector (Load )
mode1 scan_in1 a y b z c
6
mode0 scan_in0
d
scan_out0 clk mode0
mode0 scan_in0 a
mode0
2.4.4
Load
b z c
d
scan_out0 clk
scan_out1
mode1 scan_in1
y
scan_out1
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mode0 scan_in0 a
mode0
mode0 scan_in0 a
mode0
2.4.6
Load
mode1 scan_in1 y b z c d scan_out0 clk scan_out1 mode1 scan_in1 y b z c d scan_out0 clk scan_out1
2.4.5
Load
E&CE 427: 2001-Fall: Lec-19
2.4.7 Run Test Vector
mode1 scan_in1
8
mode0 scan_in0
scan_out1
scan_out0 clk mode0
2.4.8
Test Values Propagate
mode1 scan_in1
mode0 scan_in0
__
+
__
__
+
__
scan_out1
scan_out0 clk mode0
E&CE 427: 2001-Fall: Lec-19
2.4.9 Flop-In Result, Start (Un)loading Test Vector
mode1 scan_in1
9
mode0 scan_in0
-
+
__
+
__
scan_out0 clk mode0
scan_out1 (+)
__
2.4.10
Continue (Un)loading Test Vector
mode1 scan_in1
mode0 scan_in0
__
+
scan_out0
__
scan_out1 (+, +)
__
clk mode0
E&CE 427: 2001-Fall: Lec-19
2.4.11 Continue (Un)loading Test Vector
mode1 scan_in1
10
mode0 scan_in0
scan_out0
__
scan_out1 (+, +)
__
clk mode0
2.4.12
Continue (Un)loading Test Vector
mode1 scan_in1
mode0 scan_in0
scan_out0
__
scan_out1 (+, +)
__
clk mode0
E&CE 427: 2001-Fall: Lec-19
2.4.13 Run Next Test Vector
mode1 scan_in1
11
mode0 scan_in0
scan_out0
__
scan_out1 (+, +)
__
clk mode0
2.5
Summary of Scan Testing
Adding scan circuitry 1. Registers around circuit to be tested are grouped into scan chains 2. Replace each op with mux + op 3. Flops and muxes wired together into scan chains 4. Each scan chain is connected to dedicated I/O pins for loading and unloading test vectors
Running test vectors 1. Put scan chain in scan mode 2. Load in test vector (one element vector of per clock cycle) 3. Put scan chain in normal mode 4. Run circuit for one clock cycle load result of test into ops 5. Unload results of current test vector while simultaneously loading in next test vector (one element of vector per clock cycle)
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2.6
Example: Time to Test a Chip
A 800MHz chip has scan chains of length 20,000 bits, 18,000 bits, 21,000 bits, 22,000 bits, and two of 15,000 bits. 500,000 test vectors are used for each scan chain. The tests are run at 80% of full speed. Calculate the total test time. We can load and unload all of the scan chains at the same time, so time will be limited by the longest (22,000 bits). For the rst test vector, we have to load it in, run the circuit for one clock cycle, then unload the result. Loading the second test vector is done while unloading the rst.
3 Boundary Scan
Boundary scan originated as technique to test wires on printed circuit boards (PCBs). Goal was to replace bed-of-nails style testing with technique that would work for high-density PCBs (lots of small wires close together) Now used to test both boards and chip internals. Used both on boundaries (I/O pins) and internal ops. Standardized by IEEE (1149) and previously by JTAG.
4 required signals
1 optional signal
protocol to connect circuit under test to tester and other circuits
state machine to drive test circuitry on chip
3.1
Boundary Scan History
1985 JETAG: Joint European Test Action Group 1986 JTAG (North American companies joined) 1990 JTAG 2.0 formed basis for IEEE 1491 Test access port and boundary scan architecture
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TimeTot
ClockPeriod
MaxLengthVec
NumVecs
MaxLengthVec
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3.2
TDI TDO TCK TMS
Scan Pins
test data input: input testvector to chip test data output: output result of test test clock: clock signal that test runs on test mode select: controls scan state machine test reset (optional): resets the scan state machine
TRST
S TR S TR S TR RVU S TR
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CHIP BSR
BSC circuit
BSC
BSC
BSC
BSC
BSC
TDI
BR
TDO
Instruction Decoder
IR IRC IRC
IDCODE TCK
TMS
TAP Controller
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3.3
TDR DR BSC
Scan Registers and Cells
Fig 14.8 Top level diagram Test data register The boundary scan registers on a chip Data register cell Often used as a Boundary scan cell (BSC) Boundary scan cell Connects external input and scan signal to internal circuit. Acts as wire between external input and...